Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8045087 |
1 |
|
|
T22 |
192 |
|
T23 |
149 |
|
T24 |
317 |
| auto[1] |
5949511 |
1 |
|
|
T23 |
131 |
|
T27 |
80 |
|
T29 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11546488 |
1 |
|
|
T22 |
192 |
|
T23 |
247 |
|
T24 |
317 |
| auto[1] |
2448110 |
1 |
|
|
T23 |
33 |
|
T27 |
86 |
|
T29 |
33 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8081505 |
1 |
|
|
T22 |
192 |
|
T23 |
145 |
|
T24 |
317 |
| auto[1] |
5913093 |
1 |
|
|
T23 |
135 |
|
T27 |
143 |
|
T29 |
59 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1723868 |
1 |
|
|
T23 |
43 |
|
T27 |
41 |
|
T29 |
6 |
| auto[1] |
auto[0] |
auto[1] |
1220239 |
1 |
|
|
T23 |
12 |
|
T27 |
48 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1741115 |
1 |
|
|
T23 |
59 |
|
T27 |
16 |
|
T29 |
20 |
| auto[1] |
auto[1] |
auto[1] |
1227871 |
1 |
|
|
T23 |
21 |
|
T27 |
38 |
|
T29 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |