Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8090334 |
1 |
|
|
T22 |
192 |
|
T23 |
173 |
|
T24 |
317 |
| auto[1] |
5904264 |
1 |
|
|
T23 |
107 |
|
T27 |
111 |
|
T29 |
125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11569575 |
1 |
|
|
T22 |
192 |
|
T23 |
217 |
|
T24 |
317 |
| auto[1] |
2425023 |
1 |
|
|
T23 |
63 |
|
T27 |
111 |
|
T29 |
48 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8136025 |
1 |
|
|
T22 |
192 |
|
T23 |
123 |
|
T24 |
317 |
| auto[1] |
5858573 |
1 |
|
|
T23 |
157 |
|
T27 |
165 |
|
T29 |
95 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1712542 |
1 |
|
|
T23 |
61 |
|
T27 |
15 |
|
T29 |
16 |
| auto[1] |
auto[0] |
auto[1] |
1212127 |
1 |
|
|
T23 |
32 |
|
T27 |
79 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1721008 |
1 |
|
|
T23 |
33 |
|
T27 |
39 |
|
T29 |
31 |
| auto[1] |
auto[1] |
auto[1] |
1212896 |
1 |
|
|
T23 |
31 |
|
T27 |
32 |
|
T29 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |