Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072928 |
1 |
|
|
T22 |
192 |
|
T23 |
182 |
|
T24 |
317 |
| auto[1] |
5921670 |
1 |
|
|
T23 |
98 |
|
T27 |
111 |
|
T29 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11554488 |
1 |
|
|
T22 |
192 |
|
T23 |
197 |
|
T24 |
317 |
| auto[1] |
2440110 |
1 |
|
|
T23 |
83 |
|
T27 |
68 |
|
T29 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8091416 |
1 |
|
|
T22 |
192 |
|
T23 |
157 |
|
T24 |
317 |
| auto[1] |
5903182 |
1 |
|
|
T23 |
123 |
|
T27 |
109 |
|
T29 |
94 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1731854 |
1 |
|
|
T23 |
29 |
|
T27 |
20 |
|
T29 |
21 |
| auto[1] |
auto[0] |
auto[1] |
1225492 |
1 |
|
|
T23 |
62 |
|
T27 |
28 |
|
T29 |
43 |
| auto[1] |
auto[1] |
auto[0] |
1731218 |
1 |
|
|
T23 |
11 |
|
T27 |
21 |
|
T29 |
8 |
| auto[1] |
auto[1] |
auto[1] |
1214618 |
1 |
|
|
T23 |
21 |
|
T27 |
40 |
|
T29 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |