Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8097912 |
1 |
|
|
T22 |
192 |
|
T23 |
127 |
|
T24 |
317 |
| auto[1] |
5896686 |
1 |
|
|
T23 |
153 |
|
T27 |
141 |
|
T29 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11546794 |
1 |
|
|
T22 |
192 |
|
T23 |
237 |
|
T24 |
317 |
| auto[1] |
2447804 |
1 |
|
|
T23 |
43 |
|
T27 |
53 |
|
T29 |
48 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8075223 |
1 |
|
|
T22 |
192 |
|
T23 |
171 |
|
T24 |
317 |
| auto[1] |
5919375 |
1 |
|
|
T23 |
109 |
|
T27 |
91 |
|
T29 |
103 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1740295 |
1 |
|
|
T23 |
27 |
|
T27 |
14 |
|
T29 |
45 |
| auto[1] |
auto[0] |
auto[1] |
1229246 |
1 |
|
|
T23 |
22 |
|
T27 |
17 |
|
T29 |
40 |
| auto[1] |
auto[1] |
auto[0] |
1731276 |
1 |
|
|
T23 |
39 |
|
T27 |
24 |
|
T29 |
10 |
| auto[1] |
auto[1] |
auto[1] |
1218558 |
1 |
|
|
T23 |
21 |
|
T27 |
36 |
|
T29 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |