Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8105100 |
1 |
|
|
T22 |
192 |
|
T23 |
157 |
|
T24 |
317 |
| auto[1] |
5889498 |
1 |
|
|
T23 |
123 |
|
T27 |
47 |
|
T29 |
98 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11565815 |
1 |
|
|
T22 |
192 |
|
T23 |
172 |
|
T24 |
317 |
| auto[1] |
2428783 |
1 |
|
|
T23 |
108 |
|
T27 |
58 |
|
T29 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8115579 |
1 |
|
|
T22 |
192 |
|
T23 |
89 |
|
T24 |
317 |
| auto[1] |
5879019 |
1 |
|
|
T23 |
191 |
|
T27 |
124 |
|
T29 |
48 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1719178 |
1 |
|
|
T23 |
38 |
|
T27 |
60 |
|
T29 |
7 |
| auto[1] |
auto[0] |
auto[1] |
1214623 |
1 |
|
|
T23 |
66 |
|
T27 |
35 |
|
T29 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1731058 |
1 |
|
|
T23 |
45 |
|
T27 |
6 |
|
T29 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1214160 |
1 |
|
|
T23 |
42 |
|
T27 |
23 |
|
T29 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |