Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072410 |
1 |
|
|
T22 |
192 |
|
T23 |
164 |
|
T24 |
317 |
| auto[1] |
5922188 |
1 |
|
|
T23 |
116 |
|
T27 |
133 |
|
T29 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11559785 |
1 |
|
|
T22 |
192 |
|
T23 |
238 |
|
T24 |
317 |
| auto[1] |
2434813 |
1 |
|
|
T23 |
42 |
|
T27 |
31 |
|
T29 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8094354 |
1 |
|
|
T22 |
192 |
|
T23 |
156 |
|
T24 |
317 |
| auto[1] |
5900244 |
1 |
|
|
T23 |
124 |
|
T27 |
70 |
|
T29 |
72 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1726579 |
1 |
|
|
T23 |
53 |
|
T27 |
23 |
|
T29 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1216162 |
1 |
|
|
T23 |
32 |
|
T27 |
10 |
|
T29 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1738852 |
1 |
|
|
T23 |
29 |
|
T27 |
16 |
|
T29 |
26 |
| auto[1] |
auto[1] |
auto[1] |
1218651 |
1 |
|
|
T23 |
10 |
|
T27 |
21 |
|
T29 |
25 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |