Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8085459 |
1 |
|
|
T22 |
192 |
|
T23 |
166 |
|
T24 |
317 |
| auto[1] |
5909139 |
1 |
|
|
T23 |
114 |
|
T27 |
72 |
|
T29 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11553887 |
1 |
|
|
T22 |
192 |
|
T23 |
194 |
|
T24 |
317 |
| auto[1] |
2440711 |
1 |
|
|
T23 |
86 |
|
T27 |
57 |
|
T29 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8095607 |
1 |
|
|
T22 |
192 |
|
T23 |
107 |
|
T24 |
317 |
| auto[1] |
5898991 |
1 |
|
|
T23 |
173 |
|
T27 |
120 |
|
T29 |
76 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1730468 |
1 |
|
|
T23 |
43 |
|
T27 |
43 |
|
T29 |
26 |
| auto[1] |
auto[0] |
auto[1] |
1225478 |
1 |
|
|
T23 |
54 |
|
T27 |
32 |
|
T29 |
29 |
| auto[1] |
auto[1] |
auto[0] |
1727812 |
1 |
|
|
T23 |
44 |
|
T27 |
20 |
|
T29 |
10 |
| auto[1] |
auto[1] |
auto[1] |
1215233 |
1 |
|
|
T23 |
32 |
|
T27 |
25 |
|
T29 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |