Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8083249 |
1 |
|
|
T22 |
192 |
|
T23 |
144 |
|
T24 |
317 |
| auto[1] |
5911349 |
1 |
|
|
T23 |
136 |
|
T27 |
99 |
|
T29 |
66 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11540804 |
1 |
|
|
T22 |
192 |
|
T23 |
177 |
|
T24 |
317 |
| auto[1] |
2453794 |
1 |
|
|
T23 |
103 |
|
T27 |
42 |
|
T29 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8064097 |
1 |
|
|
T22 |
192 |
|
T23 |
114 |
|
T24 |
317 |
| auto[1] |
5930501 |
1 |
|
|
T23 |
166 |
|
T27 |
96 |
|
T29 |
69 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1729547 |
1 |
|
|
T23 |
32 |
|
T27 |
31 |
|
T29 |
23 |
| auto[1] |
auto[0] |
auto[1] |
1224022 |
1 |
|
|
T23 |
49 |
|
T27 |
18 |
|
T29 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1747160 |
1 |
|
|
T23 |
31 |
|
T27 |
23 |
|
T29 |
18 |
| auto[1] |
auto[1] |
auto[1] |
1229772 |
1 |
|
|
T23 |
54 |
|
T27 |
24 |
|
T29 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |