Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8079436 |
1 |
|
|
T22 |
192 |
|
T23 |
146 |
|
T24 |
317 |
| auto[1] |
5915162 |
1 |
|
|
T23 |
134 |
|
T27 |
69 |
|
T29 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11568207 |
1 |
|
|
T22 |
192 |
|
T23 |
229 |
|
T24 |
317 |
| auto[1] |
2426391 |
1 |
|
|
T23 |
51 |
|
T27 |
81 |
|
T29 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8107299 |
1 |
|
|
T22 |
192 |
|
T23 |
136 |
|
T24 |
317 |
| auto[1] |
5887299 |
1 |
|
|
T23 |
144 |
|
T27 |
145 |
|
T29 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1729998 |
1 |
|
|
T23 |
54 |
|
T27 |
45 |
|
T29 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1213721 |
1 |
|
|
T23 |
23 |
|
T27 |
50 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1730910 |
1 |
|
|
T23 |
39 |
|
T27 |
19 |
|
T29 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1212670 |
1 |
|
|
T23 |
28 |
|
T27 |
31 |
|
T29 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |