Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8110583 |
1 |
|
|
T22 |
192 |
|
T23 |
120 |
|
T24 |
317 |
| auto[1] |
5884015 |
1 |
|
|
T23 |
160 |
|
T27 |
98 |
|
T29 |
60 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11561588 |
1 |
|
|
T22 |
192 |
|
T23 |
203 |
|
T24 |
317 |
| auto[1] |
2433010 |
1 |
|
|
T23 |
77 |
|
T27 |
46 |
|
T29 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8099893 |
1 |
|
|
T22 |
192 |
|
T23 |
131 |
|
T24 |
317 |
| auto[1] |
5894705 |
1 |
|
|
T23 |
149 |
|
T27 |
131 |
|
T29 |
62 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1737712 |
1 |
|
|
T23 |
30 |
|
T27 |
48 |
|
T29 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1218513 |
1 |
|
|
T23 |
24 |
|
T27 |
19 |
|
T29 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1723983 |
1 |
|
|
T23 |
42 |
|
T27 |
37 |
|
T29 |
8 |
| auto[1] |
auto[1] |
auto[1] |
1214497 |
1 |
|
|
T23 |
53 |
|
T27 |
27 |
|
T29 |
31 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |