Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8071746 |
1 |
|
|
T22 |
192 |
|
T23 |
86 |
|
T24 |
317 |
| auto[1] |
5922852 |
1 |
|
|
T23 |
194 |
|
T27 |
102 |
|
T29 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11545555 |
1 |
|
|
T22 |
192 |
|
T23 |
203 |
|
T24 |
317 |
| auto[1] |
2449043 |
1 |
|
|
T23 |
77 |
|
T27 |
63 |
|
T29 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8060786 |
1 |
|
|
T22 |
192 |
|
T23 |
134 |
|
T24 |
317 |
| auto[1] |
5933812 |
1 |
|
|
T23 |
146 |
|
T27 |
99 |
|
T29 |
80 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1733640 |
1 |
|
|
T23 |
17 |
|
T27 |
17 |
|
T29 |
63 |
| auto[1] |
auto[0] |
auto[1] |
1226254 |
1 |
|
|
T23 |
29 |
|
T27 |
45 |
|
T29 |
17 |
| auto[1] |
auto[1] |
auto[0] |
1751129 |
1 |
|
|
T23 |
52 |
|
T27 |
19 |
|
T1 |
48 |
| auto[1] |
auto[1] |
auto[1] |
1222789 |
1 |
|
|
T23 |
48 |
|
T27 |
18 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |