Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8087580 |
1 |
|
|
T22 |
192 |
|
T23 |
182 |
|
T24 |
317 |
| auto[1] |
5907018 |
1 |
|
|
T23 |
98 |
|
T27 |
119 |
|
T29 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11548122 |
1 |
|
|
T22 |
192 |
|
T23 |
181 |
|
T24 |
317 |
| auto[1] |
2446476 |
1 |
|
|
T23 |
99 |
|
T27 |
104 |
|
T29 |
63 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8080685 |
1 |
|
|
T22 |
192 |
|
T23 |
111 |
|
T24 |
317 |
| auto[1] |
5913913 |
1 |
|
|
T23 |
169 |
|
T27 |
150 |
|
T29 |
111 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1743992 |
1 |
|
|
T23 |
40 |
|
T27 |
15 |
|
T29 |
12 |
| auto[1] |
auto[0] |
auto[1] |
1228417 |
1 |
|
|
T23 |
75 |
|
T27 |
51 |
|
T29 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1723445 |
1 |
|
|
T23 |
30 |
|
T27 |
31 |
|
T29 |
36 |
| auto[1] |
auto[1] |
auto[1] |
1218059 |
1 |
|
|
T23 |
24 |
|
T27 |
53 |
|
T29 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |