Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8108521 |
1 |
|
|
T22 |
192 |
|
T23 |
132 |
|
T24 |
317 |
| auto[1] |
5886077 |
1 |
|
|
T23 |
148 |
|
T27 |
150 |
|
T29 |
72 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11548667 |
1 |
|
|
T22 |
192 |
|
T23 |
227 |
|
T24 |
317 |
| auto[1] |
2445931 |
1 |
|
|
T23 |
53 |
|
T27 |
71 |
|
T29 |
78 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8080302 |
1 |
|
|
T22 |
192 |
|
T23 |
188 |
|
T24 |
317 |
| auto[1] |
5914296 |
1 |
|
|
T23 |
92 |
|
T27 |
114 |
|
T29 |
91 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1745533 |
1 |
|
|
T23 |
22 |
|
T27 |
13 |
|
T29 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1227164 |
1 |
|
|
T23 |
6 |
|
T27 |
33 |
|
T29 |
39 |
| auto[1] |
auto[1] |
auto[0] |
1722832 |
1 |
|
|
T23 |
17 |
|
T27 |
30 |
|
T1 |
106 |
| auto[1] |
auto[1] |
auto[1] |
1218767 |
1 |
|
|
T23 |
47 |
|
T27 |
38 |
|
T29 |
39 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |