Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8049272 |
1 |
|
|
T22 |
192 |
|
T23 |
181 |
|
T24 |
317 |
| auto[1] |
5945326 |
1 |
|
|
T23 |
99 |
|
T27 |
92 |
|
T29 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11548613 |
1 |
|
|
T22 |
192 |
|
T23 |
225 |
|
T24 |
317 |
| auto[1] |
2445985 |
1 |
|
|
T23 |
55 |
|
T27 |
20 |
|
T29 |
44 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8070408 |
1 |
|
|
T22 |
192 |
|
T23 |
164 |
|
T24 |
317 |
| auto[1] |
5924190 |
1 |
|
|
T23 |
116 |
|
T27 |
111 |
|
T29 |
81 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1725115 |
1 |
|
|
T23 |
45 |
|
T27 |
62 |
|
T29 |
14 |
| auto[1] |
auto[0] |
auto[1] |
1215572 |
1 |
|
|
T23 |
29 |
|
T27 |
16 |
|
T29 |
32 |
| auto[1] |
auto[1] |
auto[0] |
1753090 |
1 |
|
|
T23 |
16 |
|
T27 |
29 |
|
T29 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1230413 |
1 |
|
|
T23 |
26 |
|
T27 |
4 |
|
T29 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |