Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8063405 |
1 |
|
|
T22 |
192 |
|
T23 |
91 |
|
T24 |
317 |
| auto[1] |
5931193 |
1 |
|
|
T23 |
189 |
|
T27 |
104 |
|
T29 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11548801 |
1 |
|
|
T22 |
192 |
|
T23 |
201 |
|
T24 |
317 |
| auto[1] |
2445797 |
1 |
|
|
T23 |
79 |
|
T27 |
85 |
|
T29 |
48 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8073358 |
1 |
|
|
T22 |
192 |
|
T23 |
146 |
|
T24 |
317 |
| auto[1] |
5921240 |
1 |
|
|
T23 |
134 |
|
T27 |
99 |
|
T29 |
105 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1740628 |
1 |
|
|
T23 |
16 |
|
T27 |
7 |
|
T29 |
39 |
| auto[1] |
auto[0] |
auto[1] |
1223221 |
1 |
|
|
T23 |
40 |
|
T27 |
47 |
|
T29 |
35 |
| auto[1] |
auto[1] |
auto[0] |
1734815 |
1 |
|
|
T23 |
39 |
|
T27 |
7 |
|
T29 |
18 |
| auto[1] |
auto[1] |
auto[1] |
1222576 |
1 |
|
|
T23 |
39 |
|
T27 |
38 |
|
T29 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |