Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8100001 |
1 |
|
|
T22 |
192 |
|
T23 |
205 |
|
T24 |
317 |
| auto[1] |
5894597 |
1 |
|
|
T23 |
75 |
|
T27 |
106 |
|
T29 |
108 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13234125 |
1 |
|
|
T22 |
192 |
|
T23 |
271 |
|
T24 |
317 |
| auto[1] |
760473 |
1 |
|
|
T23 |
9 |
|
T27 |
7 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8075101 |
1 |
|
|
T22 |
192 |
|
T23 |
146 |
|
T24 |
317 |
| auto[1] |
5919497 |
1 |
|
|
T23 |
134 |
|
T27 |
102 |
|
T29 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2590704 |
1 |
|
|
T23 |
123 |
|
T27 |
47 |
|
T29 |
22 |
| auto[1] |
auto[0] |
auto[1] |
381042 |
1 |
|
|
T23 |
9 |
|
T27 |
5 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2568320 |
1 |
|
|
T23 |
2 |
|
T27 |
48 |
|
T29 |
20 |
| auto[1] |
auto[1] |
auto[1] |
379431 |
1 |
|
|
T27 |
2 |
|
T29 |
3 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |