Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8074974 |
1 |
|
|
T22 |
192 |
|
T23 |
168 |
|
T24 |
317 |
| auto[1] |
5919624 |
1 |
|
|
T23 |
112 |
|
T27 |
108 |
|
T29 |
88 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13236214 |
1 |
|
|
T22 |
192 |
|
T23 |
273 |
|
T24 |
317 |
| auto[1] |
758384 |
1 |
|
|
T23 |
7 |
|
T27 |
5 |
|
T29 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8081146 |
1 |
|
|
T22 |
192 |
|
T23 |
154 |
|
T24 |
317 |
| auto[1] |
5913452 |
1 |
|
|
T23 |
126 |
|
T27 |
131 |
|
T29 |
66 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2581890 |
1 |
|
|
T23 |
79 |
|
T27 |
68 |
|
T29 |
26 |
| auto[1] |
auto[0] |
auto[1] |
380562 |
1 |
|
|
T23 |
6 |
|
T27 |
3 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2573178 |
1 |
|
|
T23 |
40 |
|
T27 |
58 |
|
T29 |
35 |
| auto[1] |
auto[1] |
auto[1] |
377822 |
1 |
|
|
T23 |
1 |
|
T27 |
2 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |