Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T104 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2896148284 Jun 24 04:44:59 PM PDT 24 Jun 24 04:45:04 PM PDT 24 235120684 ps
T763 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1590545016 Jun 24 04:44:55 PM PDT 24 Jun 24 04:45:01 PM PDT 24 81612216 ps
T764 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.675655677 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:49 PM PDT 24 424293257 ps
T98 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3864950904 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:49 PM PDT 24 33430903 ps
T99 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2674946122 Jun 24 04:44:57 PM PDT 24 Jun 24 04:45:01 PM PDT 24 122083694 ps
T100 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3707939896 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:12 PM PDT 24 31440449 ps
T765 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3795478112 Jun 24 04:45:08 PM PDT 24 Jun 24 04:45:10 PM PDT 24 14484733 ps
T766 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1862178254 Jun 24 04:44:56 PM PDT 24 Jun 24 04:45:01 PM PDT 24 107256134 ps
T84 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.881674254 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:50 PM PDT 24 397902413 ps
T767 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3533542555 Jun 24 04:45:20 PM PDT 24 Jun 24 04:45:25 PM PDT 24 34002175 ps
T768 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3653793699 Jun 24 04:44:51 PM PDT 24 Jun 24 04:44:57 PM PDT 24 72165003 ps
T769 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1451550058 Jun 24 04:45:10 PM PDT 24 Jun 24 04:45:14 PM PDT 24 31931774 ps
T770 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3514923429 Jun 24 04:44:58 PM PDT 24 Jun 24 04:45:03 PM PDT 24 21482701 ps
T771 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1345775844 Jun 24 04:45:11 PM PDT 24 Jun 24 04:45:15 PM PDT 24 86716219 ps
T85 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.559455778 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:49 PM PDT 24 57256967 ps
T772 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1195197318 Jun 24 04:45:10 PM PDT 24 Jun 24 04:45:13 PM PDT 24 30601462 ps
T773 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2381977903 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:48 PM PDT 24 112591538 ps
T774 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1423626971 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:12 PM PDT 24 25327212 ps
T775 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.733243637 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:13 PM PDT 24 56647939 ps
T776 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1719321888 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:13 PM PDT 24 18199917 ps
T777 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.866252654 Jun 24 04:44:50 PM PDT 24 Jun 24 04:44:55 PM PDT 24 117654356 ps
T778 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2970202937 Jun 24 04:44:42 PM PDT 24 Jun 24 04:44:46 PM PDT 24 73757106 ps
T779 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.124231524 Jun 24 04:44:52 PM PDT 24 Jun 24 04:44:58 PM PDT 24 36390491 ps
T780 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2640627251 Jun 24 04:45:13 PM PDT 24 Jun 24 04:45:19 PM PDT 24 77830702 ps
T781 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1962599110 Jun 24 04:44:58 PM PDT 24 Jun 24 04:45:01 PM PDT 24 23741348 ps
T86 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2192759509 Jun 24 04:44:42 PM PDT 24 Jun 24 04:44:45 PM PDT 24 48577126 ps
T87 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3675846543 Jun 24 04:44:42 PM PDT 24 Jun 24 04:44:47 PM PDT 24 15704927 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1549748718 Jun 24 04:44:41 PM PDT 24 Jun 24 04:44:44 PM PDT 24 27393096 ps
T88 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3911124773 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:50 PM PDT 24 1303114930 ps
T783 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1080979195 Jun 24 04:45:16 PM PDT 24 Jun 24 04:45:22 PM PDT 24 15157044 ps
T784 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1346403561 Jun 24 04:44:51 PM PDT 24 Jun 24 04:44:56 PM PDT 24 62116666 ps
T785 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2837621578 Jun 24 04:44:53 PM PDT 24 Jun 24 04:44:59 PM PDT 24 23428003 ps
T786 /workspace/coverage/cover_reg_top/30.gpio_intr_test.375134587 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:13 PM PDT 24 23272665 ps
T787 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.338468930 Jun 24 04:44:56 PM PDT 24 Jun 24 04:45:01 PM PDT 24 408174738 ps
T788 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3855842407 Jun 24 04:44:42 PM PDT 24 Jun 24 04:44:45 PM PDT 24 93382888 ps
T789 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3878725802 Jun 24 04:44:49 PM PDT 24 Jun 24 04:44:54 PM PDT 24 125860430 ps
T790 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.512800727 Jun 24 04:44:58 PM PDT 24 Jun 24 04:45:03 PM PDT 24 72458993 ps
T791 /workspace/coverage/cover_reg_top/33.gpio_intr_test.291235986 Jun 24 04:45:18 PM PDT 24 Jun 24 04:45:24 PM PDT 24 12547007 ps
T792 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1834807989 Jun 24 04:44:50 PM PDT 24 Jun 24 04:44:55 PM PDT 24 16087263 ps
T793 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2973040831 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:48 PM PDT 24 23190930 ps
T794 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.998039520 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:12 PM PDT 24 27084740 ps
T795 /workspace/coverage/cover_reg_top/43.gpio_intr_test.418583671 Jun 24 04:45:17 PM PDT 24 Jun 24 04:45:23 PM PDT 24 37403426 ps
T796 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3348701371 Jun 24 04:44:48 PM PDT 24 Jun 24 04:44:54 PM PDT 24 96236682 ps
T797 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1015507365 Jun 24 04:44:51 PM PDT 24 Jun 24 04:44:56 PM PDT 24 17768958 ps
T798 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3439987207 Jun 24 04:44:55 PM PDT 24 Jun 24 04:45:00 PM PDT 24 88260323 ps
T799 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3394778851 Jun 24 04:45:00 PM PDT 24 Jun 24 04:45:03 PM PDT 24 13279467 ps
T800 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.441294730 Jun 24 04:45:12 PM PDT 24 Jun 24 04:45:17 PM PDT 24 19403974 ps
T801 /workspace/coverage/cover_reg_top/28.gpio_intr_test.359231555 Jun 24 04:45:06 PM PDT 24 Jun 24 04:45:08 PM PDT 24 117968871 ps
T802 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1993990802 Jun 24 04:44:49 PM PDT 24 Jun 24 04:44:54 PM PDT 24 14591658 ps
T803 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2846768277 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:48 PM PDT 24 59268350 ps
T804 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.751967835 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:49 PM PDT 24 54765627 ps
T805 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1053732340 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:48 PM PDT 24 36385578 ps
T806 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1773849372 Jun 24 04:44:50 PM PDT 24 Jun 24 04:44:55 PM PDT 24 10813559 ps
T807 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1964206758 Jun 24 04:44:45 PM PDT 24 Jun 24 04:44:51 PM PDT 24 67459106 ps
T808 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3572771871 Jun 24 04:44:41 PM PDT 24 Jun 24 04:44:46 PM PDT 24 5001977685 ps
T809 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1598582379 Jun 24 04:45:18 PM PDT 24 Jun 24 04:45:23 PM PDT 24 15146796 ps
T810 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1863385773 Jun 24 04:44:55 PM PDT 24 Jun 24 04:45:00 PM PDT 24 66009765 ps
T811 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3050421532 Jun 24 04:44:48 PM PDT 24 Jun 24 04:44:54 PM PDT 24 25182859 ps
T89 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2473926496 Jun 24 04:44:57 PM PDT 24 Jun 24 04:45:01 PM PDT 24 41428107 ps
T812 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.512703876 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:49 PM PDT 24 129055039 ps
T813 /workspace/coverage/cover_reg_top/42.gpio_intr_test.729941092 Jun 24 04:45:19 PM PDT 24 Jun 24 04:45:24 PM PDT 24 12580376 ps
T814 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3069134050 Jun 24 04:44:40 PM PDT 24 Jun 24 04:44:42 PM PDT 24 60688942 ps
T815 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.56882862 Jun 24 04:44:42 PM PDT 24 Jun 24 04:44:47 PM PDT 24 58520407 ps
T816 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3574596339 Jun 24 04:44:50 PM PDT 24 Jun 24 04:44:55 PM PDT 24 88464397 ps
T817 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2151295676 Jun 24 04:45:22 PM PDT 24 Jun 24 04:45:27 PM PDT 24 112293086 ps
T818 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3985796807 Jun 24 04:44:57 PM PDT 24 Jun 24 04:45:02 PM PDT 24 78864712 ps
T819 /workspace/coverage/cover_reg_top/29.gpio_intr_test.393824986 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:13 PM PDT 24 23849546 ps
T820 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2289348577 Jun 24 04:44:46 PM PDT 24 Jun 24 04:44:53 PM PDT 24 212225496 ps
T821 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.678614747 Jun 24 04:45:00 PM PDT 24 Jun 24 04:45:03 PM PDT 24 31342723 ps
T822 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3138537030 Jun 24 04:45:20 PM PDT 24 Jun 24 04:45:25 PM PDT 24 12668521 ps
T823 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2445908037 Jun 24 04:44:43 PM PDT 24 Jun 24 04:44:51 PM PDT 24 226902450 ps
T824 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1102510460 Jun 24 04:44:44 PM PDT 24 Jun 24 04:44:52 PM PDT 24 261538649 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.235337749 Jun 24 04:44:41 PM PDT 24 Jun 24 04:44:44 PM PDT 24 69985368 ps
T826 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.428680667 Jun 24 04:45:09 PM PDT 24 Jun 24 04:45:12 PM PDT 24 61671039 ps
T827 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1715417942 Jun 24 04:44:58 PM PDT 24 Jun 24 04:45:02 PM PDT 24 76926690 ps
T828 /workspace/coverage/cover_reg_top/45.gpio_intr_test.3742087015 Jun 24 04:45:21 PM PDT 24 Jun 24 04:45:26 PM PDT 24 36324177 ps
T829 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1911916084 Jun 24 04:45:20 PM PDT 24 Jun 24 04:45:25 PM PDT 24 21737252 ps
T830 /workspace/coverage/cover_reg_top/21.gpio_intr_test.649799364 Jun 24 04:45:12 PM PDT 24 Jun 24 04:45:17 PM PDT 24 25096550 ps
T831 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3075141924 Jun 24 04:44:52 PM PDT 24 Jun 24 04:44:58 PM PDT 24 152778704 ps
T832 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3556349482 Jun 24 04:44:47 PM PDT 24 Jun 24 04:44:53 PM PDT 24 368248839 ps
T833 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2708814375 Jun 24 04:45:02 PM PDT 24 Jun 24 04:45:06 PM PDT 24 119393306 ps
T834 /workspace/coverage/cover_reg_top/15.gpio_intr_test.789118060 Jun 24 04:44:58 PM PDT 24 Jun 24 04:45:01 PM PDT 24 61103919 ps
T835 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1413381738 Jun 24 04:44:51 PM PDT 24 Jun 24 04:44:56 PM PDT 24 170804944 ps
T836 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.41734232 Jun 24 04:44:51 PM PDT 24 Jun 24 04:44:57 PM PDT 24 64246428 ps
T90 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.127325514 Jun 24 04:44:50 PM PDT 24 Jun 24 04:44:55 PM PDT 24 54990078 ps
T837 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.295981091 Jun 24 04:45:10 PM PDT 24 Jun 24 04:45:15 PM PDT 24 80065471 ps
T838 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1915322964 Jun 24 04:45:00 PM PDT 24 Jun 24 04:45:04 PM PDT 24 299069096 ps
T839 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1995968621 Jun 24 04:44:41 PM PDT 24 Jun 24 04:44:44 PM PDT 24 118424651 ps
T840 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1073811620 Jun 24 04:44:53 PM PDT 24 Jun 24 04:44:58 PM PDT 24 77061807 ps
T841 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2626157714 Jun 24 04:44:44 PM PDT 24 Jun 24 04:44:50 PM PDT 24 11854893 ps
T842 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1677296492 Jun 24 04:44:41 PM PDT 24 Jun 24 04:44:44 PM PDT 24 38681481 ps
T91 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.981318289 Jun 24 04:44:41 PM PDT 24 Jun 24 04:44:44 PM PDT 24 59609965 ps
T843 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1989220128 Jun 24 04:44:59 PM PDT 24 Jun 24 04:45:03 PM PDT 24 14891393 ps
T844 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4117712998 Jun 24 06:02:53 PM PDT 24 Jun 24 06:02:55 PM PDT 24 188527904 ps
T845 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1607222815 Jun 24 06:02:40 PM PDT 24 Jun 24 06:02:43 PM PDT 24 54202121 ps
T846 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4021303922 Jun 24 06:02:51 PM PDT 24 Jun 24 06:02:53 PM PDT 24 1072304871 ps
T847 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986800685 Jun 24 06:02:54 PM PDT 24 Jun 24 06:02:56 PM PDT 24 38367457 ps
T848 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3816722369 Jun 24 06:02:43 PM PDT 24 Jun 24 06:02:48 PM PDT 24 178628151 ps
T849 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2302824454 Jun 24 06:02:52 PM PDT 24 Jun 24 06:02:54 PM PDT 24 74945004 ps
T850 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3643167907 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:34 PM PDT 24 277570475 ps
T851 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2010476504 Jun 24 06:02:52 PM PDT 24 Jun 24 06:02:55 PM PDT 24 449501972 ps
T852 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.894653465 Jun 24 06:02:57 PM PDT 24 Jun 24 06:02:58 PM PDT 24 74786568 ps
T853 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2968712771 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 837572232 ps
T854 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.20915184 Jun 24 06:02:44 PM PDT 24 Jun 24 06:02:48 PM PDT 24 347008489 ps
T855 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3702556882 Jun 24 06:02:57 PM PDT 24 Jun 24 06:02:59 PM PDT 24 150385000 ps
T856 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1647925810 Jun 24 06:02:56 PM PDT 24 Jun 24 06:02:58 PM PDT 24 115810754 ps
T857 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2215260204 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:46 PM PDT 24 1861132484 ps
T858 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3392124 Jun 24 06:03:00 PM PDT 24 Jun 24 06:03:01 PM PDT 24 111948513 ps
T859 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1527564510 Jun 24 06:02:53 PM PDT 24 Jun 24 06:02:55 PM PDT 24 80474640 ps
T860 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.314656217 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:47 PM PDT 24 46468720 ps
T861 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2170479011 Jun 24 06:02:30 PM PDT 24 Jun 24 06:02:32 PM PDT 24 44035402 ps
T862 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2289809942 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 466417535 ps
T863 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2262117900 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:35 PM PDT 24 51283411 ps
T864 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1906106004 Jun 24 06:02:30 PM PDT 24 Jun 24 06:02:32 PM PDT 24 86608774 ps
T865 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1565881564 Jun 24 06:02:31 PM PDT 24 Jun 24 06:02:34 PM PDT 24 115686471 ps
T866 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983625338 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:35 PM PDT 24 87750138 ps
T867 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3205568880 Jun 24 06:02:49 PM PDT 24 Jun 24 06:02:51 PM PDT 24 56869830 ps
T868 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3485086293 Jun 24 06:02:29 PM PDT 24 Jun 24 06:02:31 PM PDT 24 222875886 ps
T869 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3954854085 Jun 24 06:02:43 PM PDT 24 Jun 24 06:02:48 PM PDT 24 285126291 ps
T870 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3889951385 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 209101019 ps
T871 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2981255240 Jun 24 06:02:50 PM PDT 24 Jun 24 06:02:52 PM PDT 24 855248032 ps
T872 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.230308863 Jun 24 06:02:31 PM PDT 24 Jun 24 06:02:33 PM PDT 24 87276982 ps
T873 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1617286128 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:45 PM PDT 24 109573714 ps
T874 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1175358041 Jun 24 06:02:44 PM PDT 24 Jun 24 06:02:48 PM PDT 24 225488116 ps
T875 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4285109315 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 125926695 ps
T876 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1634026002 Jun 24 06:02:43 PM PDT 24 Jun 24 06:02:47 PM PDT 24 223181284 ps
T877 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.604501964 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 85029384 ps
T878 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2146948936 Jun 24 06:02:43 PM PDT 24 Jun 24 06:02:47 PM PDT 24 49039580 ps
T879 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735263849 Jun 24 06:02:57 PM PDT 24 Jun 24 06:02:59 PM PDT 24 32954382 ps
T880 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.686506011 Jun 24 06:02:34 PM PDT 24 Jun 24 06:02:36 PM PDT 24 305428080 ps
T881 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3272225376 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 120689772 ps
T882 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.681916249 Jun 24 06:02:35 PM PDT 24 Jun 24 06:02:37 PM PDT 24 182448367 ps
T883 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4112481328 Jun 24 06:03:00 PM PDT 24 Jun 24 06:03:02 PM PDT 24 34648922 ps
T884 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.707805358 Jun 24 06:02:44 PM PDT 24 Jun 24 06:02:48 PM PDT 24 79751174 ps
T885 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.770749742 Jun 24 06:02:52 PM PDT 24 Jun 24 06:02:55 PM PDT 24 130157244 ps
T886 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1168899691 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 80111883 ps
T887 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2203848623 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:47 PM PDT 24 66393541 ps
T888 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1483071941 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 349842322 ps
T889 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1160366519 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:35 PM PDT 24 91801497 ps
T890 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3896803714 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 243813863 ps
T891 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2050230094 Jun 24 06:02:43 PM PDT 24 Jun 24 06:02:47 PM PDT 24 139264971 ps
T892 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2740111754 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:46 PM PDT 24 52244628 ps
T893 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.358323114 Jun 24 06:02:31 PM PDT 24 Jun 24 06:02:34 PM PDT 24 48458563 ps
T894 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2164091135 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:46 PM PDT 24 106424622 ps
T895 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730104201 Jun 24 06:02:39 PM PDT 24 Jun 24 06:02:41 PM PDT 24 150356594 ps
T896 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2977500144 Jun 24 06:02:50 PM PDT 24 Jun 24 06:02:52 PM PDT 24 273828175 ps
T897 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3478129449 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:35 PM PDT 24 38153849 ps
T898 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3553301649 Jun 24 06:02:52 PM PDT 24 Jun 24 06:02:54 PM PDT 24 125850517 ps
T899 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1852977582 Jun 24 06:02:29 PM PDT 24 Jun 24 06:02:32 PM PDT 24 54413405 ps
T900 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2426088179 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:35 PM PDT 24 264847609 ps
T901 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.899340391 Jun 24 06:02:43 PM PDT 24 Jun 24 06:02:47 PM PDT 24 70191596 ps
T902 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3685144449 Jun 24 06:03:03 PM PDT 24 Jun 24 06:03:05 PM PDT 24 44640707 ps
T903 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1695025092 Jun 24 06:02:53 PM PDT 24 Jun 24 06:02:55 PM PDT 24 613722678 ps
T904 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398172286 Jun 24 06:02:54 PM PDT 24 Jun 24 06:02:56 PM PDT 24 35133530 ps
T905 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1105529243 Jun 24 06:02:53 PM PDT 24 Jun 24 06:02:55 PM PDT 24 292172191 ps
T906 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3107678236 Jun 24 06:02:52 PM PDT 24 Jun 24 06:02:54 PM PDT 24 195700490 ps
T907 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2320926857 Jun 24 06:02:53 PM PDT 24 Jun 24 06:02:55 PM PDT 24 57533663 ps
T908 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2402002854 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 251080723 ps
T909 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1875497545 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:34 PM PDT 24 72894555 ps
T910 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3012533836 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:47 PM PDT 24 378103685 ps
T911 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.233871955 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:46 PM PDT 24 35547185 ps
T912 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1948793473 Jun 24 06:02:43 PM PDT 24 Jun 24 06:02:48 PM PDT 24 185272958 ps
T913 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1678079612 Jun 24 06:02:57 PM PDT 24 Jun 24 06:02:58 PM PDT 24 122040405 ps
T914 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3337290864 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:34 PM PDT 24 254115306 ps
T915 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2099608772 Jun 24 06:02:52 PM PDT 24 Jun 24 06:02:54 PM PDT 24 185656261 ps
T916 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4050282500 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 86749205 ps
T917 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4077578114 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 78999102 ps
T918 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2981948147 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 113729922 ps
T919 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4256653315 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 516174085 ps
T920 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1813348336 Jun 24 06:02:31 PM PDT 24 Jun 24 06:02:33 PM PDT 24 79898635 ps
T921 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3847836071 Jun 24 06:02:40 PM PDT 24 Jun 24 06:02:42 PM PDT 24 94750248 ps
T922 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.854178284 Jun 24 06:02:29 PM PDT 24 Jun 24 06:02:31 PM PDT 24 86037606 ps
T923 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1332437476 Jun 24 06:02:51 PM PDT 24 Jun 24 06:02:53 PM PDT 24 70730131 ps
T924 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2990717883 Jun 24 06:02:44 PM PDT 24 Jun 24 06:02:48 PM PDT 24 99379193 ps
T925 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1706251215 Jun 24 06:02:51 PM PDT 24 Jun 24 06:02:53 PM PDT 24 338736798 ps
T926 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.967982746 Jun 24 06:02:52 PM PDT 24 Jun 24 06:02:54 PM PDT 24 36344878 ps
T927 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2061761336 Jun 24 06:02:31 PM PDT 24 Jun 24 06:02:33 PM PDT 24 93704136 ps
T928 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2574738747 Jun 24 06:02:50 PM PDT 24 Jun 24 06:02:52 PM PDT 24 29166073 ps
T929 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3901527842 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:46 PM PDT 24 91565969 ps
T930 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2922941209 Jun 24 06:02:41 PM PDT 24 Jun 24 06:02:44 PM PDT 24 146799693 ps
T931 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2126436103 Jun 24 06:03:01 PM PDT 24 Jun 24 06:03:03 PM PDT 24 93208778 ps
T932 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3395647260 Jun 24 06:02:34 PM PDT 24 Jun 24 06:02:37 PM PDT 24 126216701 ps
T933 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4042420186 Jun 24 06:02:54 PM PDT 24 Jun 24 06:02:56 PM PDT 24 197336698 ps
T934 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2309934084 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 75942671 ps
T935 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211952697 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:46 PM PDT 24 56877620 ps
T936 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2915475113 Jun 24 06:02:51 PM PDT 24 Jun 24 06:02:53 PM PDT 24 57708743 ps
T937 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3989223496 Jun 24 06:02:42 PM PDT 24 Jun 24 06:02:45 PM PDT 24 60832550 ps
T938 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2846184533 Jun 24 06:02:50 PM PDT 24 Jun 24 06:02:52 PM PDT 24 31113928 ps
T939 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2767407223 Jun 24 06:02:32 PM PDT 24 Jun 24 06:02:35 PM PDT 24 137769617 ps
T940 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.438270587 Jun 24 06:02:33 PM PDT 24 Jun 24 06:02:36 PM PDT 24 184647163 ps
T941 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4072489584 Jun 24 06:02:51 PM PDT 24 Jun 24 06:02:53 PM PDT 24 65174053 ps
T942 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3334490812 Jun 24 06:02:37 PM PDT 24 Jun 24 06:02:38 PM PDT 24 119753795 ps
T943 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.730466144 Jun 24 06:02:50 PM PDT 24 Jun 24 06:02:52 PM PDT 24 70078711 ps

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1528638056
Short name T1
Test name
Test status
Simulation time 214228229 ps
CPU time 1.48 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:19:52 PM PDT 24
Peak memory 197784 kb
Host smart-c59d5e48-5e40-4aa3-9919-eb83e9bcdf29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528638056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1528638056
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3913902475
Short name T30
Test name
Test status
Simulation time 43508558 ps
CPU time 0.99 seconds
Started Jun 24 05:18:49 PM PDT 24
Finished Jun 24 05:18:51 PM PDT 24
Peak memory 196124 kb
Host smart-12822188-2a54-47cf-948f-2dc8da7f7eb7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913902475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3913902475
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1833961152
Short name T3
Test name
Test status
Simulation time 30157254573 ps
CPU time 386.19 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:24:55 PM PDT 24
Peak memory 198200 kb
Host smart-9c1fbbcd-3cd2-4a49-b26d-08864b702121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1833961152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1833961152
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.298138710
Short name T37
Test name
Test status
Simulation time 456264233 ps
CPU time 0.94 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:29 PM PDT 24
Peak memory 214764 kb
Host smart-a9d2c5b2-1219-4963-8d2e-479769eba199
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298138710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.298138710
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1901629642
Short name T76
Test name
Test status
Simulation time 39558014 ps
CPU time 0.67 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 194604 kb
Host smart-2dec2be1-1c1a-408b-aa29-b7a74f7d49d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901629642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1901629642
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.384802710
Short name T41
Test name
Test status
Simulation time 151568936 ps
CPU time 1.47 seconds
Started Jun 24 04:44:53 PM PDT 24
Finished Jun 24 04:44:59 PM PDT 24
Peak memory 197672 kb
Host smart-88a01766-a7e6-4fee-93b2-094f3fd1c8e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384802710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.384802710
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1325422142
Short name T26
Test name
Test status
Simulation time 15943133 ps
CPU time 0.61 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 193864 kb
Host smart-e139f117-27f3-4d22-9902-90ccfd27728e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325422142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1325422142
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.811920907
Short name T12
Test name
Test status
Simulation time 351335092 ps
CPU time 4.3 seconds
Started Jun 24 05:19:33 PM PDT 24
Finished Jun 24 05:19:37 PM PDT 24
Peak memory 197892 kb
Host smart-87d35131-5c58-408d-bcf3-9fd65b01d4c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811920907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.811920907
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3864950904
Short name T98
Test name
Test status
Simulation time 33430903 ps
CPU time 0.74 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 195840 kb
Host smart-f0e4db4e-e948-4bbf-add7-575b5ef6078f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864950904 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3864950904
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.4282668923
Short name T43
Test name
Test status
Simulation time 290514857 ps
CPU time 1.11 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 197640 kb
Host smart-df7615cc-a90b-4331-a743-acd851ed2953
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282668923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.4282668923
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1995968621
Short name T839
Test name
Test status
Simulation time 118424651 ps
CPU time 1.44 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 197708 kb
Host smart-adf58dad-a71a-4651-a2ef-16f7d0c98232
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995968621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1995968621
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.981318289
Short name T91
Test name
Test status
Simulation time 59609965 ps
CPU time 0.81 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 195612 kb
Host smart-8a3b4851-5f3b-47be-a8e8-461a4ee7ca45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981318289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.981318289
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3911124773
Short name T88
Test name
Test status
Simulation time 1303114930 ps
CPU time 2.84 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 196536 kb
Host smart-4947bd69-fb8b-4b7e-b08d-b7326a722989
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911124773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3911124773
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1168471652
Short name T740
Test name
Test status
Simulation time 13862593 ps
CPU time 0.61 seconds
Started Jun 24 04:44:44 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 194184 kb
Host smart-b6e3fa27-8380-4783-9702-969c4b762055
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168471652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1168471652
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.512703876
Short name T812
Test name
Test status
Simulation time 129055039 ps
CPU time 1.49 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 197728 kb
Host smart-4eb99ae9-bb05-42b8-b209-f763cacca695
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512703876 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.512703876
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.454416534
Short name T749
Test name
Test status
Simulation time 55467143 ps
CPU time 0.66 seconds
Started Jun 24 04:44:34 PM PDT 24
Finished Jun 24 04:44:39 PM PDT 24
Peak memory 194496 kb
Host smart-f2e77be6-a656-4f8b-875e-e7a90c07a1e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454416534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.454416534
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2970202937
Short name T778
Test name
Test status
Simulation time 73757106 ps
CPU time 0.58 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 193992 kb
Host smart-d45d4a21-d92e-4151-9202-bfa368095beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970202937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2970202937
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.819549915
Short name T728
Test name
Test status
Simulation time 99599803 ps
CPU time 2.69 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 197664 kb
Host smart-b939d8d8-de60-43d7-be3e-79f16bfeca68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819549915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.819549915
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.235337749
Short name T825
Test name
Test status
Simulation time 69985368 ps
CPU time 0.66 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 194264 kb
Host smart-2b67c660-3564-475f-9aac-8f3ac8d4c991
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235337749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.235337749
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.881674254
Short name T84
Test name
Test status
Simulation time 397902413 ps
CPU time 1.51 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 196916 kb
Host smart-e608598a-f87e-4e63-8bed-d96115bf19ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881674254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.881674254
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.559455778
Short name T85
Test name
Test status
Simulation time 57256967 ps
CPU time 0.64 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 194140 kb
Host smart-38b6b0f4-7451-454f-80ce-5f185158ed8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559455778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.559455778
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2381977903
Short name T773
Test name
Test status
Simulation time 112591538 ps
CPU time 0.81 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 197588 kb
Host smart-c6807efe-ae0f-48cb-88b8-03bcc8b99b13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381977903 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2381977903
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2973040831
Short name T793
Test name
Test status
Simulation time 23190930 ps
CPU time 0.59 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 195052 kb
Host smart-80007de3-8c70-4ad9-8443-9c09877a8c2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973040831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2973040831
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2626157714
Short name T841
Test name
Test status
Simulation time 11854893 ps
CPU time 0.57 seconds
Started Jun 24 04:44:44 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 193316 kb
Host smart-f287aa56-71c4-48ec-9a20-5cc804e41037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626157714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2626157714
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.751967835
Short name T804
Test name
Test status
Simulation time 54765627 ps
CPU time 0.72 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 196380 kb
Host smart-7dd6bafa-61d4-4493-9989-a816d7a2edf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751967835 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.751967835
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.3902570699
Short name T718
Test name
Test status
Simulation time 73342720 ps
CPU time 1.52 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 197644 kb
Host smart-873c55bc-0f2f-42c0-a0d4-1c7c74f97084
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902570699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.3902570699
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1346403561
Short name T784
Test name
Test status
Simulation time 62116666 ps
CPU time 0.86 seconds
Started Jun 24 04:44:51 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 197472 kb
Host smart-59a33abb-93ce-40b0-898c-78d23f0ac6cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346403561 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1346403561
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.866252654
Short name T777
Test name
Test status
Simulation time 117654356 ps
CPU time 0.58 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 194164 kb
Host smart-992cf166-67f1-4db2-afef-2d38c5e3e053
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866252654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.866252654
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.732541454
Short name T738
Test name
Test status
Simulation time 46536738 ps
CPU time 0.64 seconds
Started Jun 24 04:44:51 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 193996 kb
Host smart-d96abc8a-1fe1-4aab-aca3-c72ca8e3fd7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732541454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.732541454
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2870324412
Short name T94
Test name
Test status
Simulation time 25304769 ps
CPU time 0.69 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 194980 kb
Host smart-7e469c56-8fab-4376-a348-3dd762b34cf7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870324412 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2870324412
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2199813037
Short name T745
Test name
Test status
Simulation time 130584206 ps
CPU time 1.32 seconds
Started Jun 24 04:44:55 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 197656 kb
Host smart-02f5bb67-d86d-4d61-a2e9-e139b741a24f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199813037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2199813037
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3439987207
Short name T798
Test name
Test status
Simulation time 88260323 ps
CPU time 0.74 seconds
Started Jun 24 04:44:55 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 197452 kb
Host smart-8c68a1ce-2af5-473b-bc01-5b9151aa2d20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439987207 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3439987207
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1773849372
Short name T806
Test name
Test status
Simulation time 10813559 ps
CPU time 0.62 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 192904 kb
Host smart-b6e378ab-36c6-470d-9565-664dcc5a56f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773849372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1773849372
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2501304032
Short name T729
Test name
Test status
Simulation time 36795974 ps
CPU time 0.61 seconds
Started Jun 24 04:44:56 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 193244 kb
Host smart-bcdc8170-7b1f-456d-907c-1acaa80a8e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501304032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2501304032
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2592036267
Short name T92
Test name
Test status
Simulation time 66252402 ps
CPU time 0.84 seconds
Started Jun 24 04:44:48 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 197420 kb
Host smart-5125c3aa-6a21-49b8-82f4-8bfce8c05380
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592036267 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2592036267
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3985796807
Short name T818
Test name
Test status
Simulation time 78864712 ps
CPU time 1.79 seconds
Started Jun 24 04:44:57 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 197744 kb
Host smart-7a9359ed-d46e-49d8-927f-50eb200f6bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985796807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3985796807
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1915322964
Short name T838
Test name
Test status
Simulation time 299069096 ps
CPU time 1.41 seconds
Started Jun 24 04:45:00 PM PDT 24
Finished Jun 24 04:45:04 PM PDT 24
Peak memory 197608 kb
Host smart-0d81b107-560e-49c4-a36e-4ce41a9a4c98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915322964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1915322964
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2576666905
Short name T735
Test name
Test status
Simulation time 245339883 ps
CPU time 0.86 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 197508 kb
Host smart-a9ab2de9-0228-4cb7-897d-d99fad539ebe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576666905 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2576666905
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.678614747
Short name T821
Test name
Test status
Simulation time 31342723 ps
CPU time 0.6 seconds
Started Jun 24 04:45:00 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 192932 kb
Host smart-a1b54dac-26a0-4a76-b594-82d83f6f06bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678614747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.678614747
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1501336235
Short name T734
Test name
Test status
Simulation time 14847212 ps
CPU time 0.61 seconds
Started Jun 24 04:44:57 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 193376 kb
Host smart-3def7a5f-0965-4c18-b637-f921fb06620e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501336235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1501336235
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2674946122
Short name T99
Test name
Test status
Simulation time 122083694 ps
CPU time 0.71 seconds
Started Jun 24 04:44:57 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 195820 kb
Host smart-cec4e8c8-fac8-4b3c-a6aa-4c1d6eded568
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674946122 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2674946122
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2708814375
Short name T833
Test name
Test status
Simulation time 119393306 ps
CPU time 1.64 seconds
Started Jun 24 04:45:02 PM PDT 24
Finished Jun 24 04:45:06 PM PDT 24
Peak memory 197588 kb
Host smart-dc333b33-91b6-4f27-ae8a-6b9bef129c67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708814375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2708814375
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.338468930
Short name T787
Test name
Test status
Simulation time 408174738 ps
CPU time 1.14 seconds
Started Jun 24 04:44:56 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 197656 kb
Host smart-aadb599e-b7e1-4c38-9870-e9c4dcec610d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338468930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.338468930
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3514923429
Short name T770
Test name
Test status
Simulation time 21482701 ps
CPU time 1.03 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 197524 kb
Host smart-811fbe09-2f31-43c0-a5df-bb52857b060f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514923429 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3514923429
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2473926496
Short name T89
Test name
Test status
Simulation time 41428107 ps
CPU time 0.61 seconds
Started Jun 24 04:44:57 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 194728 kb
Host smart-4ad889d3-4dc9-40da-98bb-49d280bf6ff1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473926496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2473926496
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1989220128
Short name T843
Test name
Test status
Simulation time 14891393 ps
CPU time 0.58 seconds
Started Jun 24 04:44:59 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 193176 kb
Host smart-b45bae5d-bf02-4bba-8007-94a8cb8e8d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989220128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1989220128
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1863385773
Short name T810
Test name
Test status
Simulation time 66009765 ps
CPU time 0.69 seconds
Started Jun 24 04:44:55 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 195824 kb
Host smart-4879ea98-ca0e-4272-b730-8de6eef55fd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863385773 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1863385773
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.512800727
Short name T790
Test name
Test status
Simulation time 72458993 ps
CPU time 1.85 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 197748 kb
Host smart-47485f58-b649-4701-aa6a-65763683ea78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512800727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.512800727
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1715417942
Short name T827
Test name
Test status
Simulation time 76926690 ps
CPU time 1.08 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 197752 kb
Host smart-61270b4a-2c89-4718-bad3-c3e844e7ac8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715417942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1715417942
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3515144874
Short name T746
Test name
Test status
Simulation time 85927138 ps
CPU time 0.91 seconds
Started Jun 24 04:45:00 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 197572 kb
Host smart-b3da6f69-50a7-4c95-81c0-789b36862a01
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515144874 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3515144874
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2509052430
Short name T79
Test name
Test status
Simulation time 126404694 ps
CPU time 0.62 seconds
Started Jun 24 04:44:59 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 192888 kb
Host smart-48cb9c8c-f690-43ba-9ba7-8b55edf741bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509052430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2509052430
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1962599110
Short name T781
Test name
Test status
Simulation time 23741348 ps
CPU time 0.63 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 193420 kb
Host smart-f512364d-3fc5-43b1-99bf-b0bc265ccad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962599110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1962599110
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3528461653
Short name T96
Test name
Test status
Simulation time 374118536 ps
CPU time 0.85 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 195972 kb
Host smart-6ccd12f7-66f1-4cb6-b86c-b6148779f945
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528461653 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3528461653
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1836772961
Short name T737
Test name
Test status
Simulation time 34637572 ps
CPU time 1.69 seconds
Started Jun 24 04:44:56 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 197724 kb
Host smart-d4184649-8819-4092-9abf-45ca2bca6f32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836772961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1836772961
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2896148284
Short name T104
Test name
Test status
Simulation time 235120684 ps
CPU time 1.42 seconds
Started Jun 24 04:44:59 PM PDT 24
Finished Jun 24 04:45:04 PM PDT 24
Peak memory 197680 kb
Host smart-5be55662-bd58-4a26-8289-2b17ed8bb04d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896148284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2896148284
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2731947592
Short name T742
Test name
Test status
Simulation time 20479947 ps
CPU time 0.73 seconds
Started Jun 24 04:44:59 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 197340 kb
Host smart-e1a6dae0-56c7-4630-ac2f-d9cae3e3a8be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731947592 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2731947592
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3394778851
Short name T799
Test name
Test status
Simulation time 13279467 ps
CPU time 0.58 seconds
Started Jun 24 04:45:00 PM PDT 24
Finished Jun 24 04:45:03 PM PDT 24
Peak memory 192944 kb
Host smart-241fc45c-4b7e-41d1-9ae3-71615d4ac7e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394778851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3394778851
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.789118060
Short name T834
Test name
Test status
Simulation time 61103919 ps
CPU time 0.63 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 194028 kb
Host smart-42897905-d992-48de-8d23-5a59eb45c4d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789118060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.789118060
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2044233183
Short name T75
Test name
Test status
Simulation time 24865188 ps
CPU time 0.76 seconds
Started Jun 24 04:44:57 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 195744 kb
Host smart-d682fc55-3c37-4eb4-baa1-23f5917e2165
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044233183 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2044233183
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.684533336
Short name T721
Test name
Test status
Simulation time 121460392 ps
CPU time 2.85 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:05 PM PDT 24
Peak memory 197668 kb
Host smart-6dda67a0-9808-45c4-aee8-45c31ab25eab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684533336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.684533336
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.555412841
Short name T36
Test name
Test status
Simulation time 162709192 ps
CPU time 0.87 seconds
Started Jun 24 04:44:58 PM PDT 24
Finished Jun 24 04:45:02 PM PDT 24
Peak memory 196804 kb
Host smart-b6483f3a-c033-40ef-b585-fd142d859ad8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555412841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.555412841
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1861164657
Short name T724
Test name
Test status
Simulation time 65313914 ps
CPU time 1.38 seconds
Started Jun 24 04:45:08 PM PDT 24
Finished Jun 24 04:45:11 PM PDT 24
Peak memory 197732 kb
Host smart-e80466fe-7a93-4c1a-91cb-b7ff2c8e4b0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861164657 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1861164657
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3795478112
Short name T765
Test name
Test status
Simulation time 14484733 ps
CPU time 0.63 seconds
Started Jun 24 04:45:08 PM PDT 24
Finished Jun 24 04:45:10 PM PDT 24
Peak memory 194492 kb
Host smart-8a4d28d9-8072-44ab-bd96-6456fb38c077
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795478112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3795478112
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1195197318
Short name T772
Test name
Test status
Simulation time 30601462 ps
CPU time 0.6 seconds
Started Jun 24 04:45:10 PM PDT 24
Finished Jun 24 04:45:13 PM PDT 24
Peak memory 193284 kb
Host smart-7306a60f-a9ae-4468-b387-5651f52eac45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195197318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1195197318
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.295981091
Short name T837
Test name
Test status
Simulation time 80065471 ps
CPU time 0.9 seconds
Started Jun 24 04:45:10 PM PDT 24
Finished Jun 24 04:45:15 PM PDT 24
Peak memory 197056 kb
Host smart-0b24b3ae-27b6-4524-ba42-0f3432808208
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295981091 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.295981091
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1845040567
Short name T748
Test name
Test status
Simulation time 276300765 ps
CPU time 2.51 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:15 PM PDT 24
Peak memory 197620 kb
Host smart-21e8e140-7972-4bff-8a5b-e8bdf77fd0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845040567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1845040567
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4024590542
Short name T42
Test name
Test status
Simulation time 136098885 ps
CPU time 1.21 seconds
Started Jun 24 04:45:08 PM PDT 24
Finished Jun 24 04:45:10 PM PDT 24
Peak memory 197672 kb
Host smart-e0bdca00-5bd2-4597-8223-76bd0e04fb9a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024590542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4024590542
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2008386751
Short name T726
Test name
Test status
Simulation time 267340318 ps
CPU time 0.75 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:13 PM PDT 24
Peak memory 196688 kb
Host smart-29779a03-72ce-4ee3-a536-a30ac7d5380b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008386751 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2008386751
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.998039520
Short name T794
Test name
Test status
Simulation time 27084740 ps
CPU time 0.57 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 192876 kb
Host smart-5baa8940-a060-47c7-aea4-33ffa0b6f254
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998039520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.998039520
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.994200497
Short name T731
Test name
Test status
Simulation time 81191219 ps
CPU time 0.59 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 193972 kb
Host smart-6044ff00-7cb9-4765-863a-19b11c53bfb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994200497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.994200497
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3707939896
Short name T100
Test name
Test status
Simulation time 31440449 ps
CPU time 0.85 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 196940 kb
Host smart-bb0dc346-1846-48ae-a0d2-39f4e09145a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707939896 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3707939896
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3808952871
Short name T722
Test name
Test status
Simulation time 130747209 ps
CPU time 1.93 seconds
Started Jun 24 04:45:07 PM PDT 24
Finished Jun 24 04:45:09 PM PDT 24
Peak memory 197732 kb
Host smart-3b5296d1-c388-417f-ab1a-e74a1aef73a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808952871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3808952871
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.453036326
Short name T44
Test name
Test status
Simulation time 442020286 ps
CPU time 1.36 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 197676 kb
Host smart-aeecb907-3936-476c-b74a-5495749c3afd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453036326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.453036326
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3046431004
Short name T751
Test name
Test status
Simulation time 40380902 ps
CPU time 1.09 seconds
Started Jun 24 04:45:10 PM PDT 24
Finished Jun 24 04:45:15 PM PDT 24
Peak memory 197768 kb
Host smart-2383ce92-773b-47aa-b409-84a486536111
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046431004 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3046431004
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1133058198
Short name T78
Test name
Test status
Simulation time 20325041 ps
CPU time 0.61 seconds
Started Jun 24 04:45:07 PM PDT 24
Finished Jun 24 04:45:09 PM PDT 24
Peak memory 195016 kb
Host smart-f0549049-705f-4a63-b1b0-f78bfc1e4724
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133058198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1133058198
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1479526535
Short name T739
Test name
Test status
Simulation time 24433175 ps
CPU time 0.61 seconds
Started Jun 24 04:45:12 PM PDT 24
Finished Jun 24 04:45:18 PM PDT 24
Peak memory 193960 kb
Host smart-356e0e5e-4a65-467d-9a53-2b451a05e464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479526535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1479526535
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.428680667
Short name T826
Test name
Test status
Simulation time 61671039 ps
CPU time 0.66 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 194464 kb
Host smart-18c42b51-b987-41d7-a6a6-2b6d2efb143a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428680667 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.428680667
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3587106143
Short name T723
Test name
Test status
Simulation time 102541268 ps
CPU time 2.07 seconds
Started Jun 24 04:45:12 PM PDT 24
Finished Jun 24 04:45:18 PM PDT 24
Peak memory 197628 kb
Host smart-424e2732-41f6-48a1-9a20-8819ea84710b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587106143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3587106143
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.439900365
Short name T34
Test name
Test status
Simulation time 102318153 ps
CPU time 1.48 seconds
Started Jun 24 04:45:08 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 197560 kb
Host smart-5cb27349-cbd7-41e3-acb0-9c00eceb039e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439900365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.439900365
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.441294730
Short name T800
Test name
Test status
Simulation time 19403974 ps
CPU time 0.86 seconds
Started Jun 24 04:45:12 PM PDT 24
Finished Jun 24 04:45:17 PM PDT 24
Peak memory 197520 kb
Host smart-dc8d532a-212e-444b-bb4e-9c0096d6d098
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441294730 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.441294730
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.639699983
Short name T83
Test name
Test status
Simulation time 23478947 ps
CPU time 0.63 seconds
Started Jun 24 04:45:11 PM PDT 24
Finished Jun 24 04:45:16 PM PDT 24
Peak memory 194544 kb
Host smart-b347131a-3fc3-4e87-bff5-49984d4e7c55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639699983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.639699983
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1423626971
Short name T774
Test name
Test status
Simulation time 25327212 ps
CPU time 0.6 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 193328 kb
Host smart-16fa0e1d-e850-4d66-aa67-566eb1a4ada9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423626971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1423626971
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.733243637
Short name T775
Test name
Test status
Simulation time 56647939 ps
CPU time 0.63 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:13 PM PDT 24
Peak memory 194828 kb
Host smart-81df4a17-4e6d-476a-9345-a5aba26bddbb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733243637 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.733243637
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.2286468518
Short name T744
Test name
Test status
Simulation time 148475291 ps
CPU time 3.24 seconds
Started Jun 24 04:45:08 PM PDT 24
Finished Jun 24 04:45:14 PM PDT 24
Peak memory 197700 kb
Host smart-5bb44b21-4e51-4f73-8d6b-93850bb55314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286468518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.2286468518
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2640627251
Short name T780
Test name
Test status
Simulation time 77830702 ps
CPU time 0.9 seconds
Started Jun 24 04:45:13 PM PDT 24
Finished Jun 24 04:45:19 PM PDT 24
Peak memory 197224 kb
Host smart-4b071b9b-a841-431a-9caf-bc3eb95c6eba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640627251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2640627251
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3968655514
Short name T82
Test name
Test status
Simulation time 16429240 ps
CPU time 0.75 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:47 PM PDT 24
Peak memory 195504 kb
Host smart-2fed30c0-78d5-4dea-b966-8993b1b136e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968655514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3968655514
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1102510460
Short name T824
Test name
Test status
Simulation time 261538649 ps
CPU time 3.22 seconds
Started Jun 24 04:44:44 PM PDT 24
Finished Jun 24 04:44:52 PM PDT 24
Peak memory 196920 kb
Host smart-52b8934c-9368-447f-8d8a-6f4ccba9af31
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102510460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1102510460
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.27823783
Short name T77
Test name
Test status
Simulation time 19600180 ps
CPU time 0.65 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 194560 kb
Host smart-518f7781-6bc4-4656-9fed-0621c2f33286
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27823783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.27823783
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1677296492
Short name T842
Test name
Test status
Simulation time 38681481 ps
CPU time 1.82 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 197724 kb
Host smart-8620eea1-9ab8-4307-8df7-824383112f4c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677296492 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1677296492
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.56882862
Short name T815
Test name
Test status
Simulation time 58520407 ps
CPU time 0.63 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:47 PM PDT 24
Peak memory 194492 kb
Host smart-bf3a8f31-29db-462c-9380-1b935c6eda89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56882862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_c
sr_rw.56882862
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3069134050
Short name T814
Test name
Test status
Simulation time 60688942 ps
CPU time 0.58 seconds
Started Jun 24 04:44:40 PM PDT 24
Finished Jun 24 04:44:42 PM PDT 24
Peak memory 193912 kb
Host smart-bdb10e1b-8f5f-489e-ad2e-d6f633b4724e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069134050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3069134050
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.1108154803
Short name T97
Test name
Test status
Simulation time 26448815 ps
CPU time 0.71 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 195304 kb
Host smart-6e01d66a-e5df-41cc-9cdc-316d4e1f20ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108154803 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.1108154803
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2445908037
Short name T823
Test name
Test status
Simulation time 226902450 ps
CPU time 2.69 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 197652 kb
Host smart-e5a0c3ff-505f-4273-976e-d1f26b637d9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445908037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2445908037
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.263763950
Short name T35
Test name
Test status
Simulation time 434204537 ps
CPU time 1.38 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:43 PM PDT 24
Peak memory 197740 kb
Host smart-12f99590-52c4-44f8-b42c-b8b59eed28a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263763950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.263763950
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1719321888
Short name T776
Test name
Test status
Simulation time 18199917 ps
CPU time 0.63 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:13 PM PDT 24
Peak memory 193952 kb
Host smart-e48587b7-58f1-41ad-b60d-3ec75f66e3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719321888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1719321888
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.649799364
Short name T830
Test name
Test status
Simulation time 25096550 ps
CPU time 0.64 seconds
Started Jun 24 04:45:12 PM PDT 24
Finished Jun 24 04:45:17 PM PDT 24
Peak memory 192956 kb
Host smart-0d21e69c-141c-4c9e-a609-eb5b6e756fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649799364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.649799364
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3215848797
Short name T725
Test name
Test status
Simulation time 18606367 ps
CPU time 0.63 seconds
Started Jun 24 04:45:12 PM PDT 24
Finished Jun 24 04:45:17 PM PDT 24
Peak memory 192904 kb
Host smart-37505e6a-a0b6-4b73-8411-4b3447c6c1aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215848797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3215848797
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.345453479
Short name T750
Test name
Test status
Simulation time 17091430 ps
CPU time 0.61 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:12 PM PDT 24
Peak memory 193460 kb
Host smart-f2b8c503-1481-4d60-8681-e3c035ca45cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345453479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.345453479
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1345775844
Short name T771
Test name
Test status
Simulation time 86716219 ps
CPU time 0.57 seconds
Started Jun 24 04:45:11 PM PDT 24
Finished Jun 24 04:45:15 PM PDT 24
Peak memory 193292 kb
Host smart-f57adaac-ff75-46cc-b8d5-3428347882be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345775844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1345775844
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1451550058
Short name T769
Test name
Test status
Simulation time 31931774 ps
CPU time 0.63 seconds
Started Jun 24 04:45:10 PM PDT 24
Finished Jun 24 04:45:14 PM PDT 24
Peak memory 193312 kb
Host smart-f3ce3b7e-e0d0-4df9-a1bd-0c8d6bd0a2f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451550058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1451550058
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1509359233
Short name T758
Test name
Test status
Simulation time 47788369 ps
CPU time 0.6 seconds
Started Jun 24 04:45:08 PM PDT 24
Finished Jun 24 04:45:11 PM PDT 24
Peak memory 193212 kb
Host smart-2ce69f5e-8935-41ee-891b-d32ff66fb1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509359233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1509359233
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3556450550
Short name T760
Test name
Test status
Simulation time 27027624 ps
CPU time 0.57 seconds
Started Jun 24 04:45:13 PM PDT 24
Finished Jun 24 04:45:18 PM PDT 24
Peak memory 193196 kb
Host smart-661a839b-7e82-43fe-8bbe-acd37d16559a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556450550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3556450550
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.359231555
Short name T801
Test name
Test status
Simulation time 117968871 ps
CPU time 0.56 seconds
Started Jun 24 04:45:06 PM PDT 24
Finished Jun 24 04:45:08 PM PDT 24
Peak memory 193296 kb
Host smart-e7ab0ba0-96f8-4983-928a-e54c1b6f68e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359231555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.359231555
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.393824986
Short name T819
Test name
Test status
Simulation time 23849546 ps
CPU time 0.6 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:13 PM PDT 24
Peak memory 193404 kb
Host smart-8ed330ab-6bc3-46c2-8c2d-acc6d2069550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393824986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.393824986
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1717719371
Short name T103
Test name
Test status
Simulation time 56315672 ps
CPU time 0.65 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 194392 kb
Host smart-fd3b3246-e511-4e7c-94ea-49798f3fcfa5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717719371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1717719371
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3572771871
Short name T808
Test name
Test status
Simulation time 5001977685 ps
CPU time 2.49 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:46 PM PDT 24
Peak memory 196180 kb
Host smart-cb25487b-bbb2-4561-ad78-b2979e450d1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572771871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3572771871
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1549748718
Short name T782
Test name
Test status
Simulation time 27393096 ps
CPU time 1.2 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 197624 kb
Host smart-15e0debd-3a2a-46be-b020-3e98de5eaa91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549748718 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1549748718
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2192759509
Short name T86
Test name
Test status
Simulation time 48577126 ps
CPU time 0.59 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 194472 kb
Host smart-8c185f59-83bc-41e6-a6a8-22292abae2d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192759509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2192759509
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4036243154
Short name T756
Test name
Test status
Simulation time 51176068 ps
CPU time 0.58 seconds
Started Jun 24 04:44:41 PM PDT 24
Finished Jun 24 04:44:44 PM PDT 24
Peak memory 193880 kb
Host smart-368a054d-6c8e-4904-8b7e-4dd618e92a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036243154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4036243154
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3855842407
Short name T788
Test name
Test status
Simulation time 93382888 ps
CPU time 0.87 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:45 PM PDT 24
Peak memory 195772 kb
Host smart-97854e4a-526f-42fd-bb53-11eb008b0a15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855842407 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3855842407
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2811632984
Short name T727
Test name
Test status
Simulation time 24263924 ps
CPU time 1.35 seconds
Started Jun 24 04:44:44 PM PDT 24
Finished Jun 24 04:44:50 PM PDT 24
Peak memory 197748 kb
Host smart-b8315b69-a5af-4ff5-8f61-f229fbcc6ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811632984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2811632984
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.675655677
Short name T764
Test name
Test status
Simulation time 424293257 ps
CPU time 1.34 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 197728 kb
Host smart-0ac4699f-8fa0-4013-bcc7-0872485431a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675655677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.675655677
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.375134587
Short name T786
Test name
Test status
Simulation time 23272665 ps
CPU time 0.61 seconds
Started Jun 24 04:45:09 PM PDT 24
Finished Jun 24 04:45:13 PM PDT 24
Peak memory 194032 kb
Host smart-7ab78600-bd45-4f0c-8b8d-147c983aafcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375134587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.375134587
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.250332362
Short name T753
Test name
Test status
Simulation time 52366523 ps
CPU time 0.63 seconds
Started Jun 24 04:45:08 PM PDT 24
Finished Jun 24 04:45:10 PM PDT 24
Peak memory 193636 kb
Host smart-6f3af5bd-b2cb-40c0-988d-a8cc7b42c50a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250332362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.250332362
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1097510826
Short name T733
Test name
Test status
Simulation time 31735618 ps
CPU time 0.57 seconds
Started Jun 24 04:45:16 PM PDT 24
Finished Jun 24 04:45:22 PM PDT 24
Peak memory 193240 kb
Host smart-9a23ceee-86d1-4c5e-aa54-8f9fab9bbb9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097510826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1097510826
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.291235986
Short name T791
Test name
Test status
Simulation time 12547007 ps
CPU time 0.62 seconds
Started Jun 24 04:45:18 PM PDT 24
Finished Jun 24 04:45:24 PM PDT 24
Peak memory 193976 kb
Host smart-28ce89e8-da6c-4e02-ac49-80031e7e34ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291235986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.291235986
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3533542555
Short name T767
Test name
Test status
Simulation time 34002175 ps
CPU time 0.61 seconds
Started Jun 24 04:45:20 PM PDT 24
Finished Jun 24 04:45:25 PM PDT 24
Peak memory 193324 kb
Host smart-bdfa89af-561b-42d7-9782-ec75087db764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533542555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3533542555
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1080979195
Short name T783
Test name
Test status
Simulation time 15157044 ps
CPU time 0.58 seconds
Started Jun 24 04:45:16 PM PDT 24
Finished Jun 24 04:45:22 PM PDT 24
Peak memory 193916 kb
Host smart-999b5fc6-e1a7-496a-89e3-ed9e7247f8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080979195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1080979195
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3138537030
Short name T822
Test name
Test status
Simulation time 12668521 ps
CPU time 0.64 seconds
Started Jun 24 04:45:20 PM PDT 24
Finished Jun 24 04:45:25 PM PDT 24
Peak memory 193996 kb
Host smart-e7063f5c-9e38-49f1-aa00-12aeec864781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138537030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3138537030
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2462074966
Short name T762
Test name
Test status
Simulation time 27280899 ps
CPU time 0.6 seconds
Started Jun 24 04:45:18 PM PDT 24
Finished Jun 24 04:45:23 PM PDT 24
Peak memory 193380 kb
Host smart-c2c5aae3-7f87-41e5-9c14-02775060d536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462074966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2462074966
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1329146943
Short name T730
Test name
Test status
Simulation time 13315277 ps
CPU time 0.59 seconds
Started Jun 24 04:45:19 PM PDT 24
Finished Jun 24 04:45:24 PM PDT 24
Peak memory 193192 kb
Host smart-ef97e47a-35aa-4965-84a6-30b58c641221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329146943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1329146943
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1598582379
Short name T809
Test name
Test status
Simulation time 15146796 ps
CPU time 0.64 seconds
Started Jun 24 04:45:18 PM PDT 24
Finished Jun 24 04:45:23 PM PDT 24
Peak memory 193372 kb
Host smart-7bc244cc-965b-44d8-a899-671259a5a5f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598582379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1598582379
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3675846543
Short name T87
Test name
Test status
Simulation time 15704927 ps
CPU time 0.76 seconds
Started Jun 24 04:44:42 PM PDT 24
Finished Jun 24 04:44:47 PM PDT 24
Peak memory 196144 kb
Host smart-d13d7637-de5f-4e67-9b86-1c8127816535
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675846543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3675846543
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1053732340
Short name T805
Test name
Test status
Simulation time 36385578 ps
CPU time 1.45 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 197656 kb
Host smart-9e4db955-0f33-47e6-8a97-a0b668f166d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053732340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1053732340
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1960968767
Short name T80
Test name
Test status
Simulation time 28638783 ps
CPU time 0.6 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 194328 kb
Host smart-ab787bb9-8b16-4279-9935-70975e805799
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960968767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1960968767
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2846768277
Short name T803
Test name
Test status
Simulation time 59268350 ps
CPU time 1.51 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 197764 kb
Host smart-2ab8ad9e-d4f8-4c77-b08f-f446290324f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846768277 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2846768277
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.4129716563
Short name T73
Test name
Test status
Simulation time 42611724 ps
CPU time 0.58 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 194656 kb
Host smart-74c2bbd8-3bf3-4828-9b63-8667219d5496
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129716563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.4129716563
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2289348577
Short name T820
Test name
Test status
Simulation time 212225496 ps
CPU time 0.61 seconds
Started Jun 24 04:44:46 PM PDT 24
Finished Jun 24 04:44:53 PM PDT 24
Peak memory 193912 kb
Host smart-d97a116e-7e8f-4386-aebc-6b5468be8ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289348577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2289348577
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3113785163
Short name T93
Test name
Test status
Simulation time 18051339 ps
CPU time 0.68 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:48 PM PDT 24
Peak memory 194580 kb
Host smart-bcd60cea-96d7-48b6-8f10-2e519f6032a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113785163 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3113785163
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.543432694
Short name T759
Test name
Test status
Simulation time 48774555 ps
CPU time 2.37 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 197700 kb
Host smart-04f66ef9-e0a3-4603-8b19-24207cda5031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543432694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.543432694
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3958419323
Short name T33
Test name
Test status
Simulation time 77725088 ps
CPU time 1.11 seconds
Started Jun 24 04:44:43 PM PDT 24
Finished Jun 24 04:44:49 PM PDT 24
Peak memory 197688 kb
Host smart-ad3817e5-cc9b-430d-8a0b-97691d1d2a17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958419323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3958419323
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1177024091
Short name T757
Test name
Test status
Simulation time 15108345 ps
CPU time 0.64 seconds
Started Jun 24 04:45:22 PM PDT 24
Finished Jun 24 04:45:27 PM PDT 24
Peak memory 193948 kb
Host smart-4edfdb65-04a1-49c6-918c-12cb95105c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177024091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1177024091
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2154431445
Short name T732
Test name
Test status
Simulation time 40918409 ps
CPU time 0.59 seconds
Started Jun 24 04:45:18 PM PDT 24
Finished Jun 24 04:45:23 PM PDT 24
Peak memory 193320 kb
Host smart-e5cfe679-d218-44b5-9d91-282331cd3382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154431445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2154431445
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.729941092
Short name T813
Test name
Test status
Simulation time 12580376 ps
CPU time 0.6 seconds
Started Jun 24 04:45:19 PM PDT 24
Finished Jun 24 04:45:24 PM PDT 24
Peak memory 193256 kb
Host smart-2b21125b-cf95-4315-8fc6-74d17602ed5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729941092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.729941092
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.418583671
Short name T795
Test name
Test status
Simulation time 37403426 ps
CPU time 0.6 seconds
Started Jun 24 04:45:17 PM PDT 24
Finished Jun 24 04:45:23 PM PDT 24
Peak memory 193300 kb
Host smart-bcdcb609-014e-4a98-93dd-7db64949b35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418583671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.418583671
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.710046142
Short name T743
Test name
Test status
Simulation time 11978833 ps
CPU time 0.64 seconds
Started Jun 24 04:45:21 PM PDT 24
Finished Jun 24 04:45:26 PM PDT 24
Peak memory 193444 kb
Host smart-550b385e-475b-42fc-8c9e-e6afd7e340ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710046142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.710046142
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3742087015
Short name T828
Test name
Test status
Simulation time 36324177 ps
CPU time 0.58 seconds
Started Jun 24 04:45:21 PM PDT 24
Finished Jun 24 04:45:26 PM PDT 24
Peak memory 193904 kb
Host smart-68d9db3d-990e-4692-807d-685b9a083cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742087015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3742087015
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1911916084
Short name T829
Test name
Test status
Simulation time 21737252 ps
CPU time 0.67 seconds
Started Jun 24 04:45:20 PM PDT 24
Finished Jun 24 04:45:25 PM PDT 24
Peak memory 194016 kb
Host smart-1a19f437-d644-459f-bb27-4a2dffbb6108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911916084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1911916084
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4067371266
Short name T720
Test name
Test status
Simulation time 40733413 ps
CPU time 0.59 seconds
Started Jun 24 04:45:21 PM PDT 24
Finished Jun 24 04:45:26 PM PDT 24
Peak memory 193380 kb
Host smart-b0298c0e-256b-4baf-8bd9-fa4cccef694d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067371266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4067371266
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2151295676
Short name T817
Test name
Test status
Simulation time 112293086 ps
CPU time 0.64 seconds
Started Jun 24 04:45:22 PM PDT 24
Finished Jun 24 04:45:27 PM PDT 24
Peak memory 193344 kb
Host smart-76bffec0-f25b-41e9-bda8-30a3e60dd48e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151295676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2151295676
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.874957707
Short name T755
Test name
Test status
Simulation time 16521048 ps
CPU time 0.62 seconds
Started Jun 24 04:45:18 PM PDT 24
Finished Jun 24 04:45:23 PM PDT 24
Peak memory 193376 kb
Host smart-3412c217-2f44-4a1b-8e0e-234ed19079a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874957707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.874957707
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2837621578
Short name T785
Test name
Test status
Simulation time 23428003 ps
CPU time 1.08 seconds
Started Jun 24 04:44:53 PM PDT 24
Finished Jun 24 04:44:59 PM PDT 24
Peak memory 197664 kb
Host smart-e082041f-76c1-4741-9d57-f43a70523777
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837621578 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2837621578
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1964206758
Short name T807
Test name
Test status
Simulation time 67459106 ps
CPU time 0.56 seconds
Started Jun 24 04:44:45 PM PDT 24
Finished Jun 24 04:44:51 PM PDT 24
Peak memory 192924 kb
Host smart-5b8a63c1-a94e-4d41-85ba-3a8ad4dfb2f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964206758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1964206758
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1993990802
Short name T802
Test name
Test status
Simulation time 14591658 ps
CPU time 0.6 seconds
Started Jun 24 04:44:49 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 193640 kb
Host smart-5a501eae-ef9f-45de-adcf-9e0214ddcfe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993990802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1993990802
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3050421532
Short name T811
Test name
Test status
Simulation time 25182859 ps
CPU time 0.66 seconds
Started Jun 24 04:44:48 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 195224 kb
Host smart-9b843b28-d5d0-4a30-8cfc-b83536bbf1bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050421532 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3050421532
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1220655769
Short name T754
Test name
Test status
Simulation time 763597315 ps
CPU time 1.45 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 197748 kb
Host smart-fc9f51f8-de71-40b5-b865-93eb7dfe7240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220655769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1220655769
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1413381738
Short name T835
Test name
Test status
Simulation time 170804944 ps
CPU time 0.88 seconds
Started Jun 24 04:44:51 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 196540 kb
Host smart-69be0b1a-8eed-46e8-84b3-ddfcc34a378c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413381738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1413381738
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4149988086
Short name T741
Test name
Test status
Simulation time 34754744 ps
CPU time 0.83 seconds
Started Jun 24 04:44:53 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 197524 kb
Host smart-254efeaf-d475-4426-86af-f0aef92cf261
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149988086 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4149988086
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.127325514
Short name T90
Test name
Test status
Simulation time 54990078 ps
CPU time 0.56 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 193288 kb
Host smart-77e08563-5afd-4fa2-b3cd-cdeb28f90ee6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127325514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.127325514
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1015507365
Short name T797
Test name
Test status
Simulation time 17768958 ps
CPU time 0.62 seconds
Started Jun 24 04:44:51 PM PDT 24
Finished Jun 24 04:44:56 PM PDT 24
Peak memory 193336 kb
Host smart-34cf40d3-96ed-4a40-bb53-ae1f15e92564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015507365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1015507365
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1834807989
Short name T792
Test name
Test status
Simulation time 16087263 ps
CPU time 0.68 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 194548 kb
Host smart-735a62cb-b99f-48f5-96af-0167a58e7248
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834807989 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1834807989
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3075141924
Short name T831
Test name
Test status
Simulation time 152778704 ps
CPU time 2.17 seconds
Started Jun 24 04:44:52 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 197668 kb
Host smart-1b54bfae-993c-493e-9315-c2680f3ee997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075141924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3075141924
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1590545016
Short name T763
Test name
Test status
Simulation time 81612216 ps
CPU time 1.12 seconds
Started Jun 24 04:44:55 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 197660 kb
Host smart-c49ecab1-62cc-4000-8dc1-c8082d0190a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590545016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1590545016
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.124231524
Short name T779
Test name
Test status
Simulation time 36390491 ps
CPU time 0.99 seconds
Started Jun 24 04:44:52 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 197508 kb
Host smart-3952948c-6fc8-4be0-a1df-6b37f07b9826
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124231524 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.124231524
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1641247844
Short name T81
Test name
Test status
Simulation time 13427349 ps
CPU time 0.58 seconds
Started Jun 24 04:44:49 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 194240 kb
Host smart-e07d8ee2-711a-42dc-b8a1-d31c0f6d70ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641247844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1641247844
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3348701371
Short name T796
Test name
Test status
Simulation time 96236682 ps
CPU time 0.57 seconds
Started Jun 24 04:44:48 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 193288 kb
Host smart-20f0452b-30c9-48bc-8b34-cbcd35239204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348701371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3348701371
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3878725802
Short name T789
Test name
Test status
Simulation time 125860430 ps
CPU time 0.83 seconds
Started Jun 24 04:44:49 PM PDT 24
Finished Jun 24 04:44:54 PM PDT 24
Peak memory 195904 kb
Host smart-6e0d1ac1-4774-4383-b508-b2686f7e9930
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878725802 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3878725802
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3653793699
Short name T768
Test name
Test status
Simulation time 72165003 ps
CPU time 1.95 seconds
Started Jun 24 04:44:51 PM PDT 24
Finished Jun 24 04:44:57 PM PDT 24
Peak memory 197640 kb
Host smart-452929b7-3078-4c65-99b2-f1bdf47e7ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653793699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3653793699
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1073811620
Short name T840
Test name
Test status
Simulation time 77061807 ps
CPU time 1.14 seconds
Started Jun 24 04:44:53 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 197280 kb
Host smart-108c3d3f-ff1c-4696-a3ec-57142e734af6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073811620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1073811620
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.182431743
Short name T736
Test name
Test status
Simulation time 57512874 ps
CPU time 0.64 seconds
Started Jun 24 04:44:56 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 196732 kb
Host smart-e8a455b8-7d04-4c11-8a5b-440c5c04a1f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182431743 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.182431743
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.799038158
Short name T102
Test name
Test status
Simulation time 13320431 ps
CPU time 0.61 seconds
Started Jun 24 04:44:53 PM PDT 24
Finished Jun 24 04:44:58 PM PDT 24
Peak memory 194272 kb
Host smart-36774528-de33-4c56-9b6d-13b6bb0f2fa8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799038158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.799038158
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1199878610
Short name T747
Test name
Test status
Simulation time 36523653 ps
CPU time 0.62 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 193908 kb
Host smart-b893d184-f4e6-4bb8-b137-a0ee56a50e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199878610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1199878610
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3556349482
Short name T832
Test name
Test status
Simulation time 368248839 ps
CPU time 0.84 seconds
Started Jun 24 04:44:47 PM PDT 24
Finished Jun 24 04:44:53 PM PDT 24
Peak memory 196752 kb
Host smart-fa1d2dcd-7d18-44bc-80e5-ace2c68940c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556349482 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3556349482
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2139494760
Short name T719
Test name
Test status
Simulation time 160434236 ps
CPU time 2.62 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:57 PM PDT 24
Peak memory 197724 kb
Host smart-4ce2ce11-7bdc-4b94-8242-ed592616941e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139494760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2139494760
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1862178254
Short name T766
Test name
Test status
Simulation time 107256134 ps
CPU time 0.82 seconds
Started Jun 24 04:44:56 PM PDT 24
Finished Jun 24 04:45:01 PM PDT 24
Peak memory 197152 kb
Host smart-2306425a-f37a-4581-8f75-ef2edffa4ed3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862178254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1862178254
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.3636734952
Short name T761
Test name
Test status
Simulation time 30592421 ps
CPU time 1.55 seconds
Started Jun 24 04:44:51 PM PDT 24
Finished Jun 24 04:44:57 PM PDT 24
Peak memory 197728 kb
Host smart-e68f9462-35dc-46dc-aa1f-222918a90e7f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636734952 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.3636734952
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.289603868
Short name T74
Test name
Test status
Simulation time 14487881 ps
CPU time 0.62 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 194432 kb
Host smart-34f65126-aa6d-42ee-8819-204eafca056c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289603868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.289603868
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.719441886
Short name T752
Test name
Test status
Simulation time 31397243 ps
CPU time 0.55 seconds
Started Jun 24 04:44:55 PM PDT 24
Finished Jun 24 04:45:00 PM PDT 24
Peak memory 193940 kb
Host smart-dc776283-6d74-4980-9c5f-82544b7e565a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719441886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.719441886
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.955044040
Short name T95
Test name
Test status
Simulation time 130051017 ps
CPU time 0.89 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 196672 kb
Host smart-4c29a3e1-48b0-43fd-a25c-d7950b66abac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955044040 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.955044040
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.41734232
Short name T836
Test name
Test status
Simulation time 64246428 ps
CPU time 1.64 seconds
Started Jun 24 04:44:51 PM PDT 24
Finished Jun 24 04:44:57 PM PDT 24
Peak memory 197688 kb
Host smart-d9502d7b-17d0-469e-b85a-ad0a44280715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.41734232
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3574596339
Short name T816
Test name
Test status
Simulation time 88464397 ps
CPU time 0.84 seconds
Started Jun 24 04:44:50 PM PDT 24
Finished Jun 24 04:44:55 PM PDT 24
Peak memory 196528 kb
Host smart-6c722102-7754-4a0e-98f8-b8d1219bb097
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574596339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3574596339
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2986326996
Short name T364
Test name
Test status
Simulation time 50190397 ps
CPU time 0.58 seconds
Started Jun 24 05:17:25 PM PDT 24
Finished Jun 24 05:17:27 PM PDT 24
Peak memory 194572 kb
Host smart-972ab36f-baf4-45b7-866a-63de108e7470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986326996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2986326996
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1739528470
Short name T72
Test name
Test status
Simulation time 300551165 ps
CPU time 0.83 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:17:26 PM PDT 24
Peak memory 195240 kb
Host smart-6e6755fb-0dd8-4df2-87b0-058b144257e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739528470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1739528470
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1736543624
Short name T192
Test name
Test status
Simulation time 1667225829 ps
CPU time 16.14 seconds
Started Jun 24 05:17:21 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 197948 kb
Host smart-b2c57809-8fd1-46dd-9546-997f6b29df5c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736543624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1736543624
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.588641428
Short name T345
Test name
Test status
Simulation time 216360823 ps
CPU time 0.97 seconds
Started Jun 24 05:17:20 PM PDT 24
Finished Jun 24 05:17:21 PM PDT 24
Peak memory 197740 kb
Host smart-a25fa859-6caf-4b37-8115-a099910da154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588641428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.588641428
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3013233062
Short name T136
Test name
Test status
Simulation time 30726639 ps
CPU time 0.67 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:17:25 PM PDT 24
Peak memory 194996 kb
Host smart-0ff438fb-035d-43f3-b650-8a61eb286332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013233062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3013233062
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.313453360
Short name T331
Test name
Test status
Simulation time 103716850 ps
CPU time 1.29 seconds
Started Jun 24 05:17:24 PM PDT 24
Finished Jun 24 05:17:27 PM PDT 24
Peak memory 197868 kb
Host smart-13d433eb-dac9-41f5-9ea6-b95dd0f0fd52
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313453360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.313453360
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2555303587
Short name T130
Test name
Test status
Simulation time 138182778 ps
CPU time 1.17 seconds
Started Jun 24 05:17:24 PM PDT 24
Finished Jun 24 05:17:27 PM PDT 24
Peak memory 196748 kb
Host smart-b3d46054-93ea-46b3-b4ab-ac2a5cc2399f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555303587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2555303587
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3604614488
Short name T191
Test name
Test status
Simulation time 54718691 ps
CPU time 0.84 seconds
Started Jun 24 05:17:21 PM PDT 24
Finished Jun 24 05:17:23 PM PDT 24
Peak memory 195360 kb
Host smart-8e58acee-6f7e-43a2-8156-d39e7a4a0444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604614488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3604614488
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3939455849
Short name T630
Test name
Test status
Simulation time 236453343 ps
CPU time 1.27 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:17:25 PM PDT 24
Peak memory 195920 kb
Host smart-e709e82a-6c1c-4646-8c7e-ce02539390f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939455849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3939455849
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3730493687
Short name T659
Test name
Test status
Simulation time 103380699 ps
CPU time 1.65 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:17:27 PM PDT 24
Peak memory 197936 kb
Host smart-c6244e7e-574e-4850-9885-40ed63adaf89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730493687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3730493687
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2560921639
Short name T47
Test name
Test status
Simulation time 57419720 ps
CPU time 0.8 seconds
Started Jun 24 05:17:24 PM PDT 24
Finished Jun 24 05:17:27 PM PDT 24
Peak memory 213544 kb
Host smart-d0ec8cf0-afab-425f-bdb6-eaa7ef785c05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560921639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2560921639
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3146437040
Short name T465
Test name
Test status
Simulation time 128619074 ps
CPU time 1.08 seconds
Started Jun 24 05:17:19 PM PDT 24
Finished Jun 24 05:17:21 PM PDT 24
Peak memory 195884 kb
Host smart-bc0810d0-44db-4219-a359-aea6d1138902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146437040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3146437040
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.401765938
Short name T375
Test name
Test status
Simulation time 61335988 ps
CPU time 1.16 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:17:26 PM PDT 24
Peak memory 195536 kb
Host smart-2aac6142-c29a-4bc5-9a62-63dead7ecc62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401765938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.401765938
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.317700776
Short name T455
Test name
Test status
Simulation time 9519400729 ps
CPU time 133.4 seconds
Started Jun 24 05:17:24 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 198084 kb
Host smart-cf59fcb3-5762-4e0d-a695-a490cc170f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317700776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.317700776
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2993588029
Short name T361
Test name
Test status
Simulation time 111782503 ps
CPU time 0.61 seconds
Started Jun 24 05:17:29 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 193772 kb
Host smart-587eab8d-b7bb-4d82-b337-3357687b27ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993588029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2993588029
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.121427464
Short name T336
Test name
Test status
Simulation time 113530641 ps
CPU time 0.66 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:31 PM PDT 24
Peak memory 194776 kb
Host smart-20bbe991-fcb8-4d00-964a-d195e6b27dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121427464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.121427464
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2939674543
Short name T298
Test name
Test status
Simulation time 560899470 ps
CPU time 20.19 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:49 PM PDT 24
Peak memory 195504 kb
Host smart-4f3e285c-85d1-4ae7-b926-c9240e23cfa7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939674543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2939674543
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1651370666
Short name T387
Test name
Test status
Simulation time 181420651 ps
CPU time 1.04 seconds
Started Jun 24 05:17:30 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 197044 kb
Host smart-9b2c0f5c-95af-4a26-bf10-5d1549cfb205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651370666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1651370666
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1800629332
Short name T498
Test name
Test status
Simulation time 162924524 ps
CPU time 1.36 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:31 PM PDT 24
Peak memory 196844 kb
Host smart-c9ffa14d-9b80-4ddb-8195-be5c287bfaa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800629332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1800629332
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2970886891
Short name T119
Test name
Test status
Simulation time 70233287 ps
CPU time 1.62 seconds
Started Jun 24 05:17:32 PM PDT 24
Finished Jun 24 05:17:35 PM PDT 24
Peak memory 196700 kb
Host smart-ab20f75e-d9a2-4858-948d-12f2c6c4ac31
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970886891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2970886891
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.216947923
Short name T137
Test name
Test status
Simulation time 1324701738 ps
CPU time 2.41 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 197948 kb
Host smart-857bc2e3-fc6a-42d9-9222-165542924a5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216947923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.216947923
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2971667376
Short name T211
Test name
Test status
Simulation time 46607288 ps
CPU time 1.07 seconds
Started Jun 24 05:17:29 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 196352 kb
Host smart-e70e37e7-74b1-4dad-acf9-821d0a3ebacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971667376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2971667376
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2384645546
Short name T585
Test name
Test status
Simulation time 23414743 ps
CPU time 0.73 seconds
Started Jun 24 05:17:30 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 194164 kb
Host smart-5fdaf842-185e-4ba4-accf-45906e206100
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384645546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2384645546
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.108699990
Short name T48
Test name
Test status
Simulation time 119785765 ps
CPU time 5.33 seconds
Started Jun 24 05:17:29 PM PDT 24
Finished Jun 24 05:17:36 PM PDT 24
Peak memory 197984 kb
Host smart-a5ae9bc2-6482-4b45-9678-7d34e514d0cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108699990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.108699990
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.3692298967
Short name T680
Test name
Test status
Simulation time 145162319 ps
CPU time 0.93 seconds
Started Jun 24 05:17:23 PM PDT 24
Finished Jun 24 05:17:26 PM PDT 24
Peak memory 195828 kb
Host smart-15c1230d-7dd2-4caf-90e2-749b28d36c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692298967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3692298967
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1918350632
Short name T686
Test name
Test status
Simulation time 178322006 ps
CPU time 0.86 seconds
Started Jun 24 05:17:22 PM PDT 24
Finished Jun 24 05:17:25 PM PDT 24
Peak memory 196044 kb
Host smart-f135701b-9f6c-4b13-9089-2e0ed91e9674
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918350632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1918350632
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1008620153
Short name T13
Test name
Test status
Simulation time 91984050818 ps
CPU time 147.86 seconds
Started Jun 24 05:17:30 PM PDT 24
Finished Jun 24 05:19:59 PM PDT 24
Peak memory 191692 kb
Host smart-afee1728-0608-4d1c-ac3d-93cef3bf1b3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008620153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1008620153
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1193875629
Short name T459
Test name
Test status
Simulation time 14040058 ps
CPU time 0.58 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 193792 kb
Host smart-146b4e01-e0bb-40f4-8351-8f93b63bac66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193875629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1193875629
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1413160405
Short name T538
Test name
Test status
Simulation time 257617503 ps
CPU time 0.92 seconds
Started Jun 24 05:17:52 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 195796 kb
Host smart-2280c7d1-348b-44b1-a4fa-4e2fb3342dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413160405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1413160405
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2431371267
Short name T67
Test name
Test status
Simulation time 2662496278 ps
CPU time 20.38 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:18:12 PM PDT 24
Peak memory 196748 kb
Host smart-581794ba-cff5-482b-bc73-1de3b8e56c60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431371267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2431371267
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3923694397
Short name T402
Test name
Test status
Simulation time 72956751 ps
CPU time 1.1 seconds
Started Jun 24 05:17:53 PM PDT 24
Finished Jun 24 05:17:55 PM PDT 24
Peak memory 197808 kb
Host smart-4ff72971-1bfe-43aa-973a-4df2f9c99aaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923694397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3923694397
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.454562245
Short name T29
Test name
Test status
Simulation time 98843853 ps
CPU time 1.01 seconds
Started Jun 24 05:17:57 PM PDT 24
Finished Jun 24 05:17:59 PM PDT 24
Peak memory 196544 kb
Host smart-ce1358c8-170e-4725-b0ce-1007ea6cf753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454562245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.454562245
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1220017305
Short name T279
Test name
Test status
Simulation time 39658942 ps
CPU time 1.62 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 196216 kb
Host smart-6c585bd6-3b2a-4e8b-bfa6-1cd9aab94f9e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220017305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1220017305
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.702003936
Short name T286
Test name
Test status
Simulation time 327699135 ps
CPU time 2.85 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:56 PM PDT 24
Peak memory 196936 kb
Host smart-3f00b0c0-0e97-4b79-8ba3-7df9e1abf4ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702003936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
702003936
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1557616427
Short name T316
Test name
Test status
Simulation time 78889891 ps
CPU time 0.89 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:53 PM PDT 24
Peak memory 196572 kb
Host smart-3ad55ff5-d310-4449-9a69-678fe56da1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557616427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1557616427
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2876403544
Short name T425
Test name
Test status
Simulation time 39939173 ps
CPU time 1.05 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:53 PM PDT 24
Peak memory 195784 kb
Host smart-2cf04c93-9035-41ed-9f64-9cabb798bb82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876403544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2876403544
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3387963219
Short name T668
Test name
Test status
Simulation time 1045011305 ps
CPU time 3.42 seconds
Started Jun 24 05:17:53 PM PDT 24
Finished Jun 24 05:17:57 PM PDT 24
Peak memory 197836 kb
Host smart-d25b6986-76ab-465b-9911-773072877732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387963219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3387963219
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3924951203
Short name T237
Test name
Test status
Simulation time 75991719 ps
CPU time 1.19 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:53 PM PDT 24
Peak memory 195680 kb
Host smart-d53f6d26-4cf3-4c87-a77a-de0c27392a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924951203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3924951203
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1110349002
Short name T323
Test name
Test status
Simulation time 331754935 ps
CPU time 1.04 seconds
Started Jun 24 05:17:52 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 196332 kb
Host smart-7331384b-62a9-493b-8f6a-71b8efdafebe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110349002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1110349002
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2757406809
Short name T45
Test name
Test status
Simulation time 8509199443 ps
CPU time 52.5 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:18:45 PM PDT 24
Peak memory 198060 kb
Host smart-c82060c7-5f01-433f-91e9-c0909bde6dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757406809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2757406809
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3864304936
Short name T55
Test name
Test status
Simulation time 50329780260 ps
CPU time 437.63 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:25:21 PM PDT 24
Peak memory 198160 kb
Host smart-72cfc3ca-856f-49f5-b922-c349c9554197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3864304936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3864304936
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1189469379
Short name T421
Test name
Test status
Simulation time 14398821 ps
CPU time 0.62 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 193772 kb
Host smart-a25d388f-1d44-4111-8a0f-fb272b893615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189469379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1189469379
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3798148442
Short name T215
Test name
Test status
Simulation time 34297856 ps
CPU time 0.84 seconds
Started Jun 24 05:18:04 PM PDT 24
Finished Jun 24 05:18:07 PM PDT 24
Peak memory 195448 kb
Host smart-100d304d-ebe2-4c57-8fde-cbe90a5aa0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798148442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3798148442
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.709668386
Short name T141
Test name
Test status
Simulation time 628028190 ps
CPU time 23.2 seconds
Started Jun 24 05:18:07 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 196756 kb
Host smart-dafb6930-ee33-4183-afb2-02cec7ce369d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709668386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.709668386
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3648413814
Short name T168
Test name
Test status
Simulation time 142472605 ps
CPU time 0.78 seconds
Started Jun 24 05:18:04 PM PDT 24
Finished Jun 24 05:18:07 PM PDT 24
Peak memory 195700 kb
Host smart-f25a7d95-5633-4058-86c7-2069d1fea9e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648413814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3648413814
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1886937768
Short name T187
Test name
Test status
Simulation time 104732633 ps
CPU time 0.7 seconds
Started Jun 24 05:18:02 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 194104 kb
Host smart-c5d4a9cb-ecf5-470c-9489-a3bf124ef820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886937768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1886937768
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2101199263
Short name T147
Test name
Test status
Simulation time 141505321 ps
CPU time 3.42 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 198012 kb
Host smart-df7fc0c6-2be1-49e4-a422-7704679803d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101199263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2101199263
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1079028289
Short name T549
Test name
Test status
Simulation time 64781044 ps
CPU time 1.77 seconds
Started Jun 24 05:18:00 PM PDT 24
Finished Jun 24 05:18:02 PM PDT 24
Peak memory 195892 kb
Host smart-631fc03e-38f6-4d15-9e50-7d29594abd97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079028289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1079028289
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.101428364
Short name T576
Test name
Test status
Simulation time 109948526 ps
CPU time 0.82 seconds
Started Jun 24 05:17:59 PM PDT 24
Finished Jun 24 05:18:01 PM PDT 24
Peak memory 195204 kb
Host smart-d67430b3-d183-4592-a159-ab94790c3bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101428364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.101428364
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3177561989
Short name T185
Test name
Test status
Simulation time 78400193 ps
CPU time 0.78 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:06 PM PDT 24
Peak memory 196060 kb
Host smart-664c2fa7-1f13-49f4-8e57-a28410e594b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177561989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3177561989
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3791574765
Short name T329
Test name
Test status
Simulation time 872983402 ps
CPU time 5.65 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:07 PM PDT 24
Peak memory 197920 kb
Host smart-b04525f2-4573-4fe1-81a6-867c3805bc33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791574765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3791574765
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1513181796
Short name T307
Test name
Test status
Simulation time 251214316 ps
CPU time 1.09 seconds
Started Jun 24 05:18:02 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 195444 kb
Host smart-4b0b6906-22ab-4aed-b59d-94d4958e4f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513181796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1513181796
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.490123478
Short name T573
Test name
Test status
Simulation time 371253193 ps
CPU time 1.4 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 196080 kb
Host smart-5d4a2e76-58bf-4ad5-a90c-bfaae3e5d89f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490123478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.490123478
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.208562825
Short name T2
Test name
Test status
Simulation time 16283353421 ps
CPU time 189.6 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:21:15 PM PDT 24
Peak memory 198424 kb
Host smart-19414ca4-b0b5-4864-8347-6f7e66057b7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208562825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.208562825
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3476710334
Short name T497
Test name
Test status
Simulation time 12877368 ps
CPU time 0.61 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 193668 kb
Host smart-e4018a51-8bd1-48e8-b388-f17cd5635b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476710334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3476710334
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3806710036
Short name T709
Test name
Test status
Simulation time 54551515 ps
CPU time 0.8 seconds
Started Jun 24 05:18:00 PM PDT 24
Finished Jun 24 05:18:02 PM PDT 24
Peak memory 195212 kb
Host smart-878228e2-37ea-475e-9d41-10acb8354eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806710036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3806710036
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.867301424
Short name T704
Test name
Test status
Simulation time 1523865358 ps
CPU time 18.02 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:21 PM PDT 24
Peak memory 197856 kb
Host smart-0f66a848-0ec1-47f2-ba40-07d3a55afc58
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867301424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.867301424
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1834705102
Short name T263
Test name
Test status
Simulation time 125289921 ps
CPU time 0.96 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 195828 kb
Host smart-81454df9-707e-4546-885b-872717b83e50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834705102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1834705102
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3893135239
Short name T125
Test name
Test status
Simulation time 25639826 ps
CPU time 0.72 seconds
Started Jun 24 05:18:02 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 194188 kb
Host smart-43e98e22-72dd-4e53-8d29-7173dc40bfc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893135239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3893135239
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2753010779
Short name T613
Test name
Test status
Simulation time 25357646 ps
CPU time 1.07 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:06 PM PDT 24
Peak memory 196212 kb
Host smart-cfe02d9c-9bb3-4797-a35c-89063df42334
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753010779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2753010779
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3835524997
Short name T373
Test name
Test status
Simulation time 133434664 ps
CPU time 2.78 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:06 PM PDT 24
Peak memory 198004 kb
Host smart-90ef67a1-2878-4e21-bd0e-646cff754c6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835524997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3835524997
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2736868861
Short name T223
Test name
Test status
Simulation time 18363869 ps
CPU time 0.75 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:02 PM PDT 24
Peak memory 194816 kb
Host smart-de2fef98-9275-404e-b46a-4a25b68b132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736868861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2736868861
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1366116489
Short name T700
Test name
Test status
Simulation time 31717347 ps
CPU time 1.2 seconds
Started Jun 24 05:18:02 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 196916 kb
Host smart-35b854f7-9bee-406a-9fc9-86da8117786f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366116489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1366116489
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.412669301
Short name T152
Test name
Test status
Simulation time 55281084 ps
CPU time 1.14 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:02 PM PDT 24
Peak memory 196432 kb
Host smart-5e7ebf1f-582d-4c35-9142-865ad0bcfc95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412669301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.412669301
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3158886747
Short name T150
Test name
Test status
Simulation time 53168883 ps
CPU time 0.76 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:03 PM PDT 24
Peak memory 195156 kb
Host smart-a2a3373d-dcc8-4ed0-a94d-dc39c46e6ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158886747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3158886747
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1576771262
Short name T24
Test name
Test status
Simulation time 89712911 ps
CPU time 1.08 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:06 PM PDT 24
Peak memory 196804 kb
Host smart-a587ade8-ea38-4903-8f08-2c7d957378d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576771262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1576771262
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3248633522
Short name T595
Test name
Test status
Simulation time 3587451124 ps
CPU time 52.01 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:54 PM PDT 24
Peak memory 198032 kb
Host smart-dc43ceeb-9805-48a7-a66b-5d900ee10f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248633522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3248633522
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3766085115
Short name T281
Test name
Test status
Simulation time 25972786 ps
CPU time 0.65 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:06 PM PDT 24
Peak memory 194560 kb
Host smart-9bd73d9b-4624-4193-bf1b-1b7718e35641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766085115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3766085115
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.317783198
Short name T467
Test name
Test status
Simulation time 42429635 ps
CPU time 0.66 seconds
Started Jun 24 05:17:58 PM PDT 24
Finished Jun 24 05:18:00 PM PDT 24
Peak memory 194228 kb
Host smart-42391448-f6e7-4d84-aace-2ac1181c9ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317783198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.317783198
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1943398092
Short name T499
Test name
Test status
Simulation time 694731887 ps
CPU time 12.57 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 197956 kb
Host smart-d85be431-6933-4936-baa8-f33f03d05410
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943398092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1943398092
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1053323769
Short name T501
Test name
Test status
Simulation time 71391263 ps
CPU time 1.02 seconds
Started Jun 24 05:18:02 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 196412 kb
Host smart-2bf2ed1e-c157-4157-ae49-f93212b53bbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053323769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1053323769
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2318109906
Short name T404
Test name
Test status
Simulation time 1137260511 ps
CPU time 1.25 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 197088 kb
Host smart-7d12dc60-7058-490a-a32a-b10486efb2eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318109906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2318109906
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1563913200
Short name T678
Test name
Test status
Simulation time 73448799 ps
CPU time 3.04 seconds
Started Jun 24 05:18:00 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 198068 kb
Host smart-5b8f7148-142a-4eeb-be45-8618933d26db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563913200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1563913200
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.1402211563
Short name T476
Test name
Test status
Simulation time 244277479 ps
CPU time 0.92 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 194236 kb
Host smart-fd8938c7-7a52-44ee-9dee-7c2c8a07ae09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402211563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.1402211563
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1144175374
Short name T207
Test name
Test status
Simulation time 231141982 ps
CPU time 1.08 seconds
Started Jun 24 05:18:07 PM PDT 24
Finished Jun 24 05:18:08 PM PDT 24
Peak memory 195828 kb
Host smart-7728656c-9391-4897-8cbd-d76ce37fbcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144175374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1144175374
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.481216223
Short name T698
Test name
Test status
Simulation time 40216616 ps
CPU time 0.72 seconds
Started Jun 24 05:18:04 PM PDT 24
Finished Jun 24 05:18:06 PM PDT 24
Peak memory 194960 kb
Host smart-f0d3d7fe-fa80-4ca6-b441-8887235a7e53
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481216223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.481216223
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2291064944
Short name T277
Test name
Test status
Simulation time 468264435 ps
CPU time 5.51 seconds
Started Jun 24 05:17:59 PM PDT 24
Finished Jun 24 05:18:05 PM PDT 24
Peak memory 197944 kb
Host smart-123b8503-03c5-4236-ba31-e7e90e155137
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291064944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2291064944
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.4146813901
Short name T462
Test name
Test status
Simulation time 228192538 ps
CPU time 1.03 seconds
Started Jun 24 05:18:03 PM PDT 24
Finished Jun 24 05:18:06 PM PDT 24
Peak memory 195576 kb
Host smart-fd80190e-65a5-4150-b4c4-8003f0ae8255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146813901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.4146813901
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1424752115
Short name T660
Test name
Test status
Simulation time 51189783 ps
CPU time 1.04 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:18:03 PM PDT 24
Peak memory 196240 kb
Host smart-0307b2bf-0395-4f68-a141-3836c87b0b60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424752115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1424752115
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1523502155
Short name T395
Test name
Test status
Simulation time 6139384994 ps
CPU time 66.63 seconds
Started Jun 24 05:18:07 PM PDT 24
Finished Jun 24 05:19:14 PM PDT 24
Peak memory 198016 kb
Host smart-7c9e4791-9da1-41a5-870a-791b223ad473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523502155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1523502155
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3773608203
Short name T620
Test name
Test status
Simulation time 1265234174173 ps
CPU time 2045.14 seconds
Started Jun 24 05:18:01 PM PDT 24
Finished Jun 24 05:52:08 PM PDT 24
Peak memory 198136 kb
Host smart-6bc95fd5-b955-4504-85cc-f67fd22edce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3773608203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3773608203
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2742320893
Short name T690
Test name
Test status
Simulation time 16130397 ps
CPU time 0.58 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:11 PM PDT 24
Peak memory 193552 kb
Host smart-4b06ce72-df6f-4958-b5a2-c60fa4c7c6f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742320893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2742320893
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.4282532157
Short name T466
Test name
Test status
Simulation time 27557818 ps
CPU time 0.7 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:14 PM PDT 24
Peak memory 194708 kb
Host smart-189a2097-3726-4880-9e97-1238dbfc6355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282532157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.4282532157
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1476146071
Short name T407
Test name
Test status
Simulation time 1433563932 ps
CPU time 20.87 seconds
Started Jun 24 05:18:07 PM PDT 24
Finished Jun 24 05:18:29 PM PDT 24
Peak memory 196912 kb
Host smart-6a47ea50-dbae-458b-8bdb-3c4925c87a6d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476146071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1476146071
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.607290416
Short name T590
Test name
Test status
Simulation time 115618298 ps
CPU time 0.89 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:12 PM PDT 24
Peak memory 196020 kb
Host smart-4cff4ba5-44db-439a-a5b0-b53e5163de5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607290416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.607290416
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.821662051
Short name T568
Test name
Test status
Simulation time 24045655 ps
CPU time 0.75 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 195464 kb
Host smart-1e32ceaf-b3a2-4442-9a96-381414824488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821662051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.821662051
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3033554309
Short name T17
Test name
Test status
Simulation time 247902517 ps
CPU time 2.17 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 198108 kb
Host smart-0bdb9db4-398c-49f8-a371-6d737c8ce021
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033554309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3033554309
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1482391709
Short name T181
Test name
Test status
Simulation time 572162752 ps
CPU time 2.86 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:14 PM PDT 24
Peak memory 196996 kb
Host smart-a9e1bd98-e9de-42d9-b2b1-a42dcbc88252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482391709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1482391709
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.360200516
Short name T527
Test name
Test status
Simulation time 504212029 ps
CPU time 1.26 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 196860 kb
Host smart-9fa56dde-f2c0-4c41-a637-f2e42e1afe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360200516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.360200516
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1425588146
Short name T321
Test name
Test status
Simulation time 301427189 ps
CPU time 1.11 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:11 PM PDT 24
Peak memory 196044 kb
Host smart-eadd03fd-4b99-4797-8dc7-70dbc8d582ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425588146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1425588146
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.909338537
Short name T675
Test name
Test status
Simulation time 471466991 ps
CPU time 4.77 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 197960 kb
Host smart-fa9b6917-9d77-495b-bb2f-63efe5f016b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909338537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.909338537
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3663236014
Short name T358
Test name
Test status
Simulation time 75183988 ps
CPU time 1.28 seconds
Started Jun 24 05:18:13 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 196724 kb
Host smart-6aa9b179-b4a6-4582-b0a1-f8637717dece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663236014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3663236014
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2938742366
Short name T268
Test name
Test status
Simulation time 125135346 ps
CPU time 1.23 seconds
Started Jun 24 05:18:14 PM PDT 24
Finished Jun 24 05:18:16 PM PDT 24
Peak memory 197984 kb
Host smart-f661628f-c3c7-4dcc-bb26-f737fc3e9eea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938742366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2938742366
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1184653215
Short name T414
Test name
Test status
Simulation time 11258267658 ps
CPU time 145.07 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:20:36 PM PDT 24
Peak memory 198040 kb
Host smart-f6c28875-f5a3-4d76-ae22-09d525c13561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184653215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1184653215
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.38032148
Short name T133
Test name
Test status
Simulation time 21546771 ps
CPU time 0.59 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 193624 kb
Host smart-78207fcc-802a-4aae-94e2-31b8b647af97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38032148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.38032148
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2459431252
Short name T496
Test name
Test status
Simulation time 28213661 ps
CPU time 0.63 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 193740 kb
Host smart-ca16e5cf-1446-4983-9e1c-02f003942f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459431252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2459431252
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.678718312
Short name T654
Test name
Test status
Simulation time 955709163 ps
CPU time 12.77 seconds
Started Jun 24 05:18:14 PM PDT 24
Finished Jun 24 05:18:27 PM PDT 24
Peak memory 197124 kb
Host smart-3e7c33af-d1f6-4f92-bb3e-052e4d09b511
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678718312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.678718312
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1629999452
Short name T381
Test name
Test status
Simulation time 41765327 ps
CPU time 0.85 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 196580 kb
Host smart-679c018f-c24e-4061-b99d-5c5c5eceb6e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629999452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1629999452
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3485394608
Short name T140
Test name
Test status
Simulation time 169080896 ps
CPU time 1.42 seconds
Started Jun 24 05:18:13 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 196884 kb
Host smart-0b7a97ce-3db8-4c7f-b4a8-3386caa543c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485394608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3485394608
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3712241230
Short name T550
Test name
Test status
Simulation time 169302767 ps
CPU time 3.51 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 198136 kb
Host smart-ce3dac26-2270-4c46-8031-4800eaca3e0c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712241230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3712241230
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3171682971
Short name T339
Test name
Test status
Simulation time 142190834 ps
CPU time 2.65 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:14 PM PDT 24
Peak memory 198076 kb
Host smart-32fd5bbb-dd21-4f6a-bde5-b91e65633014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171682971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3171682971
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1882184247
Short name T405
Test name
Test status
Simulation time 89396947 ps
CPU time 0.74 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:11 PM PDT 24
Peak memory 195956 kb
Host smart-f497ec27-9921-4dfb-8309-43a7e28fc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882184247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1882184247
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.675521112
Short name T302
Test name
Test status
Simulation time 24573891 ps
CPU time 0.76 seconds
Started Jun 24 05:18:12 PM PDT 24
Finished Jun 24 05:18:14 PM PDT 24
Peak memory 195256 kb
Host smart-7b47e5d7-179c-443d-af99-ece5e1edcc46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675521112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.675521112
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3251209841
Short name T7
Test name
Test status
Simulation time 1219983663 ps
CPU time 3.73 seconds
Started Jun 24 05:18:12 PM PDT 24
Finished Jun 24 05:18:17 PM PDT 24
Peak memory 197744 kb
Host smart-982f2692-7f91-4b22-b557-1c60262f9951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251209841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3251209841
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3807728614
Short name T240
Test name
Test status
Simulation time 46174325 ps
CPU time 0.98 seconds
Started Jun 24 05:18:13 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 195516 kb
Host smart-c8faf71f-44ea-421e-96c2-488cae53a691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807728614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3807728614
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.536857918
Short name T338
Test name
Test status
Simulation time 189719428 ps
CPU time 1.3 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 196248 kb
Host smart-40d8874d-00ec-4bd5-b2f0-bee467e822d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536857918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.536857918
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2114688327
Short name T110
Test name
Test status
Simulation time 31829688701 ps
CPU time 110.08 seconds
Started Jun 24 05:18:12 PM PDT 24
Finished Jun 24 05:20:03 PM PDT 24
Peak memory 198096 kb
Host smart-a9d81058-e0a7-4f0e-9d37-7876f2030984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114688327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2114688327
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.145228504
Short name T342
Test name
Test status
Simulation time 31589681850 ps
CPU time 936.37 seconds
Started Jun 24 05:18:07 PM PDT 24
Finished Jun 24 05:33:45 PM PDT 24
Peak memory 198220 kb
Host smart-aa2196b0-faf0-4a34-9cb6-ce2300a4925b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=145228504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.145228504
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1778530674
Short name T541
Test name
Test status
Simulation time 24263750 ps
CPU time 0.57 seconds
Started Jun 24 05:18:12 PM PDT 24
Finished Jun 24 05:18:14 PM PDT 24
Peak memory 193704 kb
Host smart-1ebe6c42-7c18-4427-99f5-9dc0dfba091f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778530674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1778530674
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.186304451
Short name T507
Test name
Test status
Simulation time 255522867 ps
CPU time 0.7 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:11 PM PDT 24
Peak memory 193724 kb
Host smart-e0efb7cb-9328-4f6f-937d-4e6bb845689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186304451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.186304451
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1967895994
Short name T196
Test name
Test status
Simulation time 955176874 ps
CPU time 12.54 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:23 PM PDT 24
Peak memory 196456 kb
Host smart-35dec83f-0864-4dfc-a17e-9558b9a201e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967895994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1967895994
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2026155924
Short name T484
Test name
Test status
Simulation time 30900323 ps
CPU time 0.72 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 194624 kb
Host smart-ea7594cc-620b-4141-9ee5-b32bd90adf4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026155924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2026155924
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.500615131
Short name T341
Test name
Test status
Simulation time 18488313 ps
CPU time 0.72 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:12 PM PDT 24
Peak memory 194996 kb
Host smart-fb5543d8-bcd2-4497-8044-6bbbd385b403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500615131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.500615131
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1060627620
Short name T561
Test name
Test status
Simulation time 69736471 ps
CPU time 1.69 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:11 PM PDT 24
Peak memory 198112 kb
Host smart-0e4db0e5-865f-45f3-9f6d-3192dda79073
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060627620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1060627620
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1832372531
Short name T523
Test name
Test status
Simulation time 117830323 ps
CPU time 1.94 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 195760 kb
Host smart-7b484545-469b-4056-a24d-ce69f6f194e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832372531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1832372531
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3662008953
Short name T303
Test name
Test status
Simulation time 129514683 ps
CPU time 0.95 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:11 PM PDT 24
Peak memory 196600 kb
Host smart-6d8c5319-3a16-465e-8cf2-1c8c005708e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662008953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3662008953
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.465858077
Short name T319
Test name
Test status
Simulation time 52449306 ps
CPU time 1.16 seconds
Started Jun 24 05:18:13 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 196696 kb
Host smart-b7af47e5-afef-4726-9d04-e298d025573b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465858077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.465858077
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3287283480
Short name T564
Test name
Test status
Simulation time 158923573 ps
CPU time 1.18 seconds
Started Jun 24 05:18:12 PM PDT 24
Finished Jun 24 05:18:15 PM PDT 24
Peak memory 196540 kb
Host smart-1cbd073d-0786-4a8d-97bf-cfa4a90bb2ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287283480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3287283480
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3428939488
Short name T714
Test name
Test status
Simulation time 107405911 ps
CPU time 1.25 seconds
Started Jun 24 05:18:11 PM PDT 24
Finished Jun 24 05:18:13 PM PDT 24
Peak memory 196736 kb
Host smart-0092c1f1-f6e0-45fb-aa28-8040461f7dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428939488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3428939488
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2053138001
Short name T615
Test name
Test status
Simulation time 399365251 ps
CPU time 1.25 seconds
Started Jun 24 05:18:09 PM PDT 24
Finished Jun 24 05:18:11 PM PDT 24
Peak memory 196740 kb
Host smart-19c7ce16-4b83-466a-92c5-530e7e1b94bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053138001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2053138001
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2877036621
Short name T707
Test name
Test status
Simulation time 13399270380 ps
CPU time 167.76 seconds
Started Jun 24 05:18:10 PM PDT 24
Finished Jun 24 05:20:59 PM PDT 24
Peak memory 198128 kb
Host smart-788d77fa-9620-4831-a71a-5516540dbd6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877036621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2877036621
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2212839331
Short name T448
Test name
Test status
Simulation time 33367874 ps
CPU time 0.6 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:23 PM PDT 24
Peak memory 193756 kb
Host smart-effc9389-a3a0-40e9-926b-06d400b6ccb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212839331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2212839331
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1025482599
Short name T702
Test name
Test status
Simulation time 126199664 ps
CPU time 0.83 seconds
Started Jun 24 05:18:20 PM PDT 24
Finished Jun 24 05:18:24 PM PDT 24
Peak memory 195356 kb
Host smart-44245294-da83-4b74-98b6-1bc3e96f3995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025482599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1025482599
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.513754889
Short name T644
Test name
Test status
Simulation time 2330541785 ps
CPU time 15.13 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:37 PM PDT 24
Peak memory 196956 kb
Host smart-ff10fd14-f2d5-4433-b313-5ae05eb55783
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513754889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.513754889
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.469292433
Short name T128
Test name
Test status
Simulation time 49205999 ps
CPU time 0.86 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:21 PM PDT 24
Peak memory 195656 kb
Host smart-6d12bcc8-a4ed-4052-9e51-2c87d51ae1af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469292433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.469292433
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.614195821
Short name T106
Test name
Test status
Simulation time 399797990 ps
CPU time 1.55 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:21 PM PDT 24
Peak memory 196488 kb
Host smart-a54ea7aa-bf0b-4c80-ae8b-7862509d047a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614195821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.614195821
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.179581421
Short name T259
Test name
Test status
Simulation time 319124181 ps
CPU time 3.33 seconds
Started Jun 24 05:18:22 PM PDT 24
Finished Jun 24 05:18:27 PM PDT 24
Peak memory 198020 kb
Host smart-76394b97-d917-41bc-b3cd-1363941270d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179581421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.179581421
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1160591455
Short name T432
Test name
Test status
Simulation time 138822403 ps
CPU time 2.75 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:22 PM PDT 24
Peak memory 197096 kb
Host smart-fb2320ea-d44b-425a-b5cd-5f1cef3d0ea3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160591455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1160591455
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3288822858
Short name T666
Test name
Test status
Simulation time 65614072 ps
CPU time 0.82 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:18:18 PM PDT 24
Peak memory 196452 kb
Host smart-2beb488d-aa82-474d-9afd-d26d1946720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288822858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3288822858
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4086602789
Short name T504
Test name
Test status
Simulation time 275894171 ps
CPU time 1.05 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:23 PM PDT 24
Peak memory 196584 kb
Host smart-185c893f-0d96-4a81-a1ef-94e6865fa52f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086602789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4086602789
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3382235543
Short name T597
Test name
Test status
Simulation time 128780307 ps
CPU time 3.18 seconds
Started Jun 24 05:18:20 PM PDT 24
Finished Jun 24 05:18:26 PM PDT 24
Peak memory 197828 kb
Host smart-06bf5bf7-6b43-4224-844e-9f065f7903b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382235543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3382235543
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3340435751
Short name T551
Test name
Test status
Simulation time 39676762 ps
CPU time 1.27 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:18:19 PM PDT 24
Peak memory 197940 kb
Host smart-89726b40-5461-45db-8b9f-9e0e9114c056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340435751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3340435751
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.764167239
Short name T61
Test name
Test status
Simulation time 34892476 ps
CPU time 1.16 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:22 PM PDT 24
Peak memory 196200 kb
Host smart-fbadf230-c0b8-49aa-8955-4c317997efe6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764167239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.764167239
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3075778794
Short name T280
Test name
Test status
Simulation time 57891781782 ps
CPU time 211.46 seconds
Started Jun 24 05:18:23 PM PDT 24
Finished Jun 24 05:21:55 PM PDT 24
Peak memory 198080 kb
Host smart-f5c63449-e5fa-4e55-b58e-4980bcf05947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075778794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3075778794
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3572711236
Short name T57
Test name
Test status
Simulation time 100206160450 ps
CPU time 508.25 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:26:47 PM PDT 24
Peak memory 206328 kb
Host smart-8b7bc24b-a4e3-401b-a365-f7084ed6509e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3572711236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3572711236
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2761759351
Short name T218
Test name
Test status
Simulation time 25191214 ps
CPU time 0.57 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:22 PM PDT 24
Peak memory 193696 kb
Host smart-ab4f3fb4-0aad-41c0-a78c-6db6b23bb3f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761759351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2761759351
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.326551228
Short name T365
Test name
Test status
Simulation time 16821730 ps
CPU time 0.67 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:18:19 PM PDT 24
Peak memory 193908 kb
Host smart-8b49117d-4100-4737-845b-23879194ce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326551228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.326551228
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.598835998
Short name T571
Test name
Test status
Simulation time 766940200 ps
CPU time 6.93 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:18:25 PM PDT 24
Peak memory 196688 kb
Host smart-2e8bd18c-aa29-4e43-9d26-69149eb97fb8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598835998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.598835998
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1687108832
Short name T20
Test name
Test status
Simulation time 384471067 ps
CPU time 1.01 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:23 PM PDT 24
Peak memory 197184 kb
Host smart-0d3e4315-f638-4e2f-93fa-136869c0257c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687108832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1687108832
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1729474131
Short name T154
Test name
Test status
Simulation time 25306222 ps
CPU time 0.74 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:20 PM PDT 24
Peak memory 194188 kb
Host smart-858ec7d6-261a-4ea9-8d82-754416ceea69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729474131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1729474131
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2480986677
Short name T229
Test name
Test status
Simulation time 94004751 ps
CPU time 3.58 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:23 PM PDT 24
Peak memory 198000 kb
Host smart-be5e76bd-f63e-4aa9-92b6-ac381c16a23f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480986677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2480986677
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3577207444
Short name T474
Test name
Test status
Simulation time 73594876 ps
CPU time 2.16 seconds
Started Jun 24 05:18:20 PM PDT 24
Finished Jun 24 05:18:25 PM PDT 24
Peak memory 196856 kb
Host smart-1c4747f6-d2f4-4d5e-8418-3b12b224e59a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577207444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3577207444
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1077989555
Short name T360
Test name
Test status
Simulation time 114938992 ps
CPU time 0.9 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:21 PM PDT 24
Peak memory 196708 kb
Host smart-e50f630d-12f2-46b1-9c33-619c9e65b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077989555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1077989555
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.259043129
Short name T209
Test name
Test status
Simulation time 237887752 ps
CPU time 1.26 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:22 PM PDT 24
Peak memory 198008 kb
Host smart-1b60033d-63e5-4532-9149-d8e22c2bfaa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259043129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.259043129
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2267971087
Short name T118
Test name
Test status
Simulation time 116807693 ps
CPU time 5.34 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:33 PM PDT 24
Peak memory 197972 kb
Host smart-dcb9af20-3ffe-42d0-a383-fb7491742a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267971087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2267971087
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3171901184
Short name T587
Test name
Test status
Simulation time 82367547 ps
CPU time 0.97 seconds
Started Jun 24 05:18:22 PM PDT 24
Finished Jun 24 05:18:25 PM PDT 24
Peak memory 196324 kb
Host smart-88e4e475-148f-45d5-9d8f-4c081b449b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171901184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3171901184
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3676765860
Short name T312
Test name
Test status
Simulation time 32327479 ps
CPU time 0.91 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:18:18 PM PDT 24
Peak memory 195276 kb
Host smart-c8f91225-79cb-4023-9f2f-5325ac8070ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676765860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3676765860
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.230316070
Short name T198
Test name
Test status
Simulation time 170972291535 ps
CPU time 166.89 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:21:08 PM PDT 24
Peak memory 198012 kb
Host smart-05a970ce-a0a5-4376-8d9d-6d77769b674e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230316070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.230316070
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.685073105
Short name T485
Test name
Test status
Simulation time 49537437 ps
CPU time 0.59 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:31 PM PDT 24
Peak memory 193784 kb
Host smart-ebdbbe67-cac9-4dda-959e-7844497b1445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685073105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.685073105
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1999167401
Short name T580
Test name
Test status
Simulation time 37081213 ps
CPU time 0.6 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:18:19 PM PDT 24
Peak memory 194600 kb
Host smart-40dead98-cb95-493a-ba62-163d425c1ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999167401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1999167401
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2229406563
Short name T588
Test name
Test status
Simulation time 959673658 ps
CPU time 12.86 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:33 PM PDT 24
Peak memory 196896 kb
Host smart-e2e996b0-fbda-4b7b-86ab-f9c85c206152
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229406563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2229406563
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.217499923
Short name T234
Test name
Test status
Simulation time 37983199 ps
CPU time 0.77 seconds
Started Jun 24 05:18:18 PM PDT 24
Finished Jun 24 05:18:20 PM PDT 24
Peak memory 196580 kb
Host smart-e707411a-22cb-47c4-a77b-f9bffbf5f777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217499923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.217499923
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1732826877
Short name T148
Test name
Test status
Simulation time 179186935 ps
CPU time 1.22 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:22 PM PDT 24
Peak memory 197136 kb
Host smart-c3f423ad-327f-4aa5-bd2c-07a804b39623
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732826877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1732826877
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1430676851
Short name T293
Test name
Test status
Simulation time 227354101 ps
CPU time 2.63 seconds
Started Jun 24 05:18:17 PM PDT 24
Finished Jun 24 05:18:21 PM PDT 24
Peak memory 196324 kb
Host smart-1ae6be4d-1e8d-40a7-935a-98cdd3d0be10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430676851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1430676851
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1854444351
Short name T199
Test name
Test status
Simulation time 31842253 ps
CPU time 0.87 seconds
Started Jun 24 05:18:21 PM PDT 24
Finished Jun 24 05:18:24 PM PDT 24
Peak memory 194332 kb
Host smart-793fc9e0-78ed-4a5d-a817-d748b3c7197f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854444351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1854444351
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.552034451
Short name T52
Test name
Test status
Simulation time 45703146 ps
CPU time 0.72 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:23 PM PDT 24
Peak memory 194164 kb
Host smart-5c89b7ce-3871-4f24-9358-f32bce53ac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552034451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.552034451
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3451806740
Short name T625
Test name
Test status
Simulation time 162411808 ps
CPU time 1.15 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:22 PM PDT 24
Peak memory 195948 kb
Host smart-bff4aa62-a316-46b4-8cbb-d3b2a6342c17
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451806740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3451806740
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.3831264308
Short name T287
Test name
Test status
Simulation time 705073880 ps
CPU time 1.65 seconds
Started Jun 24 05:18:21 PM PDT 24
Finished Jun 24 05:18:25 PM PDT 24
Peak memory 197856 kb
Host smart-6f2b6454-342a-4b35-b407-42b73c7ac2d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831264308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.3831264308
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2606813370
Short name T599
Test name
Test status
Simulation time 57912666 ps
CPU time 1.54 seconds
Started Jun 24 05:18:19 PM PDT 24
Finished Jun 24 05:18:23 PM PDT 24
Peak memory 198268 kb
Host smart-396b89d5-5293-4882-95d3-39c960d10c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606813370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2606813370
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2007459782
Short name T359
Test name
Test status
Simulation time 100162731 ps
CPU time 1.68 seconds
Started Jun 24 05:18:15 PM PDT 24
Finished Jun 24 05:18:18 PM PDT 24
Peak memory 197056 kb
Host smart-d289cf47-bd89-48b4-9448-5635df4de79d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007459782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2007459782
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3237070143
Short name T301
Test name
Test status
Simulation time 3759009363 ps
CPU time 99.53 seconds
Started Jun 24 05:18:20 PM PDT 24
Finished Jun 24 05:20:03 PM PDT 24
Peak memory 198100 kb
Host smart-a531d792-e792-4499-b154-7e51e947d2f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237070143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3237070143
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3782925451
Short name T356
Test name
Test status
Simulation time 38144005 ps
CPU time 0.57 seconds
Started Jun 24 05:17:30 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 193644 kb
Host smart-ba034b07-b610-4fb5-83eb-717579cc0a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782925451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3782925451
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.518795890
Short name T577
Test name
Test status
Simulation time 38295331 ps
CPU time 0.9 seconds
Started Jun 24 05:17:29 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 195032 kb
Host smart-6b624506-419e-4a9f-b65d-8618884b9b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518795890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.518795890
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.560361674
Short name T315
Test name
Test status
Simulation time 3407280938 ps
CPU time 25.25 seconds
Started Jun 24 05:17:32 PM PDT 24
Finished Jun 24 05:17:58 PM PDT 24
Peak memory 198092 kb
Host smart-70ae65ab-ea7c-4d4c-8ece-9dadfdf292d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560361674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.560361674
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2666270548
Short name T596
Test name
Test status
Simulation time 302932331 ps
CPU time 0.76 seconds
Started Jun 24 05:17:31 PM PDT 24
Finished Jun 24 05:17:33 PM PDT 24
Peak memory 195744 kb
Host smart-d138081d-c025-4c89-9a1f-8156596e1275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666270548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2666270548
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1121347285
Short name T556
Test name
Test status
Simulation time 85190430 ps
CPU time 1.3 seconds
Started Jun 24 05:17:29 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 198028 kb
Host smart-86e96cd6-dc56-465d-8d04-6a9eaaff7272
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121347285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1121347285
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.3337538992
Short name T505
Test name
Test status
Simulation time 122546863 ps
CPU time 1.29 seconds
Started Jun 24 05:17:29 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 198088 kb
Host smart-618859e4-d41b-41a0-ad1f-5a64c5b4a96d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337538992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.3337538992
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1604999998
Short name T457
Test name
Test status
Simulation time 381430429 ps
CPU time 3.02 seconds
Started Jun 24 05:17:32 PM PDT 24
Finished Jun 24 05:17:36 PM PDT 24
Peak memory 196468 kb
Host smart-2d9ae5fb-1645-4b34-99f5-a57b2daf4040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604999998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1604999998
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3998952249
Short name T109
Test name
Test status
Simulation time 134817238 ps
CPU time 0.73 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:29 PM PDT 24
Peak memory 195396 kb
Host smart-9d6f2c4c-d52a-4f99-b958-49dcf876bb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998952249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3998952249
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2991314810
Short name T224
Test name
Test status
Simulation time 107447309 ps
CPU time 0.9 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:30 PM PDT 24
Peak memory 196612 kb
Host smart-e905d434-4d59-481e-bf95-8ec25bdeb216
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991314810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2991314810
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.303063010
Short name T593
Test name
Test status
Simulation time 45273733 ps
CPU time 2.14 seconds
Started Jun 24 05:17:33 PM PDT 24
Finished Jun 24 05:17:35 PM PDT 24
Peak memory 197928 kb
Host smart-c1753f75-78a6-45af-80a2-615475e29e6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303063010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.303063010
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2177851805
Short name T46
Test name
Test status
Simulation time 214935668 ps
CPU time 0.87 seconds
Started Jun 24 05:17:29 PM PDT 24
Finished Jun 24 05:17:32 PM PDT 24
Peak memory 213592 kb
Host smart-0ccfc0ff-a62f-4a06-9667-6f4ac8803ffc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177851805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2177851805
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3907944559
Short name T270
Test name
Test status
Simulation time 90116951 ps
CPU time 0.84 seconds
Started Jun 24 05:17:32 PM PDT 24
Finished Jun 24 05:17:34 PM PDT 24
Peak memory 195148 kb
Host smart-37be7a0e-4a5d-425a-8b57-a2986a7e3c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907944559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3907944559
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1858615243
Short name T559
Test name
Test status
Simulation time 123654811 ps
CPU time 1.19 seconds
Started Jun 24 05:17:28 PM PDT 24
Finished Jun 24 05:17:31 PM PDT 24
Peak memory 196360 kb
Host smart-51ed7617-584b-4541-ade7-0a04d3ac53ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858615243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1858615243
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.804685863
Short name T6
Test name
Test status
Simulation time 33409635005 ps
CPU time 201.38 seconds
Started Jun 24 05:17:30 PM PDT 24
Finished Jun 24 05:20:53 PM PDT 24
Peak memory 198400 kb
Host smart-b1b908c8-69bf-4548-9053-928991802630
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804685863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.804685863
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1762805599
Short name T614
Test name
Test status
Simulation time 464041777569 ps
CPU time 2126.64 seconds
Started Jun 24 05:17:31 PM PDT 24
Finished Jun 24 05:52:59 PM PDT 24
Peak memory 198140 kb
Host smart-f21232cf-a646-438d-b4b3-bb272ca86411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1762805599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1762805599
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1370888183
Short name T114
Test name
Test status
Simulation time 13528633 ps
CPU time 0.57 seconds
Started Jun 24 05:18:24 PM PDT 24
Finished Jun 24 05:18:27 PM PDT 24
Peak memory 194244 kb
Host smart-bdd22c0a-0321-4a39-9c12-fc4eeda5ea3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370888183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1370888183
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.14158156
Short name T598
Test name
Test status
Simulation time 70916916 ps
CPU time 0.85 seconds
Started Jun 24 05:18:29 PM PDT 24
Finished Jun 24 05:18:33 PM PDT 24
Peak memory 195308 kb
Host smart-3b4237b8-18ac-4096-b7d3-16a8b09bbf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14158156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.14158156
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3056399257
Short name T193
Test name
Test status
Simulation time 9712742338 ps
CPU time 20.49 seconds
Started Jun 24 05:18:29 PM PDT 24
Finished Jun 24 05:18:53 PM PDT 24
Peak memory 197024 kb
Host smart-0068319f-98ab-421c-8314-36c87aa748c3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056399257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3056399257
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3518804057
Short name T683
Test name
Test status
Simulation time 63484138 ps
CPU time 0.88 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:28 PM PDT 24
Peak memory 195896 kb
Host smart-07442794-9b05-4891-aa90-b11086635c87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518804057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3518804057
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4169602720
Short name T115
Test name
Test status
Simulation time 35681764 ps
CPU time 0.7 seconds
Started Jun 24 05:18:28 PM PDT 24
Finished Jun 24 05:18:32 PM PDT 24
Peak memory 194892 kb
Host smart-6d4bd56b-b152-41bd-8be3-65edc5035965
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169602720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4169602720
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3290217486
Short name T442
Test name
Test status
Simulation time 179573514 ps
CPU time 3.46 seconds
Started Jun 24 05:18:28 PM PDT 24
Finished Jun 24 05:18:35 PM PDT 24
Peak memory 198028 kb
Host smart-d859507c-c775-4e6c-a206-172575ee02e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290217486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3290217486
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1400894267
Short name T511
Test name
Test status
Simulation time 481693261 ps
CPU time 3.52 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:31 PM PDT 24
Peak memory 198020 kb
Host smart-e567ab71-2b30-4321-bc6e-2a7f2578b2fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400894267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1400894267
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2968973808
Short name T600
Test name
Test status
Simulation time 64566397 ps
CPU time 0.64 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 194144 kb
Host smart-5a789c6b-d8fd-4a65-a5dc-e7c2515eb643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968973808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2968973808
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1486857782
Short name T489
Test name
Test status
Simulation time 31700209 ps
CPU time 0.74 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 195356 kb
Host smart-9c6b1801-eb4c-46be-80cf-c7011dd0d480
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486857782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1486857782
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2553472883
Short name T418
Test name
Test status
Simulation time 83846095 ps
CPU time 3.77 seconds
Started Jun 24 05:18:24 PM PDT 24
Finished Jun 24 05:18:31 PM PDT 24
Peak memory 197880 kb
Host smart-9770b881-46f9-41fa-8f07-88cf4f205011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553472883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2553472883
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3227599429
Short name T202
Test name
Test status
Simulation time 85982487 ps
CPU time 1.32 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:32 PM PDT 24
Peak memory 196552 kb
Host smart-e3a16ffc-80f9-4f71-891a-54b7809a55c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227599429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3227599429
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.269001734
Short name T238
Test name
Test status
Simulation time 58919620 ps
CPU time 1.11 seconds
Started Jun 24 05:18:29 PM PDT 24
Finished Jun 24 05:18:34 PM PDT 24
Peak memory 195700 kb
Host smart-f6ecfc25-da28-4f8c-80d2-9695334e4ea0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269001734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.269001734
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3062575076
Short name T214
Test name
Test status
Simulation time 6626075101 ps
CPU time 158.49 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:21:07 PM PDT 24
Peak memory 198032 kb
Host smart-4694c8fd-cb71-4a66-a21e-b707626c2b67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062575076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3062575076
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.708964530
Short name T59
Test name
Test status
Simulation time 42730790278 ps
CPU time 562.3 seconds
Started Jun 24 05:18:33 PM PDT 24
Finished Jun 24 05:27:57 PM PDT 24
Peak memory 198040 kb
Host smart-225a1e0c-23bf-4395-a728-776edc8388b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=708964530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.708964530
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1936965070
Short name T554
Test name
Test status
Simulation time 52020795 ps
CPU time 0.55 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:31 PM PDT 24
Peak memory 193388 kb
Host smart-8a616288-e5fa-47d7-bf74-8a78410c5979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936965070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1936965070
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.469784561
Short name T645
Test name
Test status
Simulation time 80154683 ps
CPU time 0.66 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:28 PM PDT 24
Peak memory 193856 kb
Host smart-07eaffc3-bf31-4e3b-bf06-8b40062c88f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469784561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.469784561
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3609632016
Short name T510
Test name
Test status
Simulation time 273187181 ps
CPU time 5.65 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:35 PM PDT 24
Peak memory 196784 kb
Host smart-1b06d80c-fc13-4ac3-9fa8-c638f4a1d779
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609632016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3609632016
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.915198168
Short name T21
Test name
Test status
Simulation time 512545750 ps
CPU time 0.96 seconds
Started Jun 24 05:18:28 PM PDT 24
Finished Jun 24 05:18:32 PM PDT 24
Peak memory 197040 kb
Host smart-a49611c1-6dd6-49a0-a104-828f570e45d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915198168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.915198168
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.942618191
Short name T553
Test name
Test status
Simulation time 26360078 ps
CPU time 0.84 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:29 PM PDT 24
Peak memory 196324 kb
Host smart-fa8bc2c8-5488-4f64-a84e-7c4abe3f22a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942618191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.942618191
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1285579362
Short name T672
Test name
Test status
Simulation time 199357507 ps
CPU time 1.03 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 196256 kb
Host smart-94ff80a7-1d16-4f65-ad49-4bf13001e850
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285579362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1285579362
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.489597025
Short name T461
Test name
Test status
Simulation time 81330040 ps
CPU time 1.83 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 195728 kb
Host smart-fadfc1d4-f988-4e20-8dea-2dfa8da930d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489597025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
489597025
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.38253844
Short name T25
Test name
Test status
Simulation time 81660272 ps
CPU time 0.94 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 196700 kb
Host smart-6adf0f70-e989-4fde-9653-3fcb9264e725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38253844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.38253844
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1898964298
Short name T491
Test name
Test status
Simulation time 90549743 ps
CPU time 1.04 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:28 PM PDT 24
Peak memory 195916 kb
Host smart-1c195d96-ca80-428c-b114-1e9463967dfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898964298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1898964298
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.1392975228
Short name T284
Test name
Test status
Simulation time 111811310 ps
CPU time 2.17 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:32 PM PDT 24
Peak memory 197872 kb
Host smart-801f0a2b-1188-4284-a5b7-fb4e6197305d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392975228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.1392975228
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2934822238
Short name T712
Test name
Test status
Simulation time 135602301 ps
CPU time 1.02 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:28 PM PDT 24
Peak memory 195512 kb
Host smart-3fe726ac-78e8-446c-8295-20b4c69b1bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934822238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2934822238
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2955042391
Short name T219
Test name
Test status
Simulation time 44786006 ps
CPU time 1.25 seconds
Started Jun 24 05:18:24 PM PDT 24
Finished Jun 24 05:18:27 PM PDT 24
Peak memory 196372 kb
Host smart-4e5b11fc-3b05-4b28-912d-2fc8f8fdc69f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955042391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2955042391
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.790458332
Short name T454
Test name
Test status
Simulation time 13113885509 ps
CPU time 73.52 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:19:42 PM PDT 24
Peak memory 198096 kb
Host smart-b70335c0-200a-438c-bd52-d4526b6098b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790458332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.790458332
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.4053785920
Short name T560
Test name
Test status
Simulation time 32149405538 ps
CPU time 1019.62 seconds
Started Jun 24 05:18:27 PM PDT 24
Finished Jun 24 05:35:30 PM PDT 24
Peak memory 198140 kb
Host smart-5e961e9d-8391-44f0-b69b-01cfb96514d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4053785920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.4053785920
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.52991198
Short name T112
Test name
Test status
Simulation time 79422908 ps
CPU time 0.58 seconds
Started Jun 24 05:18:40 PM PDT 24
Finished Jun 24 05:18:41 PM PDT 24
Peak memory 194488 kb
Host smart-2abc81d7-10df-4823-9fe7-022771143fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52991198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.52991198
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2454809943
Short name T423
Test name
Test status
Simulation time 34549532 ps
CPU time 0.82 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:28 PM PDT 24
Peak memory 195324 kb
Host smart-f1d848ac-f653-49b4-80d4-557b29ffe524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454809943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2454809943
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1342639132
Short name T376
Test name
Test status
Simulation time 408117396 ps
CPU time 2.96 seconds
Started Jun 24 05:18:28 PM PDT 24
Finished Jun 24 05:18:34 PM PDT 24
Peak memory 196388 kb
Host smart-396db183-9ed6-49d9-ad23-fa058cdc2031
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342639132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1342639132
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3838964086
Short name T111
Test name
Test status
Simulation time 732749613 ps
CPU time 1 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:31 PM PDT 24
Peak memory 196036 kb
Host smart-3a70d309-ee30-41a3-b221-a1d9ff199435
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838964086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3838964086
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.4134043850
Short name T464
Test name
Test status
Simulation time 38719221 ps
CPU time 0.85 seconds
Started Jun 24 05:18:29 PM PDT 24
Finished Jun 24 05:18:33 PM PDT 24
Peak memory 196276 kb
Host smart-269a6cbb-9606-4f89-99a9-7a74dfe58997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134043850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.4134043850
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.522853040
Short name T710
Test name
Test status
Simulation time 49087746 ps
CPU time 1.18 seconds
Started Jun 24 05:18:24 PM PDT 24
Finished Jun 24 05:18:27 PM PDT 24
Peak memory 197912 kb
Host smart-90bc5c95-e9b2-4f7a-ac42-bfc6d20566b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522853040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.522853040
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3220352076
Short name T632
Test name
Test status
Simulation time 143509793 ps
CPU time 1.74 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 196156 kb
Host smart-30917958-4271-4007-bbe9-0d890d7154bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220352076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3220352076
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1795282947
Short name T353
Test name
Test status
Simulation time 43372100 ps
CPU time 1.05 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 196504 kb
Host smart-63dcb924-bf31-4a11-816a-06b1bebadc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795282947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1795282947
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3051760338
Short name T370
Test name
Test status
Simulation time 57849578 ps
CPU time 1.09 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:28 PM PDT 24
Peak memory 196600 kb
Host smart-047074d5-7160-4657-8fe6-a5aed1989783
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051760338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3051760338
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3651280399
Short name T372
Test name
Test status
Simulation time 710611222 ps
CPU time 1.57 seconds
Started Jun 24 05:18:24 PM PDT 24
Finished Jun 24 05:18:27 PM PDT 24
Peak memory 197568 kb
Host smart-952322df-2f3b-40ed-81ca-58ce19dec092
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651280399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3651280399
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.609518695
Short name T296
Test name
Test status
Simulation time 104223118 ps
CPU time 0.97 seconds
Started Jun 24 05:18:31 PM PDT 24
Finished Jun 24 05:18:35 PM PDT 24
Peak memory 195224 kb
Host smart-5c876b2c-5e5f-4bd8-9521-b3b4e0a4f1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609518695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.609518695
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2052312587
Short name T610
Test name
Test status
Simulation time 94126080 ps
CPU time 1.2 seconds
Started Jun 24 05:18:25 PM PDT 24
Finished Jun 24 05:18:30 PM PDT 24
Peak memory 196608 kb
Host smart-a14dda92-f0ca-479d-89ca-cdc25472f905
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052312587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2052312587
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2837618290
Short name T428
Test name
Test status
Simulation time 31928529249 ps
CPU time 62.92 seconds
Started Jun 24 05:18:26 PM PDT 24
Finished Jun 24 05:19:33 PM PDT 24
Peak memory 197912 kb
Host smart-b6476c98-e5e6-4164-be3c-c5e10c68f50b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837618290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2837618290
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1350620686
Short name T486
Test name
Test status
Simulation time 12667656 ps
CPU time 0.57 seconds
Started Jun 24 05:18:34 PM PDT 24
Finished Jun 24 05:18:36 PM PDT 24
Peak memory 193760 kb
Host smart-c53926e1-f903-40d4-9f69-24f3a5a5e582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350620686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1350620686
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3126708805
Short name T210
Test name
Test status
Simulation time 38243232 ps
CPU time 0.8 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:18:38 PM PDT 24
Peak memory 195260 kb
Host smart-e1ee4cc1-c476-47c4-ac3a-711bdf55418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126708805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3126708805
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1572637036
Short name T195
Test name
Test status
Simulation time 4477355767 ps
CPU time 20.16 seconds
Started Jun 24 05:18:37 PM PDT 24
Finished Jun 24 05:18:59 PM PDT 24
Peak memory 196972 kb
Host smart-ddce764c-8f5b-4ac5-8a6c-f2846f6ae161
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572637036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1572637036
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2361053679
Short name T667
Test name
Test status
Simulation time 65422978 ps
CPU time 0.61 seconds
Started Jun 24 05:18:37 PM PDT 24
Finished Jun 24 05:18:39 PM PDT 24
Peak memory 195056 kb
Host smart-1cca3331-7557-4d09-adcd-58c85b776002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361053679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2361053679
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3923440568
Short name T578
Test name
Test status
Simulation time 140559339 ps
CPU time 0.8 seconds
Started Jun 24 05:18:37 PM PDT 24
Finished Jun 24 05:18:40 PM PDT 24
Peak memory 195528 kb
Host smart-1f2472f2-71fd-470e-afa7-4a99faddc91c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923440568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3923440568
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.684179624
Short name T431
Test name
Test status
Simulation time 159444045 ps
CPU time 3.14 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:18:41 PM PDT 24
Peak memory 198388 kb
Host smart-12c4b95e-b4ae-48a7-9256-98ffeb92453e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684179624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.684179624
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.534581738
Short name T641
Test name
Test status
Simulation time 47430434 ps
CPU time 1.36 seconds
Started Jun 24 05:18:34 PM PDT 24
Finished Jun 24 05:18:37 PM PDT 24
Peak memory 196620 kb
Host smart-49d0301f-86a7-4d75-9526-31f5f1fa9cce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534581738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
534581738
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2074817237
Short name T701
Test name
Test status
Simulation time 72927429 ps
CPU time 0.92 seconds
Started Jun 24 05:18:33 PM PDT 24
Finished Jun 24 05:18:36 PM PDT 24
Peak memory 195656 kb
Host smart-8f9f69e5-b3ac-4c8a-a77f-6a2358cfa084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074817237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2074817237
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3203377891
Short name T306
Test name
Test status
Simulation time 15259877 ps
CPU time 0.68 seconds
Started Jun 24 05:18:34 PM PDT 24
Finished Jun 24 05:18:37 PM PDT 24
Peak memory 195312 kb
Host smart-da057e55-7fc8-4c68-aed9-d80fa0cedcf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203377891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3203377891
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2660636423
Short name T294
Test name
Test status
Simulation time 407281850 ps
CPU time 3.54 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:18:41 PM PDT 24
Peak memory 197780 kb
Host smart-3f907157-153d-4ab1-b4b5-ae17dfc1a8cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660636423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2660636423
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1499177404
Short name T266
Test name
Test status
Simulation time 47890437 ps
CPU time 1.33 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:18:38 PM PDT 24
Peak memory 197824 kb
Host smart-ec62762f-e96b-442b-a7a5-b3d8767b18b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499177404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1499177404
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3193988812
Short name T558
Test name
Test status
Simulation time 74199857 ps
CPU time 0.78 seconds
Started Jun 24 05:18:40 PM PDT 24
Finished Jun 24 05:18:42 PM PDT 24
Peak memory 195912 kb
Host smart-be45c1ab-c9e5-4cc6-83bb-aea0928ea175
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193988812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3193988812
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1915327264
Short name T117
Test name
Test status
Simulation time 14947799548 ps
CPU time 230.34 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:22:28 PM PDT 24
Peak memory 197964 kb
Host smart-d0f56628-c749-4c2f-8b74-5e2df185bf13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915327264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1915327264
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2278119678
Short name T642
Test name
Test status
Simulation time 15243097 ps
CPU time 0.59 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:18:39 PM PDT 24
Peak memory 193724 kb
Host smart-f67c65ba-0dec-45cf-a573-901da4193f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278119678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2278119678
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2043247886
Short name T569
Test name
Test status
Simulation time 104178700 ps
CPU time 0.96 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:18:39 PM PDT 24
Peak memory 196580 kb
Host smart-7bcf68cf-28c2-485b-88bb-1e385cab1520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043247886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2043247886
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3464799130
Short name T134
Test name
Test status
Simulation time 504501147 ps
CPU time 14.34 seconds
Started Jun 24 05:18:39 PM PDT 24
Finished Jun 24 05:18:55 PM PDT 24
Peak memory 197944 kb
Host smart-b3680d5f-3d6e-44a9-8885-c4612499cd4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464799130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3464799130
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2179781359
Short name T415
Test name
Test status
Simulation time 327647485 ps
CPU time 0.99 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:18:39 PM PDT 24
Peak memory 196548 kb
Host smart-1a4f17cb-5870-409d-893f-941b7eb02496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179781359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2179781359
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1988316401
Short name T27
Test name
Test status
Simulation time 287837898 ps
CPU time 1.11 seconds
Started Jun 24 05:18:37 PM PDT 24
Finished Jun 24 05:18:40 PM PDT 24
Peak memory 196556 kb
Host smart-b877d59e-0055-4d46-a3ab-7700977ecd53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988316401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1988316401
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.117147627
Short name T494
Test name
Test status
Simulation time 105641112 ps
CPU time 2.32 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:18:40 PM PDT 24
Peak memory 198120 kb
Host smart-251ba9af-56f8-4494-aa73-f104bda0f7fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117147627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.117147627
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3558541212
Short name T164
Test name
Test status
Simulation time 162311909 ps
CPU time 3.63 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:18:42 PM PDT 24
Peak memory 198036 kb
Host smart-56da13a0-b2a5-428d-98a6-2cf312c64b6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558541212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3558541212
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3498635529
Short name T617
Test name
Test status
Simulation time 28947002 ps
CPU time 0.86 seconds
Started Jun 24 05:18:34 PM PDT 24
Finished Jun 24 05:18:37 PM PDT 24
Peak memory 195488 kb
Host smart-09e4050f-b9de-41de-8acf-308cd5f3d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498635529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3498635529
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3516111842
Short name T611
Test name
Test status
Simulation time 17646795 ps
CPU time 0.68 seconds
Started Jun 24 05:18:39 PM PDT 24
Finished Jun 24 05:18:40 PM PDT 24
Peak memory 194896 kb
Host smart-64b2176f-f3bb-4ea4-bcbf-b835ace9c18d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516111842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3516111842
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2736653344
Short name T241
Test name
Test status
Simulation time 248587873 ps
CPU time 3.49 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:18:41 PM PDT 24
Peak memory 197868 kb
Host smart-ab0c88f3-7871-49ca-b74b-9b8ae99b739b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736653344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2736653344
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2849165201
Short name T539
Test name
Test status
Simulation time 76093923 ps
CPU time 1.27 seconds
Started Jun 24 05:18:34 PM PDT 24
Finished Jun 24 05:18:37 PM PDT 24
Peak memory 195816 kb
Host smart-400033f4-a77d-47b5-beae-b05551d21a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849165201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2849165201
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2564046545
Short name T131
Test name
Test status
Simulation time 50080239 ps
CPU time 1.09 seconds
Started Jun 24 05:18:39 PM PDT 24
Finished Jun 24 05:18:41 PM PDT 24
Peak memory 195740 kb
Host smart-e9997040-87be-4326-9209-56d2ce8aeb6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564046545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2564046545
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2690895682
Short name T536
Test name
Test status
Simulation time 3401083177 ps
CPU time 95.41 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:20:13 PM PDT 24
Peak memory 198104 kb
Host smart-2737d77f-6dd0-46b4-a9f6-5c0354c4ceb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690895682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2690895682
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1808158664
Short name T665
Test name
Test status
Simulation time 53607775700 ps
CPU time 1283.28 seconds
Started Jun 24 05:18:37 PM PDT 24
Finished Jun 24 05:40:02 PM PDT 24
Peak memory 198056 kb
Host smart-f10617d7-8b99-4ce5-b54a-47c8891358c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1808158664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1808158664
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1521146009
Short name T546
Test name
Test status
Simulation time 33919702 ps
CPU time 0.57 seconds
Started Jun 24 05:18:42 PM PDT 24
Finished Jun 24 05:18:44 PM PDT 24
Peak memory 194484 kb
Host smart-f1f7d695-2c24-420c-954d-771fcd090c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521146009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1521146009
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.302367686
Short name T661
Test name
Test status
Simulation time 97538088 ps
CPU time 0.86 seconds
Started Jun 24 05:18:34 PM PDT 24
Finished Jun 24 05:18:37 PM PDT 24
Peak memory 196384 kb
Host smart-8ff78cde-f92f-45ee-9637-e8adc465bb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302367686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.302367686
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.365414415
Short name T146
Test name
Test status
Simulation time 4596934358 ps
CPU time 13.66 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:19:00 PM PDT 24
Peak memory 196604 kb
Host smart-32b57ea4-3662-4b49-844e-685a346fd970
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365414415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.365414415
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3953622803
Short name T389
Test name
Test status
Simulation time 207791712 ps
CPU time 0.92 seconds
Started Jun 24 05:18:42 PM PDT 24
Finished Jun 24 05:18:44 PM PDT 24
Peak memory 195916 kb
Host smart-29dc5850-d119-4f84-a7fb-fc2b2e0f5360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953622803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3953622803
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1681491841
Short name T691
Test name
Test status
Simulation time 82624546 ps
CPU time 0.85 seconds
Started Jun 24 05:18:38 PM PDT 24
Finished Jun 24 05:18:40 PM PDT 24
Peak memory 195272 kb
Host smart-24efc1ef-2043-4885-87ed-e42cb4a04394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681491841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1681491841
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2284512421
Short name T400
Test name
Test status
Simulation time 27918659 ps
CPU time 1.19 seconds
Started Jun 24 05:18:41 PM PDT 24
Finished Jun 24 05:18:43 PM PDT 24
Peak memory 196492 kb
Host smart-e527dd7b-0b30-4d5a-85cc-dbe1ce5432ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284512421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2284512421
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1153110721
Short name T528
Test name
Test status
Simulation time 594069414 ps
CPU time 2.63 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:18:39 PM PDT 24
Peak memory 197032 kb
Host smart-ef348bb6-a1a8-49cc-a156-bfd70ecb8112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153110721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1153110721
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2840598013
Short name T430
Test name
Test status
Simulation time 24165404 ps
CPU time 0.79 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:18:39 PM PDT 24
Peak memory 195256 kb
Host smart-571575e6-bf7e-4884-bbb9-17aebf564f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840598013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2840598013
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3428486055
Short name T124
Test name
Test status
Simulation time 77476929 ps
CPU time 0.9 seconds
Started Jun 24 05:18:35 PM PDT 24
Finished Jun 24 05:18:38 PM PDT 24
Peak memory 195916 kb
Host smart-55c2f4ab-242e-47fe-aa87-bdfb3f24949b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428486055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3428486055
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.233098290
Short name T228
Test name
Test status
Simulation time 112050291 ps
CPU time 2.6 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:18:50 PM PDT 24
Peak memory 197964 kb
Host smart-9530ab08-4c4e-45aa-9689-676927358e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233098290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.233098290
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2795138604
Short name T530
Test name
Test status
Simulation time 158856745 ps
CPU time 1.35 seconds
Started Jun 24 05:18:37 PM PDT 24
Finished Jun 24 05:18:40 PM PDT 24
Peak memory 196696 kb
Host smart-4c94cc02-0eb2-4c5b-b0c9-fa44259cddb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795138604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2795138604
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2827275919
Short name T695
Test name
Test status
Simulation time 378834920 ps
CPU time 1.08 seconds
Started Jun 24 05:18:36 PM PDT 24
Finished Jun 24 05:18:39 PM PDT 24
Peak memory 195612 kb
Host smart-ab584154-e7f7-42fb-a76f-2f263afaa9ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827275919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2827275919
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1359318401
Short name T416
Test name
Test status
Simulation time 62840820843 ps
CPU time 175.28 seconds
Started Jun 24 05:18:42 PM PDT 24
Finished Jun 24 05:21:38 PM PDT 24
Peak memory 198000 kb
Host smart-9d0e11fc-e022-4acc-94f3-e089b1640a56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359318401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1359318401
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3598266640
Short name T648
Test name
Test status
Simulation time 40220896 ps
CPU time 0.56 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:18:48 PM PDT 24
Peak memory 193376 kb
Host smart-36772f74-4c07-478e-bfa7-d31a2ed97d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598266640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3598266640
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.51462042
Short name T49
Test name
Test status
Simulation time 47769950 ps
CPU time 0.91 seconds
Started Jun 24 05:18:44 PM PDT 24
Finished Jun 24 05:18:46 PM PDT 24
Peak memory 196116 kb
Host smart-cfa59f12-1a75-4c6a-a38f-930c95a24111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51462042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.51462042
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1865360167
Short name T159
Test name
Test status
Simulation time 1971998234 ps
CPU time 25.8 seconds
Started Jun 24 05:18:45 PM PDT 24
Finished Jun 24 05:19:12 PM PDT 24
Peak memory 196960 kb
Host smart-4f988630-5833-42ff-8604-fff0a0fff028
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865360167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1865360167
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2572543185
Short name T10
Test name
Test status
Simulation time 216735697 ps
CPU time 0.9 seconds
Started Jun 24 05:18:41 PM PDT 24
Finished Jun 24 05:18:43 PM PDT 24
Peak memory 195968 kb
Host smart-0f7043b1-f382-4422-bafb-cc90ad609e45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572543185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2572543185
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3163375037
Short name T380
Test name
Test status
Simulation time 167516440 ps
CPU time 1.23 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:18:48 PM PDT 24
Peak memory 198024 kb
Host smart-4c70e96d-d9a3-4d18-af27-986552dcff35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163375037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3163375037
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.953323640
Short name T179
Test name
Test status
Simulation time 165956756 ps
CPU time 1.63 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:18:49 PM PDT 24
Peak memory 196788 kb
Host smart-3ef2a91a-c30b-43d4-b1fc-298d5029ad4c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953323640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.953323640
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3670228664
Short name T64
Test name
Test status
Simulation time 125679736 ps
CPU time 3.88 seconds
Started Jun 24 05:18:41 PM PDT 24
Finished Jun 24 05:18:46 PM PDT 24
Peak memory 198072 kb
Host smart-573eddc2-c473-4c04-9ef9-c66466b23654
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670228664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3670228664
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.823160571
Short name T433
Test name
Test status
Simulation time 41756986 ps
CPU time 1.11 seconds
Started Jun 24 05:18:43 PM PDT 24
Finished Jun 24 05:18:45 PM PDT 24
Peak memory 196764 kb
Host smart-22389c99-1186-4a2d-a236-82f543ff800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823160571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.823160571
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1340186780
Short name T438
Test name
Test status
Simulation time 120211082 ps
CPU time 0.7 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:18:48 PM PDT 24
Peak memory 195696 kb
Host smart-4c3a65c5-d895-4086-9649-05354953b9b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340186780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1340186780
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3006578671
Short name T265
Test name
Test status
Simulation time 1187939790 ps
CPU time 2.92 seconds
Started Jun 24 05:18:40 PM PDT 24
Finished Jun 24 05:18:44 PM PDT 24
Peak memory 198232 kb
Host smart-6ed66192-8027-46dc-8485-376b4f6de977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006578671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3006578671
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3387241923
Short name T249
Test name
Test status
Simulation time 977034602 ps
CPU time 0.95 seconds
Started Jun 24 05:18:43 PM PDT 24
Finished Jun 24 05:18:45 PM PDT 24
Peak memory 196408 kb
Host smart-109d142e-7b34-46de-ad01-ca83a45a6f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387241923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3387241923
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3916774878
Short name T367
Test name
Test status
Simulation time 631527491 ps
CPU time 1.16 seconds
Started Jun 24 05:18:42 PM PDT 24
Finished Jun 24 05:18:45 PM PDT 24
Peak memory 195720 kb
Host smart-c9875b81-a0a6-421d-8243-ab417c927ab9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916774878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3916774878
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3234874818
Short name T318
Test name
Test status
Simulation time 4695117201 ps
CPU time 71.04 seconds
Started Jun 24 05:18:45 PM PDT 24
Finished Jun 24 05:19:57 PM PDT 24
Peak memory 198092 kb
Host smart-e17c8d85-a3bd-4710-b464-7a0d826a85be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234874818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3234874818
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3926361580
Short name T40
Test name
Test status
Simulation time 15774321 ps
CPU time 0.58 seconds
Started Jun 24 05:18:48 PM PDT 24
Finished Jun 24 05:18:50 PM PDT 24
Peak memory 194580 kb
Host smart-ac59c5d6-f858-47de-a6fe-569655b3f107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926361580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3926361580
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3692386249
Short name T412
Test name
Test status
Simulation time 106900552 ps
CPU time 0.73 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:18:48 PM PDT 24
Peak memory 195232 kb
Host smart-447f0ad0-1eb7-4a27-be32-ec54fb4db385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692386249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3692386249
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.4046794004
Short name T282
Test name
Test status
Simulation time 802188312 ps
CPU time 10.44 seconds
Started Jun 24 05:18:54 PM PDT 24
Finished Jun 24 05:19:05 PM PDT 24
Peak memory 196696 kb
Host smart-60e73d83-a37b-40c4-924b-384af6333138
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046794004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.4046794004
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1543762893
Short name T594
Test name
Test status
Simulation time 67474341 ps
CPU time 0.79 seconds
Started Jun 24 05:18:49 PM PDT 24
Finished Jun 24 05:18:50 PM PDT 24
Peak memory 196588 kb
Host smart-b2303750-32ba-4e46-9a89-56e443b01494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543762893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1543762893
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.302245481
Short name T107
Test name
Test status
Simulation time 158476611 ps
CPU time 1.32 seconds
Started Jun 24 05:18:42 PM PDT 24
Finished Jun 24 05:18:45 PM PDT 24
Peak memory 196692 kb
Host smart-31ef0d00-25cf-4e5c-8df1-dada223af019
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302245481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.302245481
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4192047210
Short name T158
Test name
Test status
Simulation time 267791143 ps
CPU time 2.79 seconds
Started Jun 24 05:18:43 PM PDT 24
Finished Jun 24 05:18:47 PM PDT 24
Peak memory 198028 kb
Host smart-50c3a9bd-0b7e-4f19-b299-dbf690d4df60
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192047210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4192047210
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1885254937
Short name T120
Test name
Test status
Simulation time 95460681 ps
CPU time 3.01 seconds
Started Jun 24 05:18:45 PM PDT 24
Finished Jun 24 05:18:49 PM PDT 24
Peak memory 197116 kb
Host smart-b0acfa84-3ac1-4017-84c8-4c5818a499ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885254937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1885254937
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1788237475
Short name T350
Test name
Test status
Simulation time 38161634 ps
CPU time 0.89 seconds
Started Jun 24 05:18:42 PM PDT 24
Finished Jun 24 05:18:44 PM PDT 24
Peak memory 197276 kb
Host smart-194d3bb0-b8a6-4902-9721-1fb8a0cecc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788237475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1788237475
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3011449750
Short name T628
Test name
Test status
Simulation time 50342171 ps
CPU time 1.11 seconds
Started Jun 24 05:18:40 PM PDT 24
Finished Jun 24 05:18:42 PM PDT 24
Peak memory 196020 kb
Host smart-0e97a949-95b6-4b87-97e6-74d65fa2f3ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011449750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3011449750
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2132377512
Short name T351
Test name
Test status
Simulation time 100606965 ps
CPU time 4.61 seconds
Started Jun 24 05:18:48 PM PDT 24
Finished Jun 24 05:18:54 PM PDT 24
Peak memory 197924 kb
Host smart-74a33cea-138b-442c-af38-0b0f79058a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132377512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2132377512
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.871172820
Short name T335
Test name
Test status
Simulation time 67002937 ps
CPU time 1.17 seconds
Started Jun 24 05:18:47 PM PDT 24
Finished Jun 24 05:18:49 PM PDT 24
Peak memory 195676 kb
Host smart-dbafcaeb-77dc-4ab6-acce-b80abf5901d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871172820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.871172820
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3571226678
Short name T434
Test name
Test status
Simulation time 92171612 ps
CPU time 1.41 seconds
Started Jun 24 05:18:43 PM PDT 24
Finished Jun 24 05:18:45 PM PDT 24
Peak memory 196388 kb
Host smart-5bf494da-1b20-4627-8b52-53d2f4a0fe6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571226678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3571226678
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1261454444
Short name T408
Test name
Test status
Simulation time 3814542018 ps
CPU time 30.01 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:19:22 PM PDT 24
Peak memory 198116 kb
Host smart-2407820f-1d1c-4f20-8c23-f4abfde8290d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261454444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1261454444
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1100999115
Short name T519
Test name
Test status
Simulation time 292502198 ps
CPU time 1.01 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 195832 kb
Host smart-d0ac6678-e22b-4156-8154-4a4005464b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100999115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1100999115
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1683938420
Short name T717
Test name
Test status
Simulation time 346931798 ps
CPU time 4.53 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:56 PM PDT 24
Peak memory 196288 kb
Host smart-c762fafc-616c-4441-8100-c0664789edd6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683938420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1683938420
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1325783757
Short name T62
Test name
Test status
Simulation time 27670916 ps
CPU time 0.68 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 194652 kb
Host smart-9771bc38-a922-4e1b-b3a9-068d0a649a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325783757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1325783757
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3502128597
Short name T174
Test name
Test status
Simulation time 16849273 ps
CPU time 0.75 seconds
Started Jun 24 05:18:52 PM PDT 24
Finished Jun 24 05:18:54 PM PDT 24
Peak memory 194220 kb
Host smart-a8a9caf0-8b6e-4db0-947e-97939a00701e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502128597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3502128597
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2738766640
Short name T197
Test name
Test status
Simulation time 83492820 ps
CPU time 1.18 seconds
Started Jun 24 05:18:51 PM PDT 24
Finished Jun 24 05:18:53 PM PDT 24
Peak memory 195272 kb
Host smart-6e7212a1-0903-4bc5-9c14-e2107ceafb95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738766640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2738766640
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.976067612
Short name T206
Test name
Test status
Simulation time 18064703 ps
CPU time 0.7 seconds
Started Jun 24 05:18:49 PM PDT 24
Finished Jun 24 05:18:50 PM PDT 24
Peak memory 195356 kb
Host smart-ad84abe2-86ac-4c44-a890-f6c2d1d334e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976067612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.976067612
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1539672931
Short name T68
Test name
Test status
Simulation time 47435249 ps
CPU time 0.78 seconds
Started Jun 24 05:18:54 PM PDT 24
Finished Jun 24 05:18:56 PM PDT 24
Peak memory 196072 kb
Host smart-75185d42-ca99-4bf9-b561-30229b1e9ef8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539672931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1539672931
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.283388304
Short name T354
Test name
Test status
Simulation time 117608109 ps
CPU time 5.03 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:57 PM PDT 24
Peak memory 197840 kb
Host smart-b65d7e3a-e383-487c-a315-ef3bb0aeaf3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283388304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.283388304
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4167053784
Short name T427
Test name
Test status
Simulation time 48841830 ps
CPU time 0.85 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 195112 kb
Host smart-3862f70f-dad5-4771-a195-27ca2e455529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167053784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4167053784
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2934151111
Short name T70
Test name
Test status
Simulation time 194919304 ps
CPU time 1.08 seconds
Started Jun 24 05:18:51 PM PDT 24
Finished Jun 24 05:18:54 PM PDT 24
Peak memory 196532 kb
Host smart-beb858a6-fe38-4b3a-84c5-607fcad05460
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934151111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2934151111
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.704024770
Short name T713
Test name
Test status
Simulation time 1858989760 ps
CPU time 29.15 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:19:21 PM PDT 24
Peak memory 198024 kb
Host smart-06a15b1b-08a3-4462-96d4-83329dd67b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704024770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.704024770
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.145544671
Short name T248
Test name
Test status
Simulation time 11877057 ps
CPU time 0.55 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 193760 kb
Host smart-3544d8fe-ec8b-4419-a242-623b12d96b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145544671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.145544671
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2145795139
Short name T362
Test name
Test status
Simulation time 72393568 ps
CPU time 0.73 seconds
Started Jun 24 05:18:51 PM PDT 24
Finished Jun 24 05:18:53 PM PDT 24
Peak memory 195104 kb
Host smart-3c96b520-a79b-4a33-8d2b-6ba222c54bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145795139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2145795139
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.884165256
Short name T253
Test name
Test status
Simulation time 937091328 ps
CPU time 26.51 seconds
Started Jun 24 05:18:49 PM PDT 24
Finished Jun 24 05:19:16 PM PDT 24
Peak memory 196588 kb
Host smart-ae057a08-4fab-4fcf-80bb-b4b342440eae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884165256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.884165256
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.4138146886
Short name T609
Test name
Test status
Simulation time 70646081 ps
CPU time 0.78 seconds
Started Jun 24 05:18:52 PM PDT 24
Finished Jun 24 05:18:54 PM PDT 24
Peak memory 196428 kb
Host smart-e3dffd9a-ddcf-4331-acc8-21744b35c5d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138146886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.4138146886
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2588300766
Short name T607
Test name
Test status
Simulation time 24407088 ps
CPU time 0.76 seconds
Started Jun 24 05:18:48 PM PDT 24
Finished Jun 24 05:18:50 PM PDT 24
Peak memory 195356 kb
Host smart-60b66e65-9245-4d93-8a71-40c48cc70f68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588300766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2588300766
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2390977825
Short name T317
Test name
Test status
Simulation time 163739720 ps
CPU time 1.83 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:54 PM PDT 24
Peak memory 197656 kb
Host smart-85a4bed6-f9a2-4854-a2f6-259c7fa4fd96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390977825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2390977825
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1313010934
Short name T18
Test name
Test status
Simulation time 76729725 ps
CPU time 1.11 seconds
Started Jun 24 05:18:49 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 195972 kb
Host smart-83560382-c2be-4054-9f20-177db615140d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313010934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1313010934
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2264558193
Short name T417
Test name
Test status
Simulation time 41548443 ps
CPU time 0.99 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 196416 kb
Host smart-680fa525-d68c-4f1c-8bd9-df8b55392d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264558193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2264558193
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2961887137
Short name T330
Test name
Test status
Simulation time 23700242 ps
CPU time 1 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:52 PM PDT 24
Peak memory 195784 kb
Host smart-cf5748a4-8800-4ce0-98bf-aacee0529d2e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961887137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2961887137
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4001069441
Short name T711
Test name
Test status
Simulation time 531261480 ps
CPU time 1.92 seconds
Started Jun 24 05:18:53 PM PDT 24
Finished Jun 24 05:18:56 PM PDT 24
Peak memory 197836 kb
Host smart-9e0dab1b-47e0-4ccc-8357-61c7579ca2a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001069441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4001069441
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1699611819
Short name T543
Test name
Test status
Simulation time 213222757 ps
CPU time 1.16 seconds
Started Jun 24 05:18:52 PM PDT 24
Finished Jun 24 05:18:55 PM PDT 24
Peak memory 196160 kb
Host smart-282be766-a656-4b41-b403-34b367dd22ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699611819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1699611819
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2969345765
Short name T225
Test name
Test status
Simulation time 337572581 ps
CPU time 1.3 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:53 PM PDT 24
Peak memory 196420 kb
Host smart-20da31bb-315e-477c-b8b6-2ca5641c3952
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969345765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2969345765
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.858410795
Short name T8
Test name
Test status
Simulation time 18526523500 ps
CPU time 108.47 seconds
Started Jun 24 05:18:48 PM PDT 24
Finished Jun 24 05:20:37 PM PDT 24
Peak memory 197984 kb
Host smart-b51b0f6e-1ed2-4b3e-9f1b-77acc099143e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858410795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.858410795
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1374844570
Short name T56
Test name
Test status
Simulation time 80425201928 ps
CPU time 456.64 seconds
Started Jun 24 05:18:52 PM PDT 24
Finished Jun 24 05:26:30 PM PDT 24
Peak memory 198176 kb
Host smart-2a8d2fb8-4def-41df-96d6-fdf9a952b555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1374844570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1374844570
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2828317595
Short name T436
Test name
Test status
Simulation time 24906379 ps
CPU time 0.59 seconds
Started Jun 24 05:17:38 PM PDT 24
Finished Jun 24 05:17:40 PM PDT 24
Peak memory 193760 kb
Host smart-0a5b4141-50af-4b5d-8a0f-d89c3f9f27ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828317595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2828317595
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.397016519
Short name T583
Test name
Test status
Simulation time 348164684 ps
CPU time 0.83 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 196036 kb
Host smart-d0517b50-723a-4d77-9a70-193f123fdcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397016519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.397016519
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.921914634
Short name T311
Test name
Test status
Simulation time 534473814 ps
CPU time 27.51 seconds
Started Jun 24 05:17:35 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 196996 kb
Host smart-4a470a63-9a51-42d8-9715-983a685c2096
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921914634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.921914634
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2129102445
Short name T469
Test name
Test status
Simulation time 128717547 ps
CPU time 0.86 seconds
Started Jun 24 05:17:37 PM PDT 24
Finished Jun 24 05:17:40 PM PDT 24
Peak memory 195736 kb
Host smart-ec351ae4-327e-4881-92f1-2ec1fcaeecfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129102445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2129102445
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1739960152
Short name T515
Test name
Test status
Simulation time 154946042 ps
CPU time 1.37 seconds
Started Jun 24 05:17:40 PM PDT 24
Finished Jun 24 05:17:43 PM PDT 24
Peak memory 197172 kb
Host smart-c3258c67-3d66-4bc5-a152-bee156b1b428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739960152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1739960152
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2675495652
Short name T677
Test name
Test status
Simulation time 172455844 ps
CPU time 1.73 seconds
Started Jun 24 05:17:40 PM PDT 24
Finished Jun 24 05:17:43 PM PDT 24
Peak memory 198016 kb
Host smart-f7f579ac-1d27-4c1f-87e6-9ae10d6125b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675495652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2675495652
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2700086594
Short name T170
Test name
Test status
Simulation time 71674725 ps
CPU time 1.68 seconds
Started Jun 24 05:17:34 PM PDT 24
Finished Jun 24 05:17:36 PM PDT 24
Peak memory 195924 kb
Host smart-c6b15eb5-9682-48ab-affd-64abd739f936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700086594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2700086594
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.739857931
Short name T673
Test name
Test status
Simulation time 145403116 ps
CPU time 0.67 seconds
Started Jun 24 05:17:35 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 194284 kb
Host smart-92969334-f504-489d-91c9-aaef0656675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739857931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.739857931
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.797372523
Short name T623
Test name
Test status
Simulation time 45230376 ps
CPU time 1.16 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:39 PM PDT 24
Peak memory 196660 kb
Host smart-87ed7202-7e8d-4808-a75f-84d92502fa08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797372523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.797372523
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2698620821
Short name T409
Test name
Test status
Simulation time 81276819 ps
CPU time 1.64 seconds
Started Jun 24 05:17:37 PM PDT 24
Finished Jun 24 05:17:41 PM PDT 24
Peak memory 197712 kb
Host smart-9d585a90-0416-442e-9ae8-0a8b6d22cfc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698620821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2698620821
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1000581601
Short name T38
Test name
Test status
Simulation time 96404399 ps
CPU time 0.95 seconds
Started Jun 24 05:17:35 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 214680 kb
Host smart-487a7d22-46f6-4c1a-aff9-75baac0a39d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000581601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1000581601
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3237804069
Short name T310
Test name
Test status
Simulation time 149603055 ps
CPU time 0.95 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 195564 kb
Host smart-73d4694f-864a-4b3c-a678-590db4491870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237804069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3237804069
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3631070050
Short name T603
Test name
Test status
Simulation time 44880910 ps
CPU time 0.93 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:39 PM PDT 24
Peak memory 195640 kb
Host smart-36d26b80-83a8-482d-922c-3273058d0528
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631070050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3631070050
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1864725888
Short name T169
Test name
Test status
Simulation time 170070750217 ps
CPU time 151.07 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:20:08 PM PDT 24
Peak memory 198016 kb
Host smart-37733776-3d3c-4034-b79d-acbb9286b6ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864725888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1864725888
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3909258628
Short name T357
Test name
Test status
Simulation time 42394698 ps
CPU time 0.57 seconds
Started Jun 24 05:18:57 PM PDT 24
Finished Jun 24 05:18:58 PM PDT 24
Peak memory 193732 kb
Host smart-2abce5b2-2957-4c25-b1c2-8cd9b8bc6e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909258628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3909258628
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.688979432
Short name T272
Test name
Test status
Simulation time 85133578 ps
CPU time 0.92 seconds
Started Jun 24 05:18:50 PM PDT 24
Finished Jun 24 05:18:53 PM PDT 24
Peak memory 196020 kb
Host smart-06a2474e-13c5-44d5-94c6-c800271b20d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688979432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.688979432
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3598930766
Short name T622
Test name
Test status
Simulation time 484441482 ps
CPU time 13.85 seconds
Started Jun 24 05:19:00 PM PDT 24
Finished Jun 24 05:19:15 PM PDT 24
Peak memory 195504 kb
Host smart-a96754b4-fe41-47e4-a325-c6f3853778c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598930766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3598930766
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1720864872
Short name T475
Test name
Test status
Simulation time 222431168 ps
CPU time 0.99 seconds
Started Jun 24 05:18:59 PM PDT 24
Finished Jun 24 05:19:02 PM PDT 24
Peak memory 196572 kb
Host smart-e50b7076-68fc-4049-8a9d-7c6da8dbe375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720864872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1720864872
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3539667454
Short name T274
Test name
Test status
Simulation time 222060695 ps
CPU time 0.76 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:19:00 PM PDT 24
Peak memory 194300 kb
Host smart-547ac1b1-6311-4c59-bc21-dbcfcfdbb65f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539667454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3539667454
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4231619648
Short name T194
Test name
Test status
Simulation time 117196765 ps
CPU time 2.4 seconds
Started Jun 24 05:18:57 PM PDT 24
Finished Jun 24 05:19:01 PM PDT 24
Peak memory 197988 kb
Host smart-e6eb6c48-139d-4e64-a814-d0f7d47ea7a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231619648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4231619648
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2139849044
Short name T288
Test name
Test status
Simulation time 98349350 ps
CPU time 2.99 seconds
Started Jun 24 05:18:59 PM PDT 24
Finished Jun 24 05:19:03 PM PDT 24
Peak memory 198068 kb
Host smart-07b69930-55b7-425c-b958-700230fa2445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139849044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2139849044
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2656340575
Short name T348
Test name
Test status
Simulation time 28859560 ps
CPU time 0.7 seconds
Started Jun 24 05:18:46 PM PDT 24
Finished Jun 24 05:18:48 PM PDT 24
Peak memory 194992 kb
Host smart-f58c6cd8-f52d-4849-8a89-04fb699f1994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656340575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2656340575
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.501376041
Short name T458
Test name
Test status
Simulation time 58364032 ps
CPU time 0.66 seconds
Started Jun 24 05:18:52 PM PDT 24
Finished Jun 24 05:18:54 PM PDT 24
Peak memory 194196 kb
Host smart-03c0077e-36cf-4346-97d7-a1715acd6584
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501376041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.501376041
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3816199315
Short name T216
Test name
Test status
Simulation time 3842434569 ps
CPU time 5.64 seconds
Started Jun 24 05:19:01 PM PDT 24
Finished Jun 24 05:19:09 PM PDT 24
Peak memory 198012 kb
Host smart-fbb06d50-2d75-4552-bf3e-560d28ba1200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816199315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3816199315
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3492621573
Short name T233
Test name
Test status
Simulation time 167613181 ps
CPU time 1.01 seconds
Started Jun 24 05:18:53 PM PDT 24
Finished Jun 24 05:18:55 PM PDT 24
Peak memory 195400 kb
Host smart-eeb016d6-3dfc-44cd-b276-f71ad0f9c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492621573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3492621573
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3089954041
Short name T144
Test name
Test status
Simulation time 92530465 ps
CPU time 0.86 seconds
Started Jun 24 05:18:49 PM PDT 24
Finished Jun 24 05:18:51 PM PDT 24
Peak memory 196388 kb
Host smart-9f746438-4d87-4f8a-8e8a-80fe78147332
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089954041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3089954041
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1487366139
Short name T612
Test name
Test status
Simulation time 13220803296 ps
CPU time 151.55 seconds
Started Jun 24 05:19:01 PM PDT 24
Finished Jun 24 05:21:34 PM PDT 24
Peak memory 198096 kb
Host smart-23d4c287-f2ca-40ea-804c-8738b4f118c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487366139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1487366139
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.332556814
Short name T472
Test name
Test status
Simulation time 38239849 ps
CPU time 0.58 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:18:59 PM PDT 24
Peak memory 194484 kb
Host smart-f3f1008d-2c29-452f-9917-fd25acb2cbe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332556814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.332556814
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2992943943
Short name T451
Test name
Test status
Simulation time 116706084 ps
CPU time 0.84 seconds
Started Jun 24 05:19:02 PM PDT 24
Finished Jun 24 05:19:05 PM PDT 24
Peak memory 196068 kb
Host smart-74bee279-3b13-4be8-8ed9-898bc91cb28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992943943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2992943943
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3035521293
Short name T145
Test name
Test status
Simulation time 1264193898 ps
CPU time 20.74 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:19:20 PM PDT 24
Peak memory 196964 kb
Host smart-67ab0813-38be-4255-81db-9b2574be847c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035521293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3035521293
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2336009468
Short name T477
Test name
Test status
Simulation time 145728242 ps
CPU time 1.05 seconds
Started Jun 24 05:19:02 PM PDT 24
Finished Jun 24 05:19:04 PM PDT 24
Peak memory 197864 kb
Host smart-a058f37b-ce1c-4e2e-83ad-8baee190c9ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336009468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2336009468
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3181053718
Short name T635
Test name
Test status
Simulation time 45262322 ps
CPU time 0.73 seconds
Started Jun 24 05:18:56 PM PDT 24
Finished Jun 24 05:18:58 PM PDT 24
Peak memory 194620 kb
Host smart-b72f510c-5fcb-4271-8561-79f104e93827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181053718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3181053718
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1138428260
Short name T349
Test name
Test status
Simulation time 296891746 ps
CPU time 3.12 seconds
Started Jun 24 05:18:59 PM PDT 24
Finished Jun 24 05:19:04 PM PDT 24
Peak memory 198012 kb
Host smart-2cb16318-5156-4396-9c2b-df2b51fb1c41
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138428260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1138428260
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.272296938
Short name T299
Test name
Test status
Simulation time 42785792 ps
CPU time 1.53 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:19:00 PM PDT 24
Peak memory 196508 kb
Host smart-964f3348-ce4b-4547-87d7-85f190497333
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272296938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
272296938
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.877829683
Short name T445
Test name
Test status
Simulation time 44530164 ps
CPU time 0.95 seconds
Started Jun 24 05:19:00 PM PDT 24
Finished Jun 24 05:19:03 PM PDT 24
Peak memory 195912 kb
Host smart-bfc1f297-557e-4c43-abe1-129c7a06e3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877829683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.877829683
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3475585911
Short name T716
Test name
Test status
Simulation time 50331773 ps
CPU time 0.81 seconds
Started Jun 24 05:18:59 PM PDT 24
Finished Jun 24 05:19:00 PM PDT 24
Peak memory 195436 kb
Host smart-8b423373-5343-41b7-805c-29a699e268dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475585911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3475585911
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2140804796
Short name T379
Test name
Test status
Simulation time 117729002 ps
CPU time 2.94 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:19:02 PM PDT 24
Peak memory 197988 kb
Host smart-fc794cb7-64c5-4bb6-b26a-039e14cd5d5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140804796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2140804796
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2147132802
Short name T605
Test name
Test status
Simulation time 267530293 ps
CPU time 1.2 seconds
Started Jun 24 05:19:00 PM PDT 24
Finished Jun 24 05:19:03 PM PDT 24
Peak memory 195628 kb
Host smart-6b627834-42b7-434b-b025-9f5f523ab301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147132802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2147132802
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.472016602
Short name T604
Test name
Test status
Simulation time 62305944 ps
CPU time 1.25 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:19:01 PM PDT 24
Peak memory 196348 kb
Host smart-ab5e9589-476b-4ef5-ada3-74b61dfcd17f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472016602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.472016602
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.151817102
Short name T422
Test name
Test status
Simulation time 4026464282 ps
CPU time 112.87 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:20:57 PM PDT 24
Peak memory 197952 kb
Host smart-fe4db9ab-0c86-40f4-a3c9-8f58a5aa61a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151817102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.151817102
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1574023696
Short name T352
Test name
Test status
Simulation time 12346653 ps
CPU time 0.59 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:19:05 PM PDT 24
Peak memory 193652 kb
Host smart-5b798e6c-d6c6-497b-8017-2493410a65dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574023696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1574023696
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.540035139
Short name T304
Test name
Test status
Simulation time 57313317 ps
CPU time 0.65 seconds
Started Jun 24 05:19:00 PM PDT 24
Finished Jun 24 05:19:02 PM PDT 24
Peak memory 194652 kb
Host smart-9b6b198e-2f7c-4ec8-bbe0-040c31d8ac71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540035139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.540035139
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3530989162
Short name T509
Test name
Test status
Simulation time 166779991 ps
CPU time 8.49 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 196604 kb
Host smart-0757a535-c189-4129-899b-c879352bdb05
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530989162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3530989162
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2376799361
Short name T535
Test name
Test status
Simulation time 239405781 ps
CPU time 0.78 seconds
Started Jun 24 05:19:01 PM PDT 24
Finished Jun 24 05:19:04 PM PDT 24
Peak memory 195724 kb
Host smart-6a1b2910-3728-4874-8f4c-41c395c412e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376799361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2376799361
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1443892384
Short name T175
Test name
Test status
Simulation time 67252843 ps
CPU time 1.12 seconds
Started Jun 24 05:18:59 PM PDT 24
Finished Jun 24 05:19:01 PM PDT 24
Peak memory 196480 kb
Host smart-4ce9d6cf-f159-4c15-9b84-d0d6af7950dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443892384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1443892384
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2810826803
Short name T684
Test name
Test status
Simulation time 318219570 ps
CPU time 3.1 seconds
Started Jun 24 05:18:57 PM PDT 24
Finished Jun 24 05:19:01 PM PDT 24
Peak memory 196312 kb
Host smart-a58eef25-d74e-48f4-b321-0595ab9a4d61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810826803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2810826803
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1012925906
Short name T135
Test name
Test status
Simulation time 146373987 ps
CPU time 3.25 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:19:08 PM PDT 24
Peak memory 197196 kb
Host smart-befaa011-fb61-4c9e-b69d-31249953b75b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012925906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1012925906
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3091424693
Short name T685
Test name
Test status
Simulation time 358354287 ps
CPU time 1.02 seconds
Started Jun 24 05:18:59 PM PDT 24
Finished Jun 24 05:19:02 PM PDT 24
Peak memory 195992 kb
Host smart-5c6fe7cc-cf36-4343-a2b5-6099f7b8d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091424693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3091424693
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3000882797
Short name T581
Test name
Test status
Simulation time 195407403 ps
CPU time 0.97 seconds
Started Jun 24 05:19:00 PM PDT 24
Finished Jun 24 05:19:02 PM PDT 24
Peak memory 196016 kb
Host smart-eff8c3d3-3d33-45d9-8ec1-53f13691fff1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000882797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3000882797
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2101776276
Short name T269
Test name
Test status
Simulation time 681802979 ps
CPU time 4.74 seconds
Started Jun 24 05:18:57 PM PDT 24
Finished Jun 24 05:19:03 PM PDT 24
Peak memory 197976 kb
Host smart-62852519-5ae9-4837-bb15-fcf85d19165d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101776276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2101776276
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1447071094
Short name T28
Test name
Test status
Simulation time 112333835 ps
CPU time 1.08 seconds
Started Jun 24 05:19:00 PM PDT 24
Finished Jun 24 05:19:03 PM PDT 24
Peak memory 195760 kb
Host smart-0f85b8e3-e392-4c75-9622-4611e9a3d2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447071094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1447071094
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2745532783
Short name T235
Test name
Test status
Simulation time 20441467 ps
CPU time 0.72 seconds
Started Jun 24 05:19:01 PM PDT 24
Finished Jun 24 05:19:04 PM PDT 24
Peak memory 194752 kb
Host smart-ae3698e3-7b25-40fc-aa58-71a0575a7708
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745532783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2745532783
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2819046369
Short name T424
Test name
Test status
Simulation time 9715596017 ps
CPU time 65.99 seconds
Started Jun 24 05:19:00 PM PDT 24
Finished Jun 24 05:20:08 PM PDT 24
Peak memory 198140 kb
Host smart-327e76bc-3264-49ac-82b4-7ee038797ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819046369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2819046369
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3546503385
Short name T31
Test name
Test status
Simulation time 1290935282298 ps
CPU time 1784.77 seconds
Started Jun 24 05:19:02 PM PDT 24
Finished Jun 24 05:48:48 PM PDT 24
Peak memory 206376 kb
Host smart-6ed820cc-8471-469d-b1d8-db161b265592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3546503385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3546503385
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.981907335
Short name T173
Test name
Test status
Simulation time 12683516 ps
CPU time 0.57 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 194368 kb
Host smart-6b3b3c84-5f07-4368-b7b0-aab46d08c6fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981907335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.981907335
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1875657638
Short name T153
Test name
Test status
Simulation time 38498758 ps
CPU time 0.63 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 193852 kb
Host smart-a285e21a-0be0-48bf-9609-2307580896a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875657638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1875657638
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.145421323
Short name T657
Test name
Test status
Simulation time 651630630 ps
CPU time 10.22 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 196860 kb
Host smart-89d616b3-fdfe-4cbf-983c-109ca6b37284
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145421323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.145421323
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2793019445
Short name T403
Test name
Test status
Simulation time 59925651 ps
CPU time 0.89 seconds
Started Jun 24 05:19:05 PM PDT 24
Finished Jun 24 05:19:08 PM PDT 24
Peak memory 196892 kb
Host smart-a801c41a-8817-48b8-b417-39937c831609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793019445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2793019445
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.978352702
Short name T250
Test name
Test status
Simulation time 20771708 ps
CPU time 0.78 seconds
Started Jun 24 05:19:08 PM PDT 24
Finished Jun 24 05:19:11 PM PDT 24
Peak memory 195208 kb
Host smart-bd26ceae-d930-4fdb-a51a-17fbbf12d51e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978352702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.978352702
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1981824778
Short name T493
Test name
Test status
Simulation time 83569699 ps
CPU time 3.24 seconds
Started Jun 24 05:19:05 PM PDT 24
Finished Jun 24 05:19:11 PM PDT 24
Peak memory 197580 kb
Host smart-89f1c1fe-6ddb-48c1-883a-98bed0d41395
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981824778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1981824778
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.6479865
Short name T606
Test name
Test status
Simulation time 437236536 ps
CPU time 1.19 seconds
Started Jun 24 05:19:07 PM PDT 24
Finished Jun 24 05:19:10 PM PDT 24
Peak memory 195412 kb
Host smart-9c9b329e-2e73-441c-b126-c3fa9e697557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6479865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.6479865
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2566769295
Short name T22
Test name
Test status
Simulation time 69341238 ps
CPU time 0.95 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 195924 kb
Host smart-b8e357dd-eed6-4c35-994c-6d8c0132eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566769295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2566769295
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1691981770
Short name T670
Test name
Test status
Simulation time 29997064 ps
CPU time 0.72 seconds
Started Jun 24 05:19:06 PM PDT 24
Finished Jun 24 05:19:09 PM PDT 24
Peak memory 195968 kb
Host smart-5cfe64d7-19d4-4151-a89e-8ab735f2d7cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691981770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1691981770
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.426370421
Short name T9
Test name
Test status
Simulation time 168008530 ps
CPU time 2.38 seconds
Started Jun 24 05:19:07 PM PDT 24
Finished Jun 24 05:19:12 PM PDT 24
Peak memory 197856 kb
Host smart-549e129a-b87e-4e63-9409-5c1519476c06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426370421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.426370421
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2801004534
Short name T291
Test name
Test status
Simulation time 221290859 ps
CPU time 1.14 seconds
Started Jun 24 05:18:58 PM PDT 24
Finished Jun 24 05:19:00 PM PDT 24
Peak memory 195536 kb
Host smart-6c6105bf-e69d-4ae8-a920-c43b067e1d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801004534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2801004534
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.768091946
Short name T639
Test name
Test status
Simulation time 92891251 ps
CPU time 0.97 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 196484 kb
Host smart-1150f132-b5d2-4ece-b199-882846c1c761
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768091946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.768091946
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2091303035
Short name T337
Test name
Test status
Simulation time 3627510553 ps
CPU time 48.14 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:19:53 PM PDT 24
Peak memory 198088 kb
Host smart-952b56b7-550e-45a6-99a0-887dc1030dc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091303035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2091303035
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1913827344
Short name T324
Test name
Test status
Simulation time 18160451 ps
CPU time 0.58 seconds
Started Jun 24 05:19:06 PM PDT 24
Finished Jun 24 05:19:09 PM PDT 24
Peak memory 193780 kb
Host smart-902579a3-365d-4977-b8c4-5d75a1abe8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913827344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1913827344
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.4123390737
Short name T584
Test name
Test status
Simulation time 125557547 ps
CPU time 0.82 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:06 PM PDT 24
Peak memory 195224 kb
Host smart-a8a74b5a-ade4-4c34-a428-0ff159f92982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123390737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.4123390737
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.145656610
Short name T344
Test name
Test status
Simulation time 2579149820 ps
CPU time 18.05 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 196976 kb
Host smart-0b2ceeef-66cf-434e-95c1-5ec17ff6ca72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145656610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stres
s.145656610
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3645562651
Short name T439
Test name
Test status
Simulation time 85331435 ps
CPU time 0.68 seconds
Started Jun 24 05:19:05 PM PDT 24
Finished Jun 24 05:19:08 PM PDT 24
Peak memory 195228 kb
Host smart-41673bb4-af3d-4903-bdbb-064b8f3a6a40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645562651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3645562651
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3824052609
Short name T715
Test name
Test status
Simulation time 202948756 ps
CPU time 1.12 seconds
Started Jun 24 05:19:08 PM PDT 24
Finished Jun 24 05:19:10 PM PDT 24
Peak memory 195904 kb
Host smart-db3c4774-9bef-429b-83dd-443586c85c66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824052609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3824052609
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3039925989
Short name T706
Test name
Test status
Simulation time 176207057 ps
CPU time 3.41 seconds
Started Jun 24 05:19:06 PM PDT 24
Finished Jun 24 05:19:12 PM PDT 24
Peak memory 198004 kb
Host smart-4f1351fe-c0bc-4917-bee2-ac1b186373f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039925989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3039925989
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.229557294
Short name T513
Test name
Test status
Simulation time 155799613 ps
CPU time 2.39 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 195792 kb
Host smart-f16b8fe7-5a4e-4c84-8ccb-0f6edeac60c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229557294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
229557294
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4180465169
Short name T514
Test name
Test status
Simulation time 65212226 ps
CPU time 1.2 seconds
Started Jun 24 05:19:07 PM PDT 24
Finished Jun 24 05:19:10 PM PDT 24
Peak memory 197116 kb
Host smart-35c85078-aacb-49f1-9c20-865482a891ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180465169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4180465169
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1126879178
Short name T503
Test name
Test status
Simulation time 38687419 ps
CPU time 0.94 seconds
Started Jun 24 05:19:08 PM PDT 24
Finished Jun 24 05:19:10 PM PDT 24
Peak memory 196436 kb
Host smart-87cf6fb8-fa9a-46a9-b71b-9ec300977c1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126879178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1126879178
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1895549125
Short name T289
Test name
Test status
Simulation time 234746113 ps
CPU time 3.31 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:19:09 PM PDT 24
Peak memory 197964 kb
Host smart-33936bac-2c2a-45d1-a342-68abdec2bfed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895549125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1895549125
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2496172223
Short name T129
Test name
Test status
Simulation time 35292044 ps
CPU time 0.85 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 195028 kb
Host smart-537d98a0-b980-47fb-a6ed-2bf8f2d0e54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496172223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2496172223
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3260778180
Short name T655
Test name
Test status
Simulation time 172395236 ps
CPU time 0.94 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 196240 kb
Host smart-7163293d-2630-4b59-9ad6-7a52dc599bc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260778180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3260778180
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3120342803
Short name T634
Test name
Test status
Simulation time 39007738566 ps
CPU time 208.14 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:22:33 PM PDT 24
Peak memory 198100 kb
Host smart-acdee9de-9da9-4a94-9f60-9e6df08da70b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120342803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3120342803
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1010079926
Short name T410
Test name
Test status
Simulation time 74128579 ps
CPU time 0.58 seconds
Started Jun 24 05:19:12 PM PDT 24
Finished Jun 24 05:19:14 PM PDT 24
Peak memory 194464 kb
Host smart-f88339af-58e4-4238-8733-574f56e0f283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010079926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1010079926
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.619897467
Short name T155
Test name
Test status
Simulation time 54728907 ps
CPU time 0.87 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:07 PM PDT 24
Peak memory 195192 kb
Host smart-7ae1c6fc-2c60-4552-aa8b-7d8fc23353be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619897467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.619897467
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.624301806
Short name T399
Test name
Test status
Simulation time 551024870 ps
CPU time 27.78 seconds
Started Jun 24 05:19:11 PM PDT 24
Finished Jun 24 05:19:40 PM PDT 24
Peak memory 195508 kb
Host smart-ffecd692-bed9-4a05-8e8c-8a7a639a6e2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624301806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.624301806
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1416357999
Short name T327
Test name
Test status
Simulation time 161748107 ps
CPU time 1.01 seconds
Started Jun 24 05:19:12 PM PDT 24
Finished Jun 24 05:19:14 PM PDT 24
Peak memory 196856 kb
Host smart-7eb358e4-b28c-4382-8886-1714f5f023fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416357999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1416357999
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.4098945905
Short name T703
Test name
Test status
Simulation time 264538104 ps
CPU time 1.22 seconds
Started Jun 24 05:19:04 PM PDT 24
Finished Jun 24 05:19:08 PM PDT 24
Peak memory 195664 kb
Host smart-e83d0ead-e280-4971-be86-8a28947c1358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098945905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.4098945905
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1934594487
Short name T624
Test name
Test status
Simulation time 328696456 ps
CPU time 3.48 seconds
Started Jun 24 05:19:06 PM PDT 24
Finished Jun 24 05:19:12 PM PDT 24
Peak memory 197900 kb
Host smart-aee33f59-16b4-465f-8ed2-87f961915ccd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934594487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1934594487
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.326708912
Short name T456
Test name
Test status
Simulation time 1380655507 ps
CPU time 1.91 seconds
Started Jun 24 05:19:09 PM PDT 24
Finished Jun 24 05:19:12 PM PDT 24
Peak memory 196500 kb
Host smart-90f12ce1-d71b-456b-a85d-ae4d1efd4825
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326708912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
326708912
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3654603209
Short name T506
Test name
Test status
Simulation time 58800581 ps
CPU time 1.07 seconds
Started Jun 24 05:19:06 PM PDT 24
Finished Jun 24 05:19:10 PM PDT 24
Peak memory 195920 kb
Host smart-0380949a-8772-42fc-aa5c-2708ff89a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654603209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3654603209
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.633750737
Short name T188
Test name
Test status
Simulation time 31037752 ps
CPU time 1.15 seconds
Started Jun 24 05:19:05 PM PDT 24
Finished Jun 24 05:19:08 PM PDT 24
Peak memory 196568 kb
Host smart-344510c0-cf14-4e41-9892-88e09597ef64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633750737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.633750737
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2008174089
Short name T205
Test name
Test status
Simulation time 571301552 ps
CPU time 4.4 seconds
Started Jun 24 05:19:12 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 197828 kb
Host smart-a132ce6d-906c-46ed-9b5d-6f2cce87bb25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008174089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2008174089
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.810787580
Short name T165
Test name
Test status
Simulation time 71204047 ps
CPU time 0.87 seconds
Started Jun 24 05:19:06 PM PDT 24
Finished Jun 24 05:19:10 PM PDT 24
Peak memory 196036 kb
Host smart-2c38e676-ac18-4778-91a8-302241a80a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810787580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.810787580
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3440217425
Short name T398
Test name
Test status
Simulation time 47438670 ps
CPU time 0.96 seconds
Started Jun 24 05:19:03 PM PDT 24
Finished Jun 24 05:19:06 PM PDT 24
Peak memory 196220 kb
Host smart-e663cbfe-088e-4526-ab42-c374d9ffc4bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440217425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3440217425
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3221952901
Short name T371
Test name
Test status
Simulation time 8414695275 ps
CPU time 53.92 seconds
Started Jun 24 05:19:15 PM PDT 24
Finished Jun 24 05:20:10 PM PDT 24
Peak memory 198112 kb
Host smart-e7678777-a22e-4b5d-915b-e122a784fe3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221952901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3221952901
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1494618871
Short name T32
Test name
Test status
Simulation time 46761205690 ps
CPU time 994.05 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:35:49 PM PDT 24
Peak memory 198064 kb
Host smart-9b2c5a9b-7b86-4672-ad0a-0e9802cc5115
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1494618871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1494618871
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1553050391
Short name T453
Test name
Test status
Simulation time 15559524 ps
CPU time 0.6 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:16 PM PDT 24
Peak memory 193856 kb
Host smart-68b485e3-48b5-4e1d-b46a-39395cf3b24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553050391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1553050391
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3150921152
Short name T383
Test name
Test status
Simulation time 82483172 ps
CPU time 0.78 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:15 PM PDT 24
Peak memory 195116 kb
Host smart-cc2216c2-0d3a-4fdc-a1d8-9ac716ce856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150921152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3150921152
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3075637650
Short name T261
Test name
Test status
Simulation time 6831432011 ps
CPU time 22.62 seconds
Started Jun 24 05:19:22 PM PDT 24
Finished Jun 24 05:19:47 PM PDT 24
Peak memory 196920 kb
Host smart-8d764e90-c671-4655-829f-63dcc07fc188
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075637650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3075637650
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.515259218
Short name T257
Test name
Test status
Simulation time 151701372 ps
CPU time 0.78 seconds
Started Jun 24 05:19:23 PM PDT 24
Finished Jun 24 05:19:25 PM PDT 24
Peak memory 196068 kb
Host smart-dcde3056-9eff-4923-a025-b0270d6146a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515259218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.515259218
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1737663112
Short name T481
Test name
Test status
Simulation time 60027862 ps
CPU time 0.98 seconds
Started Jun 24 05:19:12 PM PDT 24
Finished Jun 24 05:19:14 PM PDT 24
Peak memory 195928 kb
Host smart-b3277364-74e0-474d-98b2-810845540299
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737663112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1737663112
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2933296054
Short name T570
Test name
Test status
Simulation time 70287678 ps
CPU time 2.72 seconds
Started Jun 24 05:19:16 PM PDT 24
Finished Jun 24 05:19:20 PM PDT 24
Peak memory 197960 kb
Host smart-ea0cda67-db80-411a-84d0-4c47cb442187
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933296054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2933296054
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1654484307
Short name T449
Test name
Test status
Simulation time 174330440 ps
CPU time 1.44 seconds
Started Jun 24 05:19:16 PM PDT 24
Finished Jun 24 05:19:19 PM PDT 24
Peak memory 196096 kb
Host smart-7dc77426-7544-42f2-89e7-424bbb412a3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654484307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1654484307
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3560894581
Short name T674
Test name
Test status
Simulation time 27415511 ps
CPU time 0.64 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 194176 kb
Host smart-b1631822-2c1d-4fbd-91d9-49b05da3648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560894581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3560894581
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.746138058
Short name T176
Test name
Test status
Simulation time 62496944 ps
CPU time 1.24 seconds
Started Jun 24 05:19:15 PM PDT 24
Finished Jun 24 05:19:18 PM PDT 24
Peak memory 198028 kb
Host smart-6c09854a-8d8b-4837-88ab-1e030bf04828
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746138058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.746138058
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.4291875253
Short name T386
Test name
Test status
Simulation time 203947394 ps
CPU time 2.7 seconds
Started Jun 24 05:19:15 PM PDT 24
Finished Jun 24 05:19:19 PM PDT 24
Peak memory 197904 kb
Host smart-7d514178-2b94-42e3-9afb-699146617e4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291875253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.4291875253
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1392121411
Short name T384
Test name
Test status
Simulation time 283585418 ps
CPU time 0.82 seconds
Started Jun 24 05:19:15 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 195156 kb
Host smart-b6dbaa96-db7f-4f67-ac50-ca10352341c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392121411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1392121411
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2190691514
Short name T631
Test name
Test status
Simulation time 441951191 ps
CPU time 1.43 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 196764 kb
Host smart-58e8a187-6ef4-4cad-a95a-764cd103172f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190691514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2190691514
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.65927242
Short name T309
Test name
Test status
Simulation time 31485910265 ps
CPU time 88.59 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:20:52 PM PDT 24
Peak memory 198376 kb
Host smart-16e32d7d-3068-4446-807d-a800694a43d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65927242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gp
io_stress_all.65927242
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3502005635
Short name T502
Test name
Test status
Simulation time 16483098156 ps
CPU time 242.68 seconds
Started Jun 24 05:19:22 PM PDT 24
Finished Jun 24 05:23:27 PM PDT 24
Peak memory 198408 kb
Host smart-592c9891-55f9-46b0-bb16-a3164ff3a6ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3502005635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3502005635
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1158150779
Short name T582
Test name
Test status
Simulation time 16903073 ps
CPU time 0.62 seconds
Started Jun 24 05:19:13 PM PDT 24
Finished Jun 24 05:19:15 PM PDT 24
Peak memory 193788 kb
Host smart-085e6c87-a795-4e25-a2ec-97c44a001021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158150779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1158150779
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2199149772
Short name T452
Test name
Test status
Simulation time 157356947 ps
CPU time 0.88 seconds
Started Jun 24 05:19:13 PM PDT 24
Finished Jun 24 05:19:14 PM PDT 24
Peak memory 195404 kb
Host smart-41219c97-1162-4f9d-8a65-a28539b22653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199149772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2199149772
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.4168378339
Short name T696
Test name
Test status
Simulation time 1553431434 ps
CPU time 14.21 seconds
Started Jun 24 05:19:13 PM PDT 24
Finished Jun 24 05:19:28 PM PDT 24
Peak memory 197868 kb
Host smart-f2163ec5-92c1-4589-ad7e-020a7d49178f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168378339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.4168378339
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.434348172
Short name T325
Test name
Test status
Simulation time 1206014316 ps
CPU time 0.91 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 195772 kb
Host smart-c09ea808-9bc0-4ed5-9e56-b8ddd578bff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434348172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.434348172
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.225152707
Short name T264
Test name
Test status
Simulation time 22689490 ps
CPU time 0.75 seconds
Started Jun 24 05:19:15 PM PDT 24
Finished Jun 24 05:19:18 PM PDT 24
Peak memory 195168 kb
Host smart-3352a6b0-9ce9-4e52-bf52-358c735796b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225152707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.225152707
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.700229298
Short name T105
Test name
Test status
Simulation time 44138364 ps
CPU time 1.1 seconds
Started Jun 24 05:19:17 PM PDT 24
Finished Jun 24 05:19:19 PM PDT 24
Peak memory 195916 kb
Host smart-cf5a1753-4371-4e6c-82a3-0023d23ac746
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700229298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.700229298
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1050047221
Short name T231
Test name
Test status
Simulation time 72153242 ps
CPU time 2.21 seconds
Started Jun 24 05:19:22 PM PDT 24
Finished Jun 24 05:19:26 PM PDT 24
Peak memory 198320 kb
Host smart-db5c632b-e8eb-4c4c-8f5a-da46152a1eec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050047221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1050047221
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.848374173
Short name T435
Test name
Test status
Simulation time 200513618 ps
CPU time 1.12 seconds
Started Jun 24 05:19:11 PM PDT 24
Finished Jun 24 05:19:13 PM PDT 24
Peak memory 196656 kb
Host smart-690c3fc2-b775-4ed1-92ce-88af45a4acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848374173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.848374173
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2428362216
Short name T618
Test name
Test status
Simulation time 31038683 ps
CPU time 0.77 seconds
Started Jun 24 05:19:15 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 194912 kb
Host smart-dd2701b0-2d90-4b3f-828f-98b5afbea093
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428362216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2428362216
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.667329680
Short name T626
Test name
Test status
Simulation time 239218826 ps
CPU time 3.87 seconds
Started Jun 24 05:19:12 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 197900 kb
Host smart-42d25ba2-704d-46bc-98d5-63170e91fab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667329680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.667329680
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3991808390
Short name T220
Test name
Test status
Simulation time 36296991 ps
CPU time 0.94 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 196064 kb
Host smart-59e7feb7-0108-4708-89a4-aa22c7349ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991808390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3991808390
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1632951243
Short name T178
Test name
Test status
Simulation time 73854079 ps
CPU time 1.41 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 196756 kb
Host smart-4214b997-15ae-4bf0-a00c-12393cab50b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632951243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1632951243
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.503176515
Short name T470
Test name
Test status
Simulation time 168840134854 ps
CPU time 143.64 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:21:40 PM PDT 24
Peak memory 198060 kb
Host smart-cc1ddfa1-c1ed-4858-83dc-d6be920074fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503176515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.503176515
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2729812546
Short name T251
Test name
Test status
Simulation time 22402633 ps
CPU time 0.62 seconds
Started Jun 24 05:19:22 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 193840 kb
Host smart-19367ad4-82b1-40bb-9b89-914200245515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729812546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2729812546
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2405292400
Short name T542
Test name
Test status
Simulation time 43751189 ps
CPU time 0.78 seconds
Started Jun 24 05:19:22 PM PDT 24
Finished Jun 24 05:19:25 PM PDT 24
Peak memory 196276 kb
Host smart-7b28b1de-b088-414f-9501-806fce220878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405292400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2405292400
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2323709221
Short name T15
Test name
Test status
Simulation time 144708226 ps
CPU time 3.98 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:26 PM PDT 24
Peak memory 195912 kb
Host smart-77cc0067-87c9-4597-9ebf-e7be86173d17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323709221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2323709221
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2155600148
Short name T406
Test name
Test status
Simulation time 20189794 ps
CPU time 0.64 seconds
Started Jun 24 05:19:19 PM PDT 24
Finished Jun 24 05:19:20 PM PDT 24
Peak memory 194944 kb
Host smart-0efd791f-b698-4cdf-a30f-14f8e0cfbcac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155600148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2155600148
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.4162421561
Short name T420
Test name
Test status
Simulation time 76384726 ps
CPU time 0.75 seconds
Started Jun 24 05:19:12 PM PDT 24
Finished Jun 24 05:19:14 PM PDT 24
Peak memory 195980 kb
Host smart-e106cfa3-5796-4b9a-a086-1787e90bbc07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162421561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.4162421561
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1248418835
Short name T171
Test name
Test status
Simulation time 148614420 ps
CPU time 3.31 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 198108 kb
Host smart-d61c0d82-d377-4b43-9bf8-07e7a8dfd702
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248418835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1248418835
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.15054770
Short name T333
Test name
Test status
Simulation time 728570499 ps
CPU time 2.84 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:26 PM PDT 24
Peak memory 197188 kb
Host smart-aaef3072-f3d3-4e21-b5c5-f8f3bdfeed44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15054770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.15054770
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.952800271
Short name T653
Test name
Test status
Simulation time 44252148 ps
CPU time 1.05 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 195896 kb
Host smart-a7dc56db-e523-4440-b3cc-d1a4a7286c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952800271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.952800271
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3270035137
Short name T676
Test name
Test status
Simulation time 56424142 ps
CPU time 1.31 seconds
Started Jun 24 05:19:11 PM PDT 24
Finished Jun 24 05:19:13 PM PDT 24
Peak memory 195712 kb
Host smart-98360b6f-5168-4391-904f-bdbd08e9069a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270035137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3270035137
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2122952984
Short name T346
Test name
Test status
Simulation time 199010798 ps
CPU time 2.34 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:23 PM PDT 24
Peak memory 197884 kb
Host smart-a2cbb0c1-c674-40d3-9009-e9ce038c9d41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122952984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2122952984
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1543436183
Short name T267
Test name
Test status
Simulation time 87061191 ps
CPU time 1.45 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:17 PM PDT 24
Peak memory 196684 kb
Host smart-c7efa370-2c30-4a55-9e4e-a4ec8524fb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543436183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1543436183
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.621102601
Short name T566
Test name
Test status
Simulation time 137944153 ps
CPU time 1.14 seconds
Started Jun 24 05:19:14 PM PDT 24
Finished Jun 24 05:19:16 PM PDT 24
Peak memory 196204 kb
Host smart-f6b85a54-c91f-4f03-903a-23d61c7f2ad3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621102601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.621102601
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1566049120
Short name T487
Test name
Test status
Simulation time 54876966148 ps
CPU time 152.2 seconds
Started Jun 24 05:19:17 PM PDT 24
Finished Jun 24 05:21:50 PM PDT 24
Peak memory 198056 kb
Host smart-fc2f3b9f-aed8-4818-850b-5504c7a61718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566049120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1566049120
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1993460805
Short name T426
Test name
Test status
Simulation time 43369664 ps
CPU time 0.63 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:21 PM PDT 24
Peak memory 193960 kb
Host smart-3098c039-6c7f-4233-925a-c23cf7b370d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993460805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1993460805
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.578169623
Short name T139
Test name
Test status
Simulation time 140501069 ps
CPU time 0.95 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 196456 kb
Host smart-f2614078-6394-47e0-9f6c-e027bb5e55b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578169623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.578169623
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.2562781241
Short name T258
Test name
Test status
Simulation time 574356128 ps
CPU time 10.9 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:34 PM PDT 24
Peak memory 197976 kb
Host smart-bc78dc17-5de8-425b-aa97-0fbfbbab51c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562781241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.2562781241
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1801249679
Short name T244
Test name
Test status
Simulation time 97066022 ps
CPU time 1.02 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 196372 kb
Host smart-e58201a8-2c1d-44ad-b00e-24ca38f7d1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801249679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1801249679
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3444916897
Short name T508
Test name
Test status
Simulation time 38745008 ps
CPU time 0.84 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:23 PM PDT 24
Peak memory 195532 kb
Host smart-05dd6aa2-c544-40cd-8353-acf2c4eece09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444916897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3444916897
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2189876772
Short name T471
Test name
Test status
Simulation time 165732756 ps
CPU time 3.45 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:27 PM PDT 24
Peak memory 197900 kb
Host smart-3f96ae70-c188-426f-8794-aacb78b52788
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189876772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2189876772
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3438258970
Short name T252
Test name
Test status
Simulation time 207630525 ps
CPU time 0.96 seconds
Started Jun 24 05:19:17 PM PDT 24
Finished Jun 24 05:19:19 PM PDT 24
Peak memory 196068 kb
Host smart-ac4e1638-1b63-4662-82a5-82bf791bc272
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438258970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3438258970
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1316687135
Short name T292
Test name
Test status
Simulation time 81219379 ps
CPU time 0.94 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 195724 kb
Host smart-ffb48638-1519-4cb2-9786-109d0d36fdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316687135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1316687135
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.4003714673
Short name T579
Test name
Test status
Simulation time 50669456 ps
CPU time 1.01 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:22 PM PDT 24
Peak memory 195776 kb
Host smart-b340b677-b7af-46db-af2d-3a058bb90fef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003714673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.4003714673
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1810058268
Short name T679
Test name
Test status
Simulation time 112114219 ps
CPU time 4.91 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:28 PM PDT 24
Peak memory 197884 kb
Host smart-b741ade3-24cb-4e43-a2d1-651ec9cc6257
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810058268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1810058268
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1793422382
Short name T213
Test name
Test status
Simulation time 34136348 ps
CPU time 0.8 seconds
Started Jun 24 05:19:19 PM PDT 24
Finished Jun 24 05:19:20 PM PDT 24
Peak memory 194060 kb
Host smart-0e08dea9-21ac-4f3a-90f0-4d8d9807d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793422382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1793422382
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2915807380
Short name T51
Test name
Test status
Simulation time 41835408 ps
CPU time 1.13 seconds
Started Jun 24 05:19:19 PM PDT 24
Finished Jun 24 05:19:21 PM PDT 24
Peak memory 195492 kb
Host smart-39b05d13-dee1-49ff-be6d-f7c8498095e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915807380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2915807380
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3634025029
Short name T443
Test name
Test status
Simulation time 4334648682 ps
CPU time 61.57 seconds
Started Jun 24 05:19:19 PM PDT 24
Finished Jun 24 05:20:22 PM PDT 24
Peak memory 191928 kb
Host smart-94dfb03f-c0a6-4e68-b9ac-6b9512029a71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634025029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3634025029
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2311759974
Short name T300
Test name
Test status
Simulation time 21857991 ps
CPU time 0.59 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 194680 kb
Host smart-27a2d315-98cf-4692-9f3b-ab63023585c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311759974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2311759974
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1429892144
Short name T692
Test name
Test status
Simulation time 16548196 ps
CPU time 0.71 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:39 PM PDT 24
Peak memory 193952 kb
Host smart-a392dc9e-398f-450b-b6eb-6a8b3fcbab6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429892144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1429892144
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1681430924
Short name T544
Test name
Test status
Simulation time 817594089 ps
CPU time 14.86 seconds
Started Jun 24 05:17:37 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 195468 kb
Host smart-b2a19cd4-dbf7-43b1-b91f-67bb3c476306
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681430924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1681430924
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3195867029
Short name T363
Test name
Test status
Simulation time 80433325 ps
CPU time 1.03 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:39 PM PDT 24
Peak memory 197624 kb
Host smart-70e74419-aeb4-4da5-ac25-4f1abcf867d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195867029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3195867029
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1394872630
Short name T221
Test name
Test status
Simulation time 278023986 ps
CPU time 0.9 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 196580 kb
Host smart-91a056c5-cf34-4d2a-bea1-9516e64a7138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394872630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1394872630
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2185365347
Short name T308
Test name
Test status
Simulation time 93608348 ps
CPU time 2.17 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:40 PM PDT 24
Peak memory 196484 kb
Host smart-5fdbae66-bf85-41a6-ba83-a638c14b1e1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185365347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2185365347
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.274531099
Short name T608
Test name
Test status
Simulation time 161718018 ps
CPU time 1.25 seconds
Started Jun 24 05:17:34 PM PDT 24
Finished Jun 24 05:17:36 PM PDT 24
Peak memory 196740 kb
Host smart-f24cd436-eaab-4446-9f44-b15766fdd3ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274531099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.274531099
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1600464163
Short name T532
Test name
Test status
Simulation time 181721639 ps
CPU time 0.8 seconds
Started Jun 24 05:17:34 PM PDT 24
Finished Jun 24 05:17:35 PM PDT 24
Peak memory 196160 kb
Host smart-1dac8a4b-82fb-4e1c-ad88-94b8e21575c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600464163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1600464163
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.337472818
Short name T156
Test name
Test status
Simulation time 368423482 ps
CPU time 1.27 seconds
Started Jun 24 05:17:37 PM PDT 24
Finished Jun 24 05:17:41 PM PDT 24
Peak memory 197032 kb
Host smart-12d49630-98b4-4cc1-bb95-84a8fd2195cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337472818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.337472818
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1039744825
Short name T697
Test name
Test status
Simulation time 213927681 ps
CPU time 1.3 seconds
Started Jun 24 05:17:34 PM PDT 24
Finished Jun 24 05:17:36 PM PDT 24
Peak memory 197916 kb
Host smart-d3c815a3-dd3e-43b8-9785-12fc9f22e52d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039744825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1039744825
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.360408050
Short name T39
Test name
Test status
Simulation time 326113263 ps
CPU time 0.95 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:39 PM PDT 24
Peak memory 214740 kb
Host smart-0f8b50be-fae0-48b7-aae6-16a6be184a77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360408050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.360408050
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1476890037
Short name T637
Test name
Test status
Simulation time 48155195 ps
CPU time 1.06 seconds
Started Jun 24 05:17:41 PM PDT 24
Finished Jun 24 05:17:43 PM PDT 24
Peak memory 195408 kb
Host smart-091d42a5-37ab-45e0-97f7-c3d8a84a9b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476890037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1476890037
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3843122040
Short name T343
Test name
Test status
Simulation time 153579737 ps
CPU time 0.89 seconds
Started Jun 24 05:17:38 PM PDT 24
Finished Jun 24 05:17:41 PM PDT 24
Peak memory 196364 kb
Host smart-a9b17e66-2f4f-4c1e-a7b6-471186001553
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843122040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3843122040
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.813659035
Short name T242
Test name
Test status
Simulation time 11527365989 ps
CPU time 140.53 seconds
Started Jun 24 05:17:35 PM PDT 24
Finished Jun 24 05:19:57 PM PDT 24
Peak memory 198056 kb
Host smart-6dd93960-6763-4019-9dcf-f4f77618aabe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813659035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.813659035
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1900188251
Short name T227
Test name
Test status
Simulation time 12966118 ps
CPU time 0.63 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:22 PM PDT 24
Peak memory 192648 kb
Host smart-1fd6d57d-b79a-4fd5-80fe-bd8cb66f02cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900188251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1900188251
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3784212351
Short name T413
Test name
Test status
Simulation time 110226684 ps
CPU time 0.89 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 197116 kb
Host smart-fc1bae63-30b0-465c-acb9-4ce5448774b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784212351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3784212351
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1667365992
Short name T204
Test name
Test status
Simulation time 697035727 ps
CPU time 24.75 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:45 PM PDT 24
Peak memory 195412 kb
Host smart-503b3535-3a8b-4400-aba7-c805516eae2d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667365992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1667365992
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2006101324
Short name T656
Test name
Test status
Simulation time 34115658 ps
CPU time 0.7 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:23 PM PDT 24
Peak memory 194856 kb
Host smart-2afd3516-ddba-4926-bea9-0beac1cd0859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006101324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2006101324
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.3398352015
Short name T463
Test name
Test status
Simulation time 49880538 ps
CPU time 0.9 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:22 PM PDT 24
Peak memory 197124 kb
Host smart-75a3ae71-15df-40a2-86f2-fdd2da2cd7f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398352015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.3398352015
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3757853044
Short name T552
Test name
Test status
Simulation time 27914028 ps
CPU time 1.21 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 196784 kb
Host smart-24605358-7b2d-49a7-9774-82dc6c043c0d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757853044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3757853044
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1119129473
Short name T629
Test name
Test status
Simulation time 70471220 ps
CPU time 1.59 seconds
Started Jun 24 05:19:19 PM PDT 24
Finished Jun 24 05:19:22 PM PDT 24
Peak memory 195792 kb
Host smart-000cae1d-2861-4268-8faf-3cc39b25f577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119129473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1119129473
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.47506161
Short name T437
Test name
Test status
Simulation time 16294841 ps
CPU time 0.66 seconds
Started Jun 24 05:19:18 PM PDT 24
Finished Jun 24 05:19:20 PM PDT 24
Peak memory 194192 kb
Host smart-cdaa3a80-7f63-4f92-9d4f-1986aa4fe050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47506161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.47506161
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2025851172
Short name T643
Test name
Test status
Simulation time 128057388 ps
CPU time 1.33 seconds
Started Jun 24 05:19:18 PM PDT 24
Finished Jun 24 05:19:20 PM PDT 24
Peak memory 197996 kb
Host smart-d79d5b4c-c5d6-4dc9-b86e-57d96d8991fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025851172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2025851172
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2948208989
Short name T529
Test name
Test status
Simulation time 340835978 ps
CPU time 2.38 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:25 PM PDT 24
Peak memory 197944 kb
Host smart-cda79562-0905-4fdf-8beb-1d7cd499219c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948208989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2948208989
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1691749373
Short name T591
Test name
Test status
Simulation time 65718645 ps
CPU time 1.33 seconds
Started Jun 24 05:19:22 PM PDT 24
Finished Jun 24 05:19:25 PM PDT 24
Peak memory 198024 kb
Host smart-511af4fa-195c-40ae-994d-dbb2672e3c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691749373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1691749373
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1465905610
Short name T518
Test name
Test status
Simulation time 321233455 ps
CPU time 1.3 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 195452 kb
Host smart-2859d5d2-0881-41a4-aa50-d2d5a678700f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465905610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1465905610
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.978879858
Short name T201
Test name
Test status
Simulation time 17230102895 ps
CPU time 131.25 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:21:34 PM PDT 24
Peak memory 198096 kb
Host smart-4dfe94c2-f585-4203-ab7b-b682f9b481bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978879858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.978879858
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1608145624
Short name T60
Test name
Test status
Simulation time 185706864302 ps
CPU time 1915.87 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:51:17 PM PDT 24
Peak memory 198184 kb
Host smart-331ac59f-a29f-4903-9e70-0d67b534fc6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1608145624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1608145624
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1608999794
Short name T232
Test name
Test status
Simulation time 16149964 ps
CPU time 0.61 seconds
Started Jun 24 05:19:28 PM PDT 24
Finished Jun 24 05:19:30 PM PDT 24
Peak memory 193968 kb
Host smart-903ec983-cdf0-4792-b3eb-4818f63cb918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608999794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1608999794
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3458353795
Short name T63
Test name
Test status
Simulation time 118088704 ps
CPU time 0.83 seconds
Started Jun 24 05:19:28 PM PDT 24
Finished Jun 24 05:19:31 PM PDT 24
Peak memory 196072 kb
Host smart-0661d110-a7e7-477a-b99a-1d13b6396875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458353795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3458353795
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2524369810
Short name T662
Test name
Test status
Simulation time 1205402160 ps
CPU time 17.84 seconds
Started Jun 24 05:19:27 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 197904 kb
Host smart-7560aef4-1093-4c25-97c9-f4a4b3d54f0d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524369810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2524369810
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3210701162
Short name T182
Test name
Test status
Simulation time 73619461 ps
CPU time 0.94 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:29 PM PDT 24
Peak memory 197076 kb
Host smart-02ee48e5-1521-4188-9c22-57d2cf57e625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210701162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3210701162
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3884770029
Short name T305
Test name
Test status
Simulation time 103392389 ps
CPU time 1.15 seconds
Started Jun 24 05:19:25 PM PDT 24
Finished Jun 24 05:19:27 PM PDT 24
Peak memory 196680 kb
Host smart-b4283e75-b2a6-43c4-979d-69cad2f54b6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884770029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3884770029
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.8883597
Short name T557
Test name
Test status
Simulation time 575670330 ps
CPU time 3.36 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:31 PM PDT 24
Peak memory 198108 kb
Host smart-6e47371f-fcf3-4eeb-a6a3-ab26951a9e1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8883597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.gpio_intr_with_filter_rand_intr_event.8883597
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2542693943
Short name T19
Test name
Test status
Simulation time 360022388 ps
CPU time 2.75 seconds
Started Jun 24 05:19:27 PM PDT 24
Finished Jun 24 05:19:31 PM PDT 24
Peak memory 197240 kb
Host smart-90146f96-869d-4508-821d-e069a91c1fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542693943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2542693943
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2910330115
Short name T184
Test name
Test status
Simulation time 34339686 ps
CPU time 0.85 seconds
Started Jun 24 05:19:21 PM PDT 24
Finished Jun 24 05:19:24 PM PDT 24
Peak memory 197012 kb
Host smart-0e9025c7-8c37-43c2-aceb-183473e3bbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910330115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2910330115
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3127270286
Short name T123
Test name
Test status
Simulation time 114814762 ps
CPU time 1.19 seconds
Started Jun 24 05:19:29 PM PDT 24
Finished Jun 24 05:19:32 PM PDT 24
Peak memory 197024 kb
Host smart-8579def3-b1fd-4ce9-ba83-e909c04b1864
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127270286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3127270286
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.4236839292
Short name T699
Test name
Test status
Simulation time 2072158602 ps
CPU time 6.15 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:34 PM PDT 24
Peak memory 197964 kb
Host smart-6d1ef765-8a2f-448b-bdee-2bf9cdb6b8dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236839292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.4236839292
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3582798741
Short name T572
Test name
Test status
Simulation time 58233000 ps
CPU time 0.87 seconds
Started Jun 24 05:19:20 PM PDT 24
Finished Jun 24 05:19:22 PM PDT 24
Peak memory 195200 kb
Host smart-276e3133-e707-4c80-bc01-27a3ac15989e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582798741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3582798741
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.303718532
Short name T394
Test name
Test status
Simulation time 358004508 ps
CPU time 1.27 seconds
Started Jun 24 05:19:19 PM PDT 24
Finished Jun 24 05:19:22 PM PDT 24
Peak memory 195576 kb
Host smart-6608031e-e0ef-46e9-9308-eac7cb40c9c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303718532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.303718532
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1739931853
Short name T689
Test name
Test status
Simulation time 6311174073 ps
CPU time 41.92 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:20:09 PM PDT 24
Peak memory 198104 kb
Host smart-2d51f676-d713-405f-bb57-0804f1f41e44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739931853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1739931853
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2049357796
Short name T314
Test name
Test status
Simulation time 38800486 ps
CPU time 0.59 seconds
Started Jun 24 05:19:27 PM PDT 24
Finished Jun 24 05:19:29 PM PDT 24
Peak memory 194680 kb
Host smart-994287f5-c1b3-4a08-856e-4397a45231cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049357796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2049357796
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.510012377
Short name T167
Test name
Test status
Simulation time 87470885 ps
CPU time 0.8 seconds
Started Jun 24 05:19:29 PM PDT 24
Finished Jun 24 05:19:31 PM PDT 24
Peak memory 195392 kb
Host smart-78760d2d-abdc-4ebd-a905-1551e43edd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510012377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.510012377
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2027134462
Short name T313
Test name
Test status
Simulation time 1391890436 ps
CPU time 19.27 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:47 PM PDT 24
Peak memory 196676 kb
Host smart-c815f44e-2108-4656-aad7-06631a9b6dca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027134462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2027134462
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3596748221
Short name T526
Test name
Test status
Simulation time 306725872 ps
CPU time 1.06 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:28 PM PDT 24
Peak memory 196276 kb
Host smart-49a8e113-ddef-4c86-a578-1ff2c1b6b613
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596748221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3596748221
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3816767731
Short name T368
Test name
Test status
Simulation time 55887407 ps
CPU time 1.44 seconds
Started Jun 24 05:19:25 PM PDT 24
Finished Jun 24 05:19:28 PM PDT 24
Peak memory 196784 kb
Host smart-93549de7-b7b2-4eab-aa19-503a96d970da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816767731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3816767731
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.25503587
Short name T340
Test name
Test status
Simulation time 23719323 ps
CPU time 1.08 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:29 PM PDT 24
Peak memory 195960 kb
Host smart-ea06ebae-836b-425b-bf26-ff8085ceba2e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.gpio_intr_with_filter_rand_intr_event.25503587
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.416219885
Short name T283
Test name
Test status
Simulation time 95251262 ps
CPU time 2.79 seconds
Started Jun 24 05:19:25 PM PDT 24
Finished Jun 24 05:19:29 PM PDT 24
Peak memory 197912 kb
Host smart-06f77745-1950-4b07-b248-7dd9d29b7fb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416219885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
416219885
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2658023244
Short name T14
Test name
Test status
Simulation time 122758845 ps
CPU time 1.19 seconds
Started Jun 24 05:19:27 PM PDT 24
Finished Jun 24 05:19:30 PM PDT 24
Peak memory 196044 kb
Host smart-7bf6b912-10a4-4482-ae26-c75480dcfa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658023244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2658023244
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.4137697196
Short name T488
Test name
Test status
Simulation time 21683368 ps
CPU time 0.89 seconds
Started Jun 24 05:19:27 PM PDT 24
Finished Jun 24 05:19:29 PM PDT 24
Peak memory 195968 kb
Host smart-67401b00-2f7d-45d7-a43a-de3a5b81db2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137697196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.4137697196
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.231267232
Short name T236
Test name
Test status
Simulation time 287565667 ps
CPU time 3.58 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:31 PM PDT 24
Peak memory 197760 kb
Host smart-90fc500f-9dc9-4651-85d2-0d4a921d295c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231267232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.231267232
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.329921994
Short name T222
Test name
Test status
Simulation time 206227285 ps
CPU time 1.08 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:19:29 PM PDT 24
Peak memory 196292 kb
Host smart-fe09bc5f-6e1e-4dd5-a6a9-011a32e459ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329921994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.329921994
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3482738090
Short name T574
Test name
Test status
Simulation time 266360116 ps
CPU time 1.32 seconds
Started Jun 24 05:19:27 PM PDT 24
Finished Jun 24 05:19:29 PM PDT 24
Peak memory 197960 kb
Host smart-503b0430-0841-435c-a187-0581824c27f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482738090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3482738090
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2190356586
Short name T392
Test name
Test status
Simulation time 13136030991 ps
CPU time 166.37 seconds
Started Jun 24 05:19:24 PM PDT 24
Finished Jun 24 05:22:11 PM PDT 24
Peak memory 198372 kb
Host smart-617532dc-f311-4308-8972-9ab897d4f73e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190356586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2190356586
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.549030942
Short name T534
Test name
Test status
Simulation time 79601353127 ps
CPU time 1535.97 seconds
Started Jun 24 05:19:26 PM PDT 24
Finished Jun 24 05:45:04 PM PDT 24
Peak memory 198088 kb
Host smart-39036039-7362-4d0e-b6f4-64f3e50fb5cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=549030942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.549030942
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1645696546
Short name T262
Test name
Test status
Simulation time 63227213 ps
CPU time 0.61 seconds
Started Jun 24 05:19:39 PM PDT 24
Finished Jun 24 05:19:41 PM PDT 24
Peak memory 193736 kb
Host smart-32286acc-f362-4038-b36c-fa8b90f63d6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645696546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1645696546
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.97059749
Short name T468
Test name
Test status
Simulation time 23413562 ps
CPU time 0.67 seconds
Started Jun 24 05:19:34 PM PDT 24
Finished Jun 24 05:19:36 PM PDT 24
Peak memory 193920 kb
Host smart-d5283d24-1b39-4376-abc3-4f4a29bc4ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97059749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.97059749
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4257527585
Short name T166
Test name
Test status
Simulation time 218131192 ps
CPU time 5.68 seconds
Started Jun 24 05:19:36 PM PDT 24
Finished Jun 24 05:19:42 PM PDT 24
Peak memory 196788 kb
Host smart-862c3416-13a1-4c44-b9c8-a3508796fd14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257527585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4257527585
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1471758869
Short name T533
Test name
Test status
Simulation time 379615157 ps
CPU time 1.1 seconds
Started Jun 24 05:19:31 PM PDT 24
Finished Jun 24 05:19:33 PM PDT 24
Peak memory 196368 kb
Host smart-c1d68127-ad90-4f58-b696-b063e3dc78c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471758869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1471758869
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4153172727
Short name T247
Test name
Test status
Simulation time 198085222 ps
CPU time 0.85 seconds
Started Jun 24 05:19:34 PM PDT 24
Finished Jun 24 05:19:35 PM PDT 24
Peak memory 195532 kb
Host smart-5328a014-bf0c-445b-85b1-4334442d7a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153172727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4153172727
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.384046451
Short name T651
Test name
Test status
Simulation time 330125260 ps
CPU time 3.3 seconds
Started Jun 24 05:19:37 PM PDT 24
Finished Jun 24 05:19:41 PM PDT 24
Peak memory 197916 kb
Host smart-bf75ddda-ec45-4610-bfa5-24a8351508ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384046451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.384046451
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4085792674
Short name T520
Test name
Test status
Simulation time 216464492 ps
CPU time 1.68 seconds
Started Jun 24 05:19:32 PM PDT 24
Finished Jun 24 05:19:35 PM PDT 24
Peak memory 196040 kb
Host smart-63f306f0-0051-4dc4-b344-4a4ac32a01dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085792674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4085792674
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.48476184
Short name T522
Test name
Test status
Simulation time 46422006 ps
CPU time 1.05 seconds
Started Jun 24 05:19:34 PM PDT 24
Finished Jun 24 05:19:36 PM PDT 24
Peak memory 196528 kb
Host smart-a86fe956-ba8b-45db-a594-15dbb62814bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48476184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.48476184
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1920371628
Short name T531
Test name
Test status
Simulation time 276774690 ps
CPU time 1.38 seconds
Started Jun 24 05:19:38 PM PDT 24
Finished Jun 24 05:19:40 PM PDT 24
Peak memory 196992 kb
Host smart-b2dc7f6a-065e-4638-a015-5f78cf1190eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920371628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1920371628
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.748306439
Short name T479
Test name
Test status
Simulation time 496281033 ps
CPU time 5.7 seconds
Started Jun 24 05:19:38 PM PDT 24
Finished Jun 24 05:19:44 PM PDT 24
Peak memory 197804 kb
Host smart-09403342-64dc-42eb-8fe3-7c7abafbbb71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748306439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.748306439
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1714349548
Short name T245
Test name
Test status
Simulation time 180974589 ps
CPU time 1.41 seconds
Started Jun 24 05:19:25 PM PDT 24
Finished Jun 24 05:19:27 PM PDT 24
Peak memory 196824 kb
Host smart-ca8bee8f-2718-404c-8f39-4d505eb719c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714349548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1714349548
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2083290950
Short name T183
Test name
Test status
Simulation time 40658602 ps
CPU time 0.93 seconds
Started Jun 24 05:19:30 PM PDT 24
Finished Jun 24 05:19:32 PM PDT 24
Peak memory 196244 kb
Host smart-e368b393-ac14-42ba-8fa6-77dcd9e2a455
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083290950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2083290950
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.802152317
Short name T516
Test name
Test status
Simulation time 14284472580 ps
CPU time 203.28 seconds
Started Jun 24 05:19:37 PM PDT 24
Finished Jun 24 05:23:01 PM PDT 24
Peak memory 197916 kb
Host smart-792ba76b-6eeb-4822-a235-5c542bda982c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802152317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.802152317
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.699715568
Short name T647
Test name
Test status
Simulation time 525516950168 ps
CPU time 2893.35 seconds
Started Jun 24 05:19:36 PM PDT 24
Finished Jun 24 06:07:51 PM PDT 24
Peak memory 198124 kb
Host smart-4c259e08-9d12-4b75-95e1-16acf44d95b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=699715568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.699715568
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1953066173
Short name T483
Test name
Test status
Simulation time 23605632 ps
CPU time 0.61 seconds
Started Jun 24 05:19:38 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 193992 kb
Host smart-2dea5572-54ff-4e73-993d-c922f1256605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953066173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1953066173
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2598713520
Short name T621
Test name
Test status
Simulation time 118001942 ps
CPU time 0.77 seconds
Started Jun 24 05:19:33 PM PDT 24
Finished Jun 24 05:19:35 PM PDT 24
Peak memory 195832 kb
Host smart-9a5be279-1f94-44fc-a294-d7003d089a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598713520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2598713520
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.962675288
Short name T396
Test name
Test status
Simulation time 504011051 ps
CPU time 14.17 seconds
Started Jun 24 05:19:39 PM PDT 24
Finished Jun 24 05:19:54 PM PDT 24
Peak memory 196976 kb
Host smart-ad914628-18d7-4e03-90c8-8d6c62b5fe14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962675288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.962675288
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4257407077
Short name T586
Test name
Test status
Simulation time 310069163 ps
CPU time 1.01 seconds
Started Jun 24 05:19:34 PM PDT 24
Finished Jun 24 05:19:36 PM PDT 24
Peak memory 197796 kb
Host smart-5f3e5dc3-568e-47d7-a4b7-1580d2ef7eb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257407077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4257407077
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1535466514
Short name T161
Test name
Test status
Simulation time 30945446 ps
CPU time 0.79 seconds
Started Jun 24 05:19:34 PM PDT 24
Finished Jun 24 05:19:36 PM PDT 24
Peak memory 196112 kb
Host smart-8694fe55-cab5-4731-9844-0722d0a7eb9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535466514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1535466514
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1195260258
Short name T138
Test name
Test status
Simulation time 817163715 ps
CPU time 2.92 seconds
Started Jun 24 05:19:38 PM PDT 24
Finished Jun 24 05:19:42 PM PDT 24
Peak memory 197916 kb
Host smart-c45d218b-7a6c-4a8b-b4db-21e270478b4e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195260258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1195260258
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2453575930
Short name T334
Test name
Test status
Simulation time 93368326 ps
CPU time 2.08 seconds
Started Jun 24 05:19:35 PM PDT 24
Finished Jun 24 05:19:38 PM PDT 24
Peak memory 196680 kb
Host smart-12b96655-d515-4289-bcd3-d3630b704d5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453575930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2453575930
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3965104385
Short name T419
Test name
Test status
Simulation time 292629164 ps
CPU time 1.13 seconds
Started Jun 24 05:19:35 PM PDT 24
Finished Jun 24 05:19:37 PM PDT 24
Peak memory 196496 kb
Host smart-4f17e77e-2bae-45c7-b079-16ff8d51be07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965104385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3965104385
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3755271018
Short name T256
Test name
Test status
Simulation time 30106095 ps
CPU time 1.12 seconds
Started Jun 24 05:19:35 PM PDT 24
Finished Jun 24 05:19:37 PM PDT 24
Peak memory 196056 kb
Host smart-5f489ab0-ed1b-4fb5-95e8-9d934ec188f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755271018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3755271018
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4270271335
Short name T478
Test name
Test status
Simulation time 177951189 ps
CPU time 1.42 seconds
Started Jun 24 05:19:36 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 197908 kb
Host smart-a737b219-87e5-46f7-aeb9-3d22fb345cc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270271335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4270271335
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3180635414
Short name T190
Test name
Test status
Simulation time 146681919 ps
CPU time 0.98 seconds
Started Jun 24 05:19:37 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 195608 kb
Host smart-87d5338e-dcce-438a-a36e-0d0aade78026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180635414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3180635414
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.123295789
Short name T260
Test name
Test status
Simulation time 50581993 ps
CPU time 1.08 seconds
Started Jun 24 05:19:37 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 195476 kb
Host smart-5ef060c6-3afe-46b1-9538-fe83df14b24d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123295789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.123295789
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.578738651
Short name T444
Test name
Test status
Simulation time 5117030353 ps
CPU time 73.46 seconds
Started Jun 24 05:19:35 PM PDT 24
Finished Jun 24 05:20:50 PM PDT 24
Peak memory 197964 kb
Host smart-585a5a57-8758-4f69-9c4e-b6365f4b24ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578738651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.578738651
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3904007999
Short name T332
Test name
Test status
Simulation time 61920266 ps
CPU time 0.59 seconds
Started Jun 24 05:19:38 PM PDT 24
Finished Jun 24 05:19:40 PM PDT 24
Peak memory 193888 kb
Host smart-cabd6856-dbd7-4819-8fa8-3fbbb6ef725c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904007999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3904007999
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1066613431
Short name T212
Test name
Test status
Simulation time 30155129 ps
CPU time 0.91 seconds
Started Jun 24 05:19:39 PM PDT 24
Finished Jun 24 05:19:41 PM PDT 24
Peak memory 196924 kb
Host smart-f225c9e8-dc49-41ce-9608-1f141e3a81a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066613431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1066613431
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2809470421
Short name T682
Test name
Test status
Simulation time 153408226 ps
CPU time 5.69 seconds
Started Jun 24 05:19:36 PM PDT 24
Finished Jun 24 05:19:43 PM PDT 24
Peak memory 196748 kb
Host smart-bca5fed1-a3de-495a-b856-87b09ee67477
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809470421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2809470421
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1274594940
Short name T151
Test name
Test status
Simulation time 279108997 ps
CPU time 1.08 seconds
Started Jun 24 05:19:33 PM PDT 24
Finished Jun 24 05:19:35 PM PDT 24
Peak memory 196572 kb
Host smart-9b9ff486-edcc-4041-8951-cebfafa4b4d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274594940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1274594940
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2057807932
Short name T255
Test name
Test status
Simulation time 50979506 ps
CPU time 1.54 seconds
Started Jun 24 05:19:38 PM PDT 24
Finished Jun 24 05:19:41 PM PDT 24
Peak memory 197000 kb
Host smart-a27a2faf-b756-4c71-9cf5-98b149397f2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057807932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2057807932
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.295406982
Short name T217
Test name
Test status
Simulation time 796266897 ps
CPU time 3.07 seconds
Started Jun 24 05:19:33 PM PDT 24
Finished Jun 24 05:19:37 PM PDT 24
Peak memory 197992 kb
Host smart-03268c32-2c3c-48ee-aa24-494419c2ffbe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295406982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.295406982
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4286167155
Short name T66
Test name
Test status
Simulation time 81589206 ps
CPU time 2.56 seconds
Started Jun 24 05:19:35 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 197964 kb
Host smart-1a5b8674-dc08-4af8-a819-534a801d1e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286167155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4286167155
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1438766877
Short name T189
Test name
Test status
Simulation time 82015185 ps
CPU time 1.36 seconds
Started Jun 24 05:19:37 PM PDT 24
Finished Jun 24 05:19:39 PM PDT 24
Peak memory 196852 kb
Host smart-9ca0c7b8-3a44-498d-9862-303bfdf4c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438766877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1438766877
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.611639871
Short name T385
Test name
Test status
Simulation time 28788616 ps
CPU time 1.1 seconds
Started Jun 24 05:19:34 PM PDT 24
Finished Jun 24 05:19:36 PM PDT 24
Peak memory 196000 kb
Host smart-e78dc5b5-eebe-48bc-87fa-385d9ea2a093
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611639871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.611639871
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_smoke.3691919518
Short name T602
Test name
Test status
Simulation time 68257130 ps
CPU time 1.29 seconds
Started Jun 24 05:19:34 PM PDT 24
Finished Jun 24 05:19:36 PM PDT 24
Peak memory 195760 kb
Host smart-9a0c7d07-8654-4949-ac56-8ce16d692690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691919518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3691919518
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1103169507
Short name T203
Test name
Test status
Simulation time 809731614 ps
CPU time 1.72 seconds
Started Jun 24 05:19:36 PM PDT 24
Finished Jun 24 05:19:38 PM PDT 24
Peak memory 197940 kb
Host smart-11fb889f-96d6-4724-bf91-7d03dae02dca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103169507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1103169507
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1109073344
Short name T297
Test name
Test status
Simulation time 12455170146 ps
CPU time 36.14 seconds
Started Jun 24 05:19:35 PM PDT 24
Finished Jun 24 05:20:12 PM PDT 24
Peak memory 198096 kb
Host smart-6cf59b1f-7f62-46b5-8b96-ff4d8e778240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109073344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1109073344
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1794870747
Short name T54
Test name
Test status
Simulation time 128734722178 ps
CPU time 703.61 seconds
Started Jun 24 05:19:38 PM PDT 24
Finished Jun 24 05:31:23 PM PDT 24
Peak memory 198036 kb
Host smart-6f085f37-d51e-4866-93a5-85a5fad30180
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1794870747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1794870747
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2210652068
Short name T500
Test name
Test status
Simulation time 14611105 ps
CPU time 0.57 seconds
Started Jun 24 05:19:42 PM PDT 24
Finished Jun 24 05:19:43 PM PDT 24
Peak memory 193772 kb
Host smart-d8108962-9721-4d1c-ba6a-566e4f419b8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210652068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2210652068
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.148416255
Short name T663
Test name
Test status
Simulation time 39502322 ps
CPU time 0.67 seconds
Started Jun 24 05:19:41 PM PDT 24
Finished Jun 24 05:19:42 PM PDT 24
Peak memory 194728 kb
Host smart-4c32c4e8-55ef-4ecf-beb1-1196cc6e796c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148416255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.148416255
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1953541214
Short name T646
Test name
Test status
Simulation time 782590074 ps
CPU time 21.89 seconds
Started Jun 24 05:19:43 PM PDT 24
Finished Jun 24 05:20:06 PM PDT 24
Peak memory 195480 kb
Host smart-03735c37-7574-4836-8b16-d5317f69df14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953541214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1953541214
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2551709023
Short name T473
Test name
Test status
Simulation time 136582932 ps
CPU time 0.82 seconds
Started Jun 24 05:19:41 PM PDT 24
Finished Jun 24 05:19:43 PM PDT 24
Peak memory 195792 kb
Host smart-34c3b7ee-9fea-4a64-b2d6-749c18f5fbf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551709023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2551709023
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2964482863
Short name T239
Test name
Test status
Simulation time 135767024 ps
CPU time 1.14 seconds
Started Jun 24 05:19:45 PM PDT 24
Finished Jun 24 05:19:47 PM PDT 24
Peak memory 196072 kb
Host smart-9f414a6e-a032-4330-8e2e-a924de2d965d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964482863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2964482863
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1878474798
Short name T482
Test name
Test status
Simulation time 1656329433 ps
CPU time 3.61 seconds
Started Jun 24 05:19:42 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 198392 kb
Host smart-011e8b2a-a73b-42df-93cd-2b1dcecfaaae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878474798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1878474798
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2697972623
Short name T116
Test name
Test status
Simulation time 166670619 ps
CPU time 3.39 seconds
Started Jun 24 05:19:42 PM PDT 24
Finished Jun 24 05:19:47 PM PDT 24
Peak memory 198072 kb
Host smart-8d25126b-68cc-4b8c-86d9-b206985825da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697972623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2697972623
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.316875531
Short name T382
Test name
Test status
Simulation time 229491822 ps
CPU time 1.27 seconds
Started Jun 24 05:19:39 PM PDT 24
Finished Jun 24 05:19:41 PM PDT 24
Peak memory 198284 kb
Host smart-5a7c4edc-9282-4fd7-a6b4-becf61ccf226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316875531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.316875531
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1098066358
Short name T142
Test name
Test status
Simulation time 40681621 ps
CPU time 1 seconds
Started Jun 24 05:19:41 PM PDT 24
Finished Jun 24 05:19:43 PM PDT 24
Peak memory 195772 kb
Host smart-98c66ba2-cff7-45cf-af26-ac53b264276e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098066358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1098066358
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.169217030
Short name T4
Test name
Test status
Simulation time 704594605 ps
CPU time 4.16 seconds
Started Jun 24 05:19:45 PM PDT 24
Finished Jun 24 05:19:50 PM PDT 24
Peak memory 197940 kb
Host smart-cad319d5-2789-444b-b0b9-0c4e0852bb51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169217030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.169217030
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1571132761
Short name T547
Test name
Test status
Simulation time 28550995 ps
CPU time 0.98 seconds
Started Jun 24 05:19:47 PM PDT 24
Finished Jun 24 05:19:49 PM PDT 24
Peak memory 195240 kb
Host smart-91c744f8-134e-407f-9fda-e0f7bf0284ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571132761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1571132761
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2150746401
Short name T108
Test name
Test status
Simulation time 147839076 ps
CPU time 0.89 seconds
Started Jun 24 05:19:45 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 195364 kb
Host smart-3a7f8d99-a812-41f1-b6a4-3027459925ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150746401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2150746401
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2107800815
Short name T177
Test name
Test status
Simulation time 5546017833 ps
CPU time 144.6 seconds
Started Jun 24 05:19:43 PM PDT 24
Finished Jun 24 05:22:09 PM PDT 24
Peak memory 198108 kb
Host smart-e83aefc5-b380-4305-8398-218434154e8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107800815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2107800815
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1236885605
Short name T58
Test name
Test status
Simulation time 240564577803 ps
CPU time 1355.77 seconds
Started Jun 24 05:19:41 PM PDT 24
Finished Jun 24 05:42:18 PM PDT 24
Peak memory 198120 kb
Host smart-9862638d-7899-4b37-868d-d2d1fa36534d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1236885605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1236885605
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3356478858
Short name T163
Test name
Test status
Simulation time 13512092 ps
CPU time 0.61 seconds
Started Jun 24 05:19:51 PM PDT 24
Finished Jun 24 05:19:53 PM PDT 24
Peak memory 193760 kb
Host smart-02575388-f464-4310-bc82-ad1e0343fcd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356478858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3356478858
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1976055454
Short name T524
Test name
Test status
Simulation time 29978969 ps
CPU time 0.95 seconds
Started Jun 24 05:19:47 PM PDT 24
Finished Jun 24 05:19:49 PM PDT 24
Peak memory 195720 kb
Host smart-b47b6f30-c8ac-420a-993e-d7bae2e1aae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976055454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1976055454
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1501046135
Short name T273
Test name
Test status
Simulation time 1500242735 ps
CPU time 22.98 seconds
Started Jun 24 05:19:40 PM PDT 24
Finished Jun 24 05:20:04 PM PDT 24
Peak memory 196944 kb
Host smart-fafeca9d-cf1c-406a-8c3d-791d4fb0aaca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501046135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1501046135
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.288362615
Short name T122
Test name
Test status
Simulation time 61651894 ps
CPU time 1.04 seconds
Started Jun 24 05:19:41 PM PDT 24
Finished Jun 24 05:19:43 PM PDT 24
Peak memory 196524 kb
Host smart-5203695f-832f-4caa-8391-bd17e008576c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288362615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.288362615
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1740140858
Short name T447
Test name
Test status
Simulation time 389230309 ps
CPU time 1.37 seconds
Started Jun 24 05:19:43 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 195780 kb
Host smart-1a619242-92a2-41d9-9aa0-c8ff2e382eb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740140858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1740140858
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2793506446
Short name T320
Test name
Test status
Simulation time 39646574 ps
CPU time 1.56 seconds
Started Jun 24 05:19:43 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 196884 kb
Host smart-2a5ff0be-39f8-4fca-8a66-0868c5928591
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793506446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2793506446
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2518014550
Short name T285
Test name
Test status
Simulation time 146924907 ps
CPU time 1.35 seconds
Started Jun 24 05:19:43 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 196000 kb
Host smart-613a305e-c834-4273-9b61-56d604fbb418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518014550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2518014550
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3308679657
Short name T160
Test name
Test status
Simulation time 107198970 ps
CPU time 0.83 seconds
Started Jun 24 05:19:44 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 196600 kb
Host smart-c4968606-550a-4a6b-beff-2122990a8fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308679657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3308679657
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2997196468
Short name T143
Test name
Test status
Simulation time 255204186 ps
CPU time 1 seconds
Started Jun 24 05:19:42 PM PDT 24
Finished Jun 24 05:19:45 PM PDT 24
Peak memory 195984 kb
Host smart-980b775b-41f8-43d1-aaa7-b79bf96556aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997196468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2997196468
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.664888516
Short name T276
Test name
Test status
Simulation time 49740301 ps
CPU time 1.18 seconds
Started Jun 24 05:19:45 PM PDT 24
Finished Jun 24 05:19:47 PM PDT 24
Peak memory 196236 kb
Host smart-32a46440-0e82-48c5-9a16-6b8fec48dd97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664888516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.664888516
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.85296142
Short name T50
Test name
Test status
Simulation time 35467242 ps
CPU time 0.98 seconds
Started Jun 24 05:19:45 PM PDT 24
Finished Jun 24 05:19:46 PM PDT 24
Peak memory 195512 kb
Host smart-ccd50b64-96f7-443c-95d9-0523e01fe1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85296142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.85296142
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1472093701
Short name T132
Test name
Test status
Simulation time 108192215 ps
CPU time 1.13 seconds
Started Jun 24 05:19:42 PM PDT 24
Finished Jun 24 05:19:45 PM PDT 24
Peak memory 195736 kb
Host smart-74373743-3dd3-46e4-a956-cf695cfcd835
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472093701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1472093701
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3626440420
Short name T545
Test name
Test status
Simulation time 20343383104 ps
CPU time 93.46 seconds
Started Jun 24 05:19:43 PM PDT 24
Finished Jun 24 05:21:18 PM PDT 24
Peak memory 198100 kb
Host smart-7173e5e7-5b07-4f72-a0a8-4f977dc2160f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626440420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3626440420
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.726353715
Short name T441
Test name
Test status
Simulation time 106399512907 ps
CPU time 451.13 seconds
Started Jun 24 05:19:42 PM PDT 24
Finished Jun 24 05:27:15 PM PDT 24
Peak memory 198160 kb
Host smart-b0f38aa9-76dc-4b33-a6bc-25ca811efde9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=726353715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.726353715
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.963676569
Short name T688
Test name
Test status
Simulation time 16886765 ps
CPU time 0.6 seconds
Started Jun 24 05:19:49 PM PDT 24
Finished Jun 24 05:19:50 PM PDT 24
Peak memory 193900 kb
Host smart-436d784e-af6c-4639-8482-e4d3df93d170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963676569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.963676569
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3546045212
Short name T157
Test name
Test status
Simulation time 75650112 ps
CPU time 0.85 seconds
Started Jun 24 05:19:47 PM PDT 24
Finished Jun 24 05:19:48 PM PDT 24
Peak memory 195376 kb
Host smart-e6861cd2-e9b7-4a9e-901d-7d24cae2766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546045212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3546045212
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3070275337
Short name T567
Test name
Test status
Simulation time 913044207 ps
CPU time 26.59 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:20:15 PM PDT 24
Peak memory 196944 kb
Host smart-be5f4276-f4cd-4a1a-8402-d91ef0495c3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070275337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3070275337
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.579619237
Short name T652
Test name
Test status
Simulation time 98865743 ps
CPU time 1.14 seconds
Started Jun 24 05:19:51 PM PDT 24
Finished Jun 24 05:19:54 PM PDT 24
Peak memory 196644 kb
Host smart-daf02bf5-c58d-4255-99dd-5921561adeda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579619237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.579619237
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.4270139582
Short name T200
Test name
Test status
Simulation time 117862760 ps
CPU time 1.15 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:19:52 PM PDT 24
Peak memory 196480 kb
Host smart-7c31cb72-b269-4dbc-b9ba-a03a62bd80fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270139582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.4270139582
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.667246266
Short name T53
Test name
Test status
Simulation time 63081366 ps
CPU time 2.5 seconds
Started Jun 24 05:19:52 PM PDT 24
Finished Jun 24 05:19:55 PM PDT 24
Peak memory 197972 kb
Host smart-4c58c810-a465-4f00-ae37-d8df0dd396de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667246266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.667246266
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.423891847
Short name T446
Test name
Test status
Simulation time 282139851 ps
CPU time 2.44 seconds
Started Jun 24 05:19:51 PM PDT 24
Finished Jun 24 05:19:54 PM PDT 24
Peak memory 197024 kb
Host smart-8cc5ce17-a48a-4271-8434-a5b637784c1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423891847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
423891847
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3952286114
Short name T208
Test name
Test status
Simulation time 101008785 ps
CPU time 1.07 seconds
Started Jun 24 05:19:42 PM PDT 24
Finished Jun 24 05:19:44 PM PDT 24
Peak memory 196088 kb
Host smart-1496e007-5795-42aa-bd83-8687ef03cbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952286114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3952286114
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2194783851
Short name T69
Test name
Test status
Simulation time 100710920 ps
CPU time 0.66 seconds
Started Jun 24 05:19:51 PM PDT 24
Finished Jun 24 05:19:53 PM PDT 24
Peak memory 194128 kb
Host smart-78579e74-6f91-4d00-a8e8-a0d3ad988d88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194783851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2194783851
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_smoke.3934643953
Short name T664
Test name
Test status
Simulation time 169234413 ps
CPU time 1.22 seconds
Started Jun 24 05:19:43 PM PDT 24
Finished Jun 24 05:19:45 PM PDT 24
Peak memory 197952 kb
Host smart-1b637daf-e1ba-4ac8-a19d-050aef52d2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934643953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3934643953
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2158689276
Short name T537
Test name
Test status
Simulation time 168951110 ps
CPU time 1.19 seconds
Started Jun 24 05:19:47 PM PDT 24
Finished Jun 24 05:19:49 PM PDT 24
Peak memory 195400 kb
Host smart-bca16326-1232-4cd2-891a-2610f72cd1ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158689276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2158689276
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3132073943
Short name T562
Test name
Test status
Simulation time 3674482729 ps
CPU time 39.27 seconds
Started Jun 24 05:19:52 PM PDT 24
Finished Jun 24 05:20:33 PM PDT 24
Peak memory 198032 kb
Host smart-74adc499-7f37-4f3a-875c-2cad4402fe44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132073943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3132073943
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3798639838
Short name T619
Test name
Test status
Simulation time 182737906650 ps
CPU time 1280.15 seconds
Started Jun 24 05:19:47 PM PDT 24
Finished Jun 24 05:41:08 PM PDT 24
Peak memory 198140 kb
Host smart-e6dbddd2-9d9a-46be-8909-52ea7494d9cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3798639838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3798639838
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2410120634
Short name T658
Test name
Test status
Simulation time 35420157 ps
CPU time 0.56 seconds
Started Jun 24 05:19:52 PM PDT 24
Finished Jun 24 05:19:54 PM PDT 24
Peak memory 193676 kb
Host smart-8e310123-8a37-4ea2-b863-c998269add2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410120634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2410120634
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1412010100
Short name T517
Test name
Test status
Simulation time 163008077 ps
CPU time 0.87 seconds
Started Jun 24 05:19:51 PM PDT 24
Finished Jun 24 05:19:53 PM PDT 24
Peak memory 196528 kb
Host smart-ee21a510-5b11-44b4-b2d8-4d60c4d4e732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412010100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1412010100
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2223279586
Short name T669
Test name
Test status
Simulation time 1047551077 ps
CPU time 9.01 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:19:58 PM PDT 24
Peak memory 196712 kb
Host smart-e21c7f4b-0693-4859-8c71-4703e52e8a4d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223279586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2223279586
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1561163395
Short name T149
Test name
Test status
Simulation time 75918954 ps
CPU time 0.7 seconds
Started Jun 24 05:19:47 PM PDT 24
Finished Jun 24 05:19:48 PM PDT 24
Peak memory 194380 kb
Host smart-6e9c9a18-cfed-46b4-b525-857315327c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561163395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1561163395
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2869251556
Short name T636
Test name
Test status
Simulation time 19753814 ps
CPU time 0.7 seconds
Started Jun 24 05:19:50 PM PDT 24
Finished Jun 24 05:19:51 PM PDT 24
Peak memory 195300 kb
Host smart-f95589cf-75a4-460c-b65e-92c7968282e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869251556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2869251556
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1240717824
Short name T71
Test name
Test status
Simulation time 98818338 ps
CPU time 3.79 seconds
Started Jun 24 05:19:53 PM PDT 24
Finished Jun 24 05:19:58 PM PDT 24
Peak memory 198072 kb
Host smart-248ee57a-a741-475d-b50d-57a76773cbda
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240717824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1240717824
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2371316768
Short name T172
Test name
Test status
Simulation time 260398857 ps
CPU time 2.86 seconds
Started Jun 24 05:19:47 PM PDT 24
Finished Jun 24 05:19:50 PM PDT 24
Peak memory 198052 kb
Host smart-0f2d867f-02d7-4d87-b803-8907fc4f4093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371316768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2371316768
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.4288471711
Short name T393
Test name
Test status
Simulation time 16637796 ps
CPU time 0.71 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:19:50 PM PDT 24
Peak memory 194292 kb
Host smart-ad8bfb34-dfe6-4bc9-916c-800c2f5a16d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288471711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.4288471711
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2321323005
Short name T328
Test name
Test status
Simulation time 35716817 ps
CPU time 0.95 seconds
Started Jun 24 05:19:48 PM PDT 24
Finished Jun 24 05:19:50 PM PDT 24
Peak memory 195932 kb
Host smart-14e88d20-cd7f-429b-bc13-ccb2494a9cc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321323005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2321323005
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2173404099
Short name T693
Test name
Test status
Simulation time 737953638 ps
CPU time 4.51 seconds
Started Jun 24 05:19:49 PM PDT 24
Finished Jun 24 05:19:55 PM PDT 24
Peak memory 197828 kb
Host smart-2017abb2-7a8b-465a-9606-5826ffdcda04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173404099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2173404099
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.670602012
Short name T113
Test name
Test status
Simulation time 157089585 ps
CPU time 1.28 seconds
Started Jun 24 05:19:53 PM PDT 24
Finished Jun 24 05:19:56 PM PDT 24
Peak memory 197144 kb
Host smart-1393aa0e-4a55-4002-a86f-8c70712918cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670602012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.670602012
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1607190775
Short name T492
Test name
Test status
Simulation time 57549481 ps
CPU time 1.31 seconds
Started Jun 24 05:19:49 PM PDT 24
Finished Jun 24 05:19:52 PM PDT 24
Peak memory 196180 kb
Host smart-e129ee42-1d06-471d-b0d2-103ae41656c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607190775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1607190775
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2067269654
Short name T162
Test name
Test status
Simulation time 77110566174 ps
CPU time 191.04 seconds
Started Jun 24 05:19:52 PM PDT 24
Finished Jun 24 05:23:04 PM PDT 24
Peak memory 198096 kb
Host smart-a793b8b5-80ea-42c0-9301-811dab21288c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067269654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2067269654
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1049939469
Short name T347
Test name
Test status
Simulation time 45057497 ps
CPU time 0.59 seconds
Started Jun 24 05:17:34 PM PDT 24
Finished Jun 24 05:17:36 PM PDT 24
Peak memory 194572 kb
Host smart-37c02f21-cadb-4a00-8972-b0281aa9e506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049939469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1049939469
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2193053260
Short name T401
Test name
Test status
Simulation time 42876692 ps
CPU time 0.91 seconds
Started Jun 24 05:17:35 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 197460 kb
Host smart-182f3f00-dfa4-47c2-9f92-a9321f378df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193053260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2193053260
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2882394490
Short name T525
Test name
Test status
Simulation time 307276090 ps
CPU time 7.32 seconds
Started Jun 24 05:17:37 PM PDT 24
Finished Jun 24 05:17:46 PM PDT 24
Peak memory 196652 kb
Host smart-bc12d073-aac0-416f-b000-9cdcf730428c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882394490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2882394490
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.4292204502
Short name T374
Test name
Test status
Simulation time 96777229 ps
CPU time 0.82 seconds
Started Jun 24 05:17:37 PM PDT 24
Finished Jun 24 05:17:40 PM PDT 24
Peak memory 195932 kb
Host smart-942898c1-db43-4cb5-848b-e7922d851178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292204502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.4292204502
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2657780715
Short name T548
Test name
Test status
Simulation time 825311738 ps
CPU time 1.18 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 195788 kb
Host smart-a207026b-864c-4f7b-9345-bfbf5a636f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657780715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2657780715
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3168352083
Short name T377
Test name
Test status
Simulation time 483880928 ps
CPU time 2.9 seconds
Started Jun 24 05:17:39 PM PDT 24
Finished Jun 24 05:17:43 PM PDT 24
Peak memory 198072 kb
Host smart-8d984280-8810-4ce1-acc4-7cb53f553dc4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168352083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3168352083
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4164619002
Short name T490
Test name
Test status
Simulation time 103611390 ps
CPU time 1.84 seconds
Started Jun 24 05:17:34 PM PDT 24
Finished Jun 24 05:17:36 PM PDT 24
Peak memory 196300 kb
Host smart-7cdffdea-dd11-4867-8a78-7ecf7dd04716
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164619002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4164619002
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2122832964
Short name T121
Test name
Test status
Simulation time 50666732 ps
CPU time 1.13 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:39 PM PDT 24
Peak memory 195704 kb
Host smart-d15073a9-36b7-4b5f-bfed-08e58ad090d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122832964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2122832964
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.364443248
Short name T322
Test name
Test status
Simulation time 28863365 ps
CPU time 0.7 seconds
Started Jun 24 05:17:38 PM PDT 24
Finished Jun 24 05:17:40 PM PDT 24
Peak memory 194780 kb
Host smart-616c86fb-60a9-4763-b762-096fcfaece44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364443248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.364443248
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.223161995
Short name T243
Test name
Test status
Simulation time 1753595281 ps
CPU time 5.13 seconds
Started Jun 24 05:17:40 PM PDT 24
Finished Jun 24 05:17:46 PM PDT 24
Peak memory 197960 kb
Host smart-ef3a0c63-7607-4db8-92da-8eac64396b78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223161995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.223161995
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1655086218
Short name T230
Test name
Test status
Simulation time 105050323 ps
CPU time 1.3 seconds
Started Jun 24 05:17:35 PM PDT 24
Finished Jun 24 05:17:37 PM PDT 24
Peak memory 196688 kb
Host smart-564b035f-2aeb-42e6-a7bf-fad961b4a2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655086218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1655086218
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3475960328
Short name T650
Test name
Test status
Simulation time 66881344 ps
CPU time 0.96 seconds
Started Jun 24 05:17:38 PM PDT 24
Finished Jun 24 05:17:41 PM PDT 24
Peak memory 196340 kb
Host smart-20bc79fc-24ca-4a52-b548-d479e7626096
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475960328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3475960328
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2221833006
Short name T5
Test name
Test status
Simulation time 4565894032 ps
CPU time 54.16 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:18:31 PM PDT 24
Peak memory 198096 kb
Host smart-98c3c9fd-4cfc-4a0b-a6c8-ef45b2b9c6ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221833006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2221833006
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.1864448156
Short name T521
Test name
Test status
Simulation time 67273504651 ps
CPU time 1453.57 seconds
Started Jun 24 05:17:38 PM PDT 24
Finished Jun 24 05:41:54 PM PDT 24
Peak memory 198108 kb
Host smart-93ba7fde-b52f-4594-aa11-20e098e7457f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1864448156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.1864448156
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.4238045494
Short name T563
Test name
Test status
Simulation time 11670357 ps
CPU time 0.62 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 193820 kb
Host smart-8a8a8e59-99b6-4322-b8ad-17d440d2cb61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238045494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.4238045494
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3120835895
Short name T565
Test name
Test status
Simulation time 77664678 ps
CPU time 0.72 seconds
Started Jun 24 05:17:47 PM PDT 24
Finished Jun 24 05:17:49 PM PDT 24
Peak memory 195488 kb
Host smart-17d092ab-92c5-4463-92ba-dd375b5a2fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120835895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3120835895
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1811533788
Short name T397
Test name
Test status
Simulation time 1129479552 ps
CPU time 14.94 seconds
Started Jun 24 05:17:47 PM PDT 24
Finished Jun 24 05:18:03 PM PDT 24
Peak memory 196728 kb
Host smart-4e2a7263-5a14-47ef-b049-f7b0948cd7f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811533788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1811533788
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1876998448
Short name T440
Test name
Test status
Simulation time 504267951 ps
CPU time 0.91 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:53 PM PDT 24
Peak memory 196560 kb
Host smart-69f9a164-2729-4b58-bf6e-d4e3b7518a96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876998448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1876998448
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.612025261
Short name T23
Test name
Test status
Simulation time 245563076 ps
CPU time 1.24 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:46 PM PDT 24
Peak memory 195968 kb
Host smart-ae3f589e-9232-42b6-9a42-04c3b9bfbb8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612025261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.612025261
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.307943675
Short name T671
Test name
Test status
Simulation time 239823064 ps
CPU time 2.59 seconds
Started Jun 24 05:17:45 PM PDT 24
Finished Jun 24 05:17:50 PM PDT 24
Peak memory 197872 kb
Host smart-8a6f9b34-ea33-4960-975a-a84069a8fd0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307943675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.307943675
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.556327930
Short name T555
Test name
Test status
Simulation time 390022720 ps
CPU time 2.11 seconds
Started Jun 24 05:17:44 PM PDT 24
Finished Jun 24 05:17:48 PM PDT 24
Peak memory 196024 kb
Host smart-00a879ea-684b-4a51-a3f0-982f9d3e780a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556327930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.556327930
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2665412395
Short name T411
Test name
Test status
Simulation time 39869719 ps
CPU time 0.99 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 195904 kb
Host smart-8a57cc9f-9f6b-4fa6-8198-f47ea677db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665412395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2665412395
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3984326055
Short name T512
Test name
Test status
Simulation time 377255912 ps
CPU time 1.16 seconds
Started Jun 24 05:17:47 PM PDT 24
Finished Jun 24 05:17:49 PM PDT 24
Peak memory 196068 kb
Host smart-ec76f911-e110-444e-aea9-ffc079a402a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984326055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3984326055
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2903249753
Short name T633
Test name
Test status
Simulation time 609548154 ps
CPU time 2.34 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:47 PM PDT 24
Peak memory 197948 kb
Host smart-1246c169-ae43-4105-899a-a0e20ba941fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903249753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2903249753
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1050774593
Short name T127
Test name
Test status
Simulation time 240286801 ps
CPU time 1.18 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:38 PM PDT 24
Peak memory 196204 kb
Host smart-9b738e5e-811c-451e-b58f-2fb60ae55200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050774593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1050774593
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3768006871
Short name T616
Test name
Test status
Simulation time 381142361 ps
CPU time 1.32 seconds
Started Jun 24 05:17:36 PM PDT 24
Finished Jun 24 05:17:39 PM PDT 24
Peak memory 196304 kb
Host smart-80564438-c9e9-4c4a-8223-d68bb92caf57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768006871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3768006871
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3390982291
Short name T540
Test name
Test status
Simulation time 827258917 ps
CPU time 17.73 seconds
Started Jun 24 05:17:49 PM PDT 24
Finished Jun 24 05:18:08 PM PDT 24
Peak memory 198004 kb
Host smart-9c80c5a0-0e61-464a-8e46-594fe9b7a9de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390982291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3390982291
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2162023770
Short name T589
Test name
Test status
Simulation time 13525863 ps
CPU time 0.54 seconds
Started Jun 24 05:17:50 PM PDT 24
Finished Jun 24 05:17:51 PM PDT 24
Peak memory 192628 kb
Host smart-e4884ff7-d4d6-4a97-97c8-2fb57640cae4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162023770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2162023770
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2128401926
Short name T694
Test name
Test status
Simulation time 27954747 ps
CPU time 0.7 seconds
Started Jun 24 05:17:44 PM PDT 24
Finished Jun 24 05:17:47 PM PDT 24
Peak memory 193972 kb
Host smart-ae9d6e47-3d38-4049-aa05-9eaf35fa7294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128401926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2128401926
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2616791538
Short name T186
Test name
Test status
Simulation time 2620599323 ps
CPU time 22.37 seconds
Started Jun 24 05:17:45 PM PDT 24
Finished Jun 24 05:18:09 PM PDT 24
Peak memory 196996 kb
Host smart-e6a876c9-9d06-4c36-9ef1-17dff3d84979
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616791538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2616791538
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3865629544
Short name T592
Test name
Test status
Simulation time 149208823 ps
CPU time 1.01 seconds
Started Jun 24 05:17:47 PM PDT 24
Finished Jun 24 05:17:49 PM PDT 24
Peak memory 196764 kb
Host smart-644cce8d-485d-4477-9dc2-84e6983cf9ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865629544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3865629544
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2489524134
Short name T290
Test name
Test status
Simulation time 118401940 ps
CPU time 1.38 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:46 PM PDT 24
Peak memory 196496 kb
Host smart-ced6bb4a-f7b2-431c-92b8-d259efdf8a9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489524134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2489524134
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2104894884
Short name T254
Test name
Test status
Simulation time 229436762 ps
CPU time 2.43 seconds
Started Jun 24 05:17:44 PM PDT 24
Finished Jun 24 05:17:49 PM PDT 24
Peak memory 196300 kb
Host smart-22997338-e761-4898-bf16-b97cdc87d8ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104894884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2104894884
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2298333399
Short name T295
Test name
Test status
Simulation time 363988328 ps
CPU time 1.87 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 196072 kb
Host smart-92052358-b961-4bf9-a5aa-ad26fab11b02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298333399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2298333399
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.4216745360
Short name T378
Test name
Test status
Simulation time 44066572 ps
CPU time 0.96 seconds
Started Jun 24 05:17:45 PM PDT 24
Finished Jun 24 05:17:48 PM PDT 24
Peak memory 196660 kb
Host smart-3696d40d-ef44-41e3-8f95-a4821214f931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216745360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.4216745360
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3133031324
Short name T649
Test name
Test status
Simulation time 170772515 ps
CPU time 1.17 seconds
Started Jun 24 05:17:45 PM PDT 24
Finished Jun 24 05:17:48 PM PDT 24
Peak memory 195836 kb
Host smart-8d6edf95-4548-4fde-b800-055972548603
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133031324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3133031324
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1400309012
Short name T429
Test name
Test status
Simulation time 108887110 ps
CPU time 4.81 seconds
Started Jun 24 05:17:50 PM PDT 24
Finished Jun 24 05:17:57 PM PDT 24
Peak memory 197928 kb
Host smart-d00e20fd-762d-44b5-a20e-dd1d67e7b1c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400309012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1400309012
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2568880408
Short name T450
Test name
Test status
Simulation time 691205941 ps
CPU time 1.36 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 195696 kb
Host smart-ceade760-c34e-4743-9a21-9516db408565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568880408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2568880408
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.713130353
Short name T226
Test name
Test status
Simulation time 1306341469 ps
CPU time 1.47 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 196232 kb
Host smart-38f4f19f-f7ba-40fe-bf78-f14af90e51ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713130353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.713130353
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.247561383
Short name T460
Test name
Test status
Simulation time 9858089453 ps
CPU time 68.46 seconds
Started Jun 24 05:17:50 PM PDT 24
Finished Jun 24 05:19:00 PM PDT 24
Peak memory 198064 kb
Host smart-66f27667-3ce7-4155-a6d8-f27fac180f8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247561383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.247561383
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.4116827403
Short name T101
Test name
Test status
Simulation time 265869464482 ps
CPU time 938.04 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:33:22 PM PDT 24
Peak memory 206344 kb
Host smart-ad6114f5-9e2e-422a-8566-646d370cfd8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4116827403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.4116827403
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.569824658
Short name T11
Test name
Test status
Simulation time 15596660 ps
CPU time 0.65 seconds
Started Jun 24 05:17:47 PM PDT 24
Finished Jun 24 05:17:49 PM PDT 24
Peak memory 193356 kb
Host smart-0ff72717-fc21-4fed-824a-387b311bacef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569824658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.569824658
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.926962583
Short name T275
Test name
Test status
Simulation time 87577293 ps
CPU time 0.91 seconds
Started Jun 24 05:17:50 PM PDT 24
Finished Jun 24 05:17:52 PM PDT 24
Peak memory 196376 kb
Host smart-e65dabd8-01d9-4171-ae5d-9a36132aa458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926962583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.926962583
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1442963917
Short name T627
Test name
Test status
Simulation time 2489486284 ps
CPU time 21.4 seconds
Started Jun 24 05:17:47 PM PDT 24
Finished Jun 24 05:18:10 PM PDT 24
Peak memory 196692 kb
Host smart-1b65f310-87c1-4d7d-a74b-c03a0600a0a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442963917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1442963917
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.144591375
Short name T705
Test name
Test status
Simulation time 41434093 ps
CPU time 0.77 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 196372 kb
Host smart-c91aade6-ae5b-46e0-a353-d80654e2e844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144591375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.144591375
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1206047630
Short name T16
Test name
Test status
Simulation time 27496684 ps
CPU time 0.72 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:46 PM PDT 24
Peak memory 194280 kb
Host smart-2c9ff906-9622-498a-9318-b6ce71042e02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206047630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1206047630
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.592982346
Short name T180
Test name
Test status
Simulation time 350441202 ps
CPU time 3.2 seconds
Started Jun 24 05:17:49 PM PDT 24
Finished Jun 24 05:17:53 PM PDT 24
Peak memory 197988 kb
Host smart-7a2f6d44-1836-4553-b7dd-154c0a6e8009
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592982346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.592982346
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.574107076
Short name T575
Test name
Test status
Simulation time 342558976 ps
CPU time 2.51 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:47 PM PDT 24
Peak memory 195732 kb
Host smart-ede2fa4f-0e5d-4393-a1da-54d4a322f293
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574107076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.574107076
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3952317776
Short name T638
Test name
Test status
Simulation time 17982492 ps
CPU time 0.69 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:44 PM PDT 24
Peak memory 195252 kb
Host smart-973927be-e759-4c5b-9d14-e9a0427d570e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952317776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3952317776
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3137669882
Short name T687
Test name
Test status
Simulation time 72121713 ps
CPU time 1.31 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:46 PM PDT 24
Peak memory 195836 kb
Host smart-ab117d14-8a34-4716-a882-2f66f803d452
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137669882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3137669882
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2698940873
Short name T271
Test name
Test status
Simulation time 449286387 ps
CPU time 4.18 seconds
Started Jun 24 05:17:45 PM PDT 24
Finished Jun 24 05:17:51 PM PDT 24
Peak memory 197804 kb
Host smart-d423d379-f8e7-43c7-9bc6-091645f207f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698940873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2698940873
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3643674302
Short name T601
Test name
Test status
Simulation time 47757888 ps
CPU time 1.35 seconds
Started Jun 24 05:17:45 PM PDT 24
Finished Jun 24 05:17:48 PM PDT 24
Peak memory 196648 kb
Host smart-8382c5c7-219d-440b-88f4-3efb8f716dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643674302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3643674302
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2498842044
Short name T278
Test name
Test status
Simulation time 466922950 ps
CPU time 1.19 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 195736 kb
Host smart-b46d055e-e393-4fd2-9755-71df969d0def
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498842044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2498842044
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2287723493
Short name T388
Test name
Test status
Simulation time 124933784512 ps
CPU time 178.36 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:20:43 PM PDT 24
Peak memory 198052 kb
Host smart-03ee3cbd-1511-443f-b5ca-57b76ee5fd54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287723493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2287723493
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1879168302
Short name T708
Test name
Test status
Simulation time 47475102260 ps
CPU time 909.15 seconds
Started Jun 24 05:17:50 PM PDT 24
Finished Jun 24 05:33:01 PM PDT 24
Peak memory 198168 kb
Host smart-865161f1-a293-4780-8b2d-f670fa35a66b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1879168302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1879168302
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.332701852
Short name T366
Test name
Test status
Simulation time 12301122 ps
CPU time 0.57 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 194416 kb
Host smart-abcf8091-d0d3-4049-9b6d-27ad29ff84fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332701852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.332701852
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2417014904
Short name T480
Test name
Test status
Simulation time 85941490 ps
CPU time 0.84 seconds
Started Jun 24 05:17:44 PM PDT 24
Finished Jun 24 05:17:47 PM PDT 24
Peak memory 195288 kb
Host smart-52378be7-4e6f-471d-931f-34e50e5830c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417014904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2417014904
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3015911207
Short name T681
Test name
Test status
Simulation time 696054907 ps
CPU time 23.04 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:18:16 PM PDT 24
Peak memory 196836 kb
Host smart-045464ed-d162-4d75-bbd5-13720673fb9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015911207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3015911207
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.787558381
Short name T355
Test name
Test status
Simulation time 24163841 ps
CPU time 0.71 seconds
Started Jun 24 05:17:52 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 195176 kb
Host smart-29ca9d3b-0c39-48af-95d8-d114d60b5907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787558381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.787558381
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2778294717
Short name T65
Test name
Test status
Simulation time 82160549 ps
CPU time 1.21 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 195952 kb
Host smart-4035e5a5-e5bb-4810-b497-c06a7910afc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778294717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2778294717
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3582019128
Short name T126
Test name
Test status
Simulation time 46346538 ps
CPU time 2.03 seconds
Started Jun 24 05:17:52 PM PDT 24
Finished Jun 24 05:17:56 PM PDT 24
Peak memory 198032 kb
Host smart-5b542d3e-4052-43d4-b7be-47b636bb08d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582019128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3582019128
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.4165199328
Short name T640
Test name
Test status
Simulation time 1529912646 ps
CPU time 1.68 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:17:54 PM PDT 24
Peak memory 195728 kb
Host smart-28ffd074-0d81-4cec-a28c-3b899a63b910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165199328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
4165199328
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2595738757
Short name T390
Test name
Test status
Simulation time 227197313 ps
CPU time 1.13 seconds
Started Jun 24 05:17:44 PM PDT 24
Finished Jun 24 05:17:47 PM PDT 24
Peak memory 195728 kb
Host smart-66172e4d-7c4e-417e-a78d-906a7e292079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595738757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2595738757
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.13836840
Short name T369
Test name
Test status
Simulation time 28189478 ps
CPU time 0.86 seconds
Started Jun 24 05:17:43 PM PDT 24
Finished Jun 24 05:17:46 PM PDT 24
Peak memory 197080 kb
Host smart-5d4b71bc-a560-4bf7-a524-3258b6167a11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13836840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_p
ulldown.13836840
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2661886334
Short name T246
Test name
Test status
Simulation time 1621991087 ps
CPU time 4.67 seconds
Started Jun 24 05:17:52 PM PDT 24
Finished Jun 24 05:17:58 PM PDT 24
Peak memory 197848 kb
Host smart-84daaaa3-ccc4-41e7-9310-626e17b7f946
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661886334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2661886334
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3162698555
Short name T495
Test name
Test status
Simulation time 238998722 ps
CPU time 1.35 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 196780 kb
Host smart-7dc22ddf-8c4b-45a8-b2f6-9b5e0ec50d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162698555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3162698555
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2403744039
Short name T326
Test name
Test status
Simulation time 103297026 ps
CPU time 1.12 seconds
Started Jun 24 05:17:42 PM PDT 24
Finished Jun 24 05:17:44 PM PDT 24
Peak memory 195756 kb
Host smart-048fa5c0-d79c-4246-ae18-abbc14fbe189
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403744039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2403744039
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.908273779
Short name T391
Test name
Test status
Simulation time 13170659879 ps
CPU time 41.75 seconds
Started Jun 24 05:17:51 PM PDT 24
Finished Jun 24 05:18:34 PM PDT 24
Peak memory 198136 kb
Host smart-b03146e2-c9dd-4518-a5fb-f55643d2908d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908273779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.908273779
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.854178284
Short name T922
Test name
Test status
Simulation time 86037606 ps
CPU time 1.31 seconds
Started Jun 24 06:02:29 PM PDT 24
Finished Jun 24 06:02:31 PM PDT 24
Peak memory 196720 kb
Host smart-8c65dbd9-d2a3-4d71-af97-0a705545b2f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=854178284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.854178284
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1813348336
Short name T920
Test name
Test status
Simulation time 79898635 ps
CPU time 0.77 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:33 PM PDT 24
Peak memory 195336 kb
Host smart-74f592e7-e97f-475b-89ca-633132d0800c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813348336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1813348336
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1160366519
Short name T889
Test name
Test status
Simulation time 91801497 ps
CPU time 1.49 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 196696 kb
Host smart-9cfa02e9-78b3-4b38-abeb-4efc63e9fa1d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1160366519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1160366519
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2426088179
Short name T900
Test name
Test status
Simulation time 264847609 ps
CPU time 1.23 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 197788 kb
Host smart-fd15c504-8b14-4827-9da2-ea42c58ae1e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426088179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2426088179
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3337290864
Short name T914
Test name
Test status
Simulation time 254115306 ps
CPU time 0.76 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 196004 kb
Host smart-da20e312-1f36-494b-bbc8-0f3e7ba3ee7d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3337290864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3337290864
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3485086293
Short name T868
Test name
Test status
Simulation time 222875886 ps
CPU time 0.82 seconds
Started Jun 24 06:02:29 PM PDT 24
Finished Jun 24 06:02:31 PM PDT 24
Peak memory 195984 kb
Host smart-ddfee97f-ddc7-4a5f-ad95-28b20f38a733
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485086293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3485086293
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3478129449
Short name T897
Test name
Test status
Simulation time 38153849 ps
CPU time 0.86 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 195420 kb
Host smart-12849764-6feb-46e1-95c3-0dbca45343d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3478129449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3478129449
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.358323114
Short name T893
Test name
Test status
Simulation time 48458563 ps
CPU time 1.21 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 196336 kb
Host smart-2e5395b8-0fbc-4a64-98cc-bc7cfc5cfb62
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358323114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.358323114
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3816722369
Short name T848
Test name
Test status
Simulation time 178628151 ps
CPU time 1.41 seconds
Started Jun 24 06:02:43 PM PDT 24
Finished Jun 24 06:02:48 PM PDT 24
Peak memory 196432 kb
Host smart-f9ef6d6c-4a46-415f-aefc-b62ecc036284
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3816722369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3816722369
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3954854085
Short name T869
Test name
Test status
Simulation time 285126291 ps
CPU time 1.47 seconds
Started Jun 24 06:02:43 PM PDT 24
Finished Jun 24 06:02:48 PM PDT 24
Peak memory 196692 kb
Host smart-d72a77aa-35d6-4269-bd5f-ad2d4d585973
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954854085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3954854085
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2164091135
Short name T894
Test name
Test status
Simulation time 106424622 ps
CPU time 1.08 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:46 PM PDT 24
Peak memory 196448 kb
Host smart-d889ad25-d4b7-42d6-aaa2-a6add2555a8d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2164091135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2164091135
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2981948147
Short name T918
Test name
Test status
Simulation time 113729922 ps
CPU time 0.96 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 197100 kb
Host smart-dd7b5a05-acea-41ca-aa69-3a1fc1e798fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981948147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2981948147
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4077578114
Short name T917
Test name
Test status
Simulation time 78999102 ps
CPU time 0.8 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 196004 kb
Host smart-2e5ccdb8-35d0-47e0-a262-036d6b191108
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4077578114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4077578114
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.899340391
Short name T901
Test name
Test status
Simulation time 70191596 ps
CPU time 1.12 seconds
Started Jun 24 06:02:43 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 197840 kb
Host smart-8f7d0e97-a4cc-436b-b8a3-4206d491d9c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899340391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.899340391
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4050282500
Short name T916
Test name
Test status
Simulation time 86749205 ps
CPU time 0.96 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 196244 kb
Host smart-e8149cca-5b7f-4768-9621-218a665a133c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4050282500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.4050282500
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.730104201
Short name T895
Test name
Test status
Simulation time 150356594 ps
CPU time 0.95 seconds
Started Jun 24 06:02:39 PM PDT 24
Finished Jun 24 06:02:41 PM PDT 24
Peak memory 196336 kb
Host smart-b8522cd6-531e-4b59-9b23-614e11b8013b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730104201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.730104201
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2289809942
Short name T862
Test name
Test status
Simulation time 466417535 ps
CPU time 1.24 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 196436 kb
Host smart-ebc4b604-f604-49c1-aea4-9a7d33a44523
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2289809942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2289809942
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2309934084
Short name T934
Test name
Test status
Simulation time 75942671 ps
CPU time 1.17 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 195440 kb
Host smart-3c1ef9cf-659f-41d8-8f4a-429d3fb77254
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309934084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2309934084
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2990717883
Short name T924
Test name
Test status
Simulation time 99379193 ps
CPU time 1.04 seconds
Started Jun 24 06:02:44 PM PDT 24
Finished Jun 24 06:02:48 PM PDT 24
Peak memory 196464 kb
Host smart-fb39ffe5-75ad-44d0-985d-f923fb0e2246
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2990717883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2990717883
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3989223496
Short name T937
Test name
Test status
Simulation time 60832550 ps
CPU time 1.34 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 197096 kb
Host smart-a0ff9b22-24a4-4cd7-87db-f52f4d6d3437
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989223496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3989223496
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.4285109315
Short name T875
Test name
Test status
Simulation time 125926695 ps
CPU time 1.19 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 197376 kb
Host smart-881b2c56-34ae-483a-bb22-f06066e4cb20
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4285109315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.4285109315
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2050230094
Short name T891
Test name
Test status
Simulation time 139264971 ps
CPU time 0.96 seconds
Started Jun 24 06:02:43 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 196336 kb
Host smart-de0036bd-5dd7-4761-b365-98286b431e88
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050230094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2050230094
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.20915184
Short name T854
Test name
Test status
Simulation time 347008489 ps
CPU time 1.42 seconds
Started Jun 24 06:02:44 PM PDT 24
Finished Jun 24 06:02:48 PM PDT 24
Peak memory 196536 kb
Host smart-3f040bb8-b998-4761-958d-4e967a94ffb0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=20915184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.20915184
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3847836071
Short name T921
Test name
Test status
Simulation time 94750248 ps
CPU time 0.96 seconds
Started Jun 24 06:02:40 PM PDT 24
Finished Jun 24 06:02:42 PM PDT 24
Peak memory 196232 kb
Host smart-71446013-173a-452c-b772-4e38bb57e290
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847836071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3847836071
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2262117900
Short name T863
Test name
Test status
Simulation time 51283411 ps
CPU time 1.08 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 196340 kb
Host smart-05a8fd26-f67b-4e7f-a610-3a9e010344b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2262117900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2262117900
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.438270587
Short name T940
Test name
Test status
Simulation time 184647163 ps
CPU time 1.28 seconds
Started Jun 24 06:02:33 PM PDT 24
Finished Jun 24 06:02:36 PM PDT 24
Peak memory 196376 kb
Host smart-db443c2c-d074-47ba-8dfb-1f8902a9183f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438270587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.438270587
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3012533836
Short name T910
Test name
Test status
Simulation time 378103685 ps
CPU time 1.52 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 196532 kb
Host smart-51dfc048-ce5f-4f57-872f-6bd9cff106e6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3012533836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3012533836
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1483071941
Short name T888
Test name
Test status
Simulation time 349842322 ps
CPU time 1.23 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 195460 kb
Host smart-69dc9a3b-52b1-4127-a801-1a72f8e3633d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483071941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1483071941
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.233871955
Short name T911
Test name
Test status
Simulation time 35547185 ps
CPU time 0.87 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:46 PM PDT 24
Peak memory 196136 kb
Host smart-1a4d29c3-97d3-4626-8e3d-e5ebf9877d51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=233871955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.233871955
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2146948936
Short name T878
Test name
Test status
Simulation time 49039580 ps
CPU time 0.9 seconds
Started Jun 24 06:02:43 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 197732 kb
Host smart-932a517e-fc0f-4a17-9ca5-a2843f100dc4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146948936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2146948936
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2968712771
Short name T853
Test name
Test status
Simulation time 837572232 ps
CPU time 1.41 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 196536 kb
Host smart-dc4cd755-04e6-420b-a696-8cd50e5f4074
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2968712771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2968712771
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3901527842
Short name T929
Test name
Test status
Simulation time 91565969 ps
CPU time 1.23 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:46 PM PDT 24
Peak memory 197816 kb
Host smart-51b6a35a-d519-4b25-83ae-3d5933634751
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901527842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3901527842
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.604501964
Short name T877
Test name
Test status
Simulation time 85029384 ps
CPU time 1.26 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 196784 kb
Host smart-d61e3a50-b592-4b03-8b64-52d6daa9efda
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=604501964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.604501964
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2211952697
Short name T935
Test name
Test status
Simulation time 56877620 ps
CPU time 1.12 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:46 PM PDT 24
Peak memory 195824 kb
Host smart-a818458e-4b3a-4ecf-85fa-748459fd4938
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211952697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2211952697
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3272225376
Short name T881
Test name
Test status
Simulation time 120689772 ps
CPU time 1.16 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 197836 kb
Host smart-f4a23f96-7541-40a8-b9e4-f1caef4292f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3272225376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3272225376
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2203848623
Short name T887
Test name
Test status
Simulation time 66393541 ps
CPU time 1.24 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 196472 kb
Host smart-66881ca7-9191-460b-89f7-e509f3a985fb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203848623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2203848623
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2922941209
Short name T930
Test name
Test status
Simulation time 146799693 ps
CPU time 0.98 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 196556 kb
Host smart-ed0192ef-3389-48ce-92d5-9483fbae0244
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2922941209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2922941209
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1607222815
Short name T845
Test name
Test status
Simulation time 54202121 ps
CPU time 0.83 seconds
Started Jun 24 06:02:40 PM PDT 24
Finished Jun 24 06:02:43 PM PDT 24
Peak memory 195828 kb
Host smart-056384b4-08c6-463e-bf50-8e7b2a74298f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607222815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1607222815
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3896803714
Short name T890
Test name
Test status
Simulation time 243813863 ps
CPU time 1.28 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 196312 kb
Host smart-54e13079-b724-4c56-8070-31235b529d70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3896803714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3896803714
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1617286128
Short name T873
Test name
Test status
Simulation time 109573714 ps
CPU time 1.33 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 196624 kb
Host smart-7cd372eb-6fb2-4ca1-9d9b-a5eec8ce1f79
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617286128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1617286128
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.707805358
Short name T884
Test name
Test status
Simulation time 79751174 ps
CPU time 0.75 seconds
Started Jun 24 06:02:44 PM PDT 24
Finished Jun 24 06:02:48 PM PDT 24
Peak memory 195284 kb
Host smart-c944ad9d-f997-4ea3-9da4-cb6af997cb65
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=707805358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.707805358
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4256653315
Short name T919
Test name
Test status
Simulation time 516174085 ps
CPU time 1.01 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 195960 kb
Host smart-9dad4505-9765-493b-bb00-2586412c4800
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256653315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4256653315
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3889951385
Short name T870
Test name
Test status
Simulation time 209101019 ps
CPU time 1.53 seconds
Started Jun 24 06:02:41 PM PDT 24
Finished Jun 24 06:02:44 PM PDT 24
Peak memory 197820 kb
Host smart-5c4414ee-60a0-4805-850b-6dd8acd3296c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3889951385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3889951385
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1175358041
Short name T874
Test name
Test status
Simulation time 225488116 ps
CPU time 0.93 seconds
Started Jun 24 06:02:44 PM PDT 24
Finished Jun 24 06:02:48 PM PDT 24
Peak memory 196300 kb
Host smart-b5e2e288-79f9-42ac-8125-256c1b725f04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175358041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1175358041
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2402002854
Short name T908
Test name
Test status
Simulation time 251080723 ps
CPU time 0.87 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 195304 kb
Host smart-ddc5e188-1824-467a-934f-fa875d8641e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2402002854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2402002854
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1948793473
Short name T912
Test name
Test status
Simulation time 185272958 ps
CPU time 1.36 seconds
Started Jun 24 06:02:43 PM PDT 24
Finished Jun 24 06:02:48 PM PDT 24
Peak memory 196372 kb
Host smart-96be428a-4a29-4f89-bc87-e1b517a0d308
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948793473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1948793473
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1906106004
Short name T864
Test name
Test status
Simulation time 86608774 ps
CPU time 0.85 seconds
Started Jun 24 06:02:30 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 196348 kb
Host smart-32f65857-fed7-4ab5-a4c2-b912ae9daa56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1906106004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1906106004
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983625338
Short name T866
Test name
Test status
Simulation time 87750138 ps
CPU time 1.49 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 196360 kb
Host smart-c1e5d5ff-87fc-4dcb-8295-02eda99fc4f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983625338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.983625338
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1634026002
Short name T876
Test name
Test status
Simulation time 223181284 ps
CPU time 1.23 seconds
Started Jun 24 06:02:43 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 196864 kb
Host smart-6bacbb31-c6a1-4543-b376-52f235d22271
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1634026002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1634026002
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2215260204
Short name T857
Test name
Test status
Simulation time 1861132484 ps
CPU time 1.4 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:46 PM PDT 24
Peak memory 196648 kb
Host smart-76400963-47f0-4fac-84cc-9b7e3c62eaad
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215260204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2215260204
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1168899691
Short name T886
Test name
Test status
Simulation time 80111883 ps
CPU time 0.91 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:45 PM PDT 24
Peak memory 195468 kb
Host smart-20e1b915-4810-4888-9b46-8fba86566968
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1168899691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1168899691
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2740111754
Short name T892
Test name
Test status
Simulation time 52244628 ps
CPU time 1 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:46 PM PDT 24
Peak memory 195736 kb
Host smart-f5b7e25a-506c-4e55-a268-92f86c0c6447
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740111754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2740111754
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.314656217
Short name T860
Test name
Test status
Simulation time 46468720 ps
CPU time 1.18 seconds
Started Jun 24 06:02:42 PM PDT 24
Finished Jun 24 06:02:47 PM PDT 24
Peak memory 197792 kb
Host smart-db787077-071a-4291-8b84-484d3a25ffbc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=314656217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.314656217
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2302824454
Short name T849
Test name
Test status
Simulation time 74945004 ps
CPU time 1.16 seconds
Started Jun 24 06:02:52 PM PDT 24
Finished Jun 24 06:02:54 PM PDT 24
Peak memory 196348 kb
Host smart-2bb40b69-d728-49c7-9a65-1fe1f582379a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302824454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2302824454
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1706251215
Short name T925
Test name
Test status
Simulation time 338736798 ps
CPU time 0.93 seconds
Started Jun 24 06:02:51 PM PDT 24
Finished Jun 24 06:02:53 PM PDT 24
Peak memory 197260 kb
Host smart-31fdddad-bd79-4d72-b35c-dad34b4c15c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1706251215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1706251215
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3702556882
Short name T855
Test name
Test status
Simulation time 150385000 ps
CPU time 1.06 seconds
Started Jun 24 06:02:57 PM PDT 24
Finished Jun 24 06:02:59 PM PDT 24
Peak memory 195484 kb
Host smart-17c67815-e63a-49fe-8be2-16dc3900f64b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702556882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3702556882
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2010476504
Short name T851
Test name
Test status
Simulation time 449501972 ps
CPU time 1.22 seconds
Started Jun 24 06:02:52 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 196416 kb
Host smart-da034112-16f1-4ab1-8108-e885b9e839ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2010476504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2010476504
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3205568880
Short name T867
Test name
Test status
Simulation time 56869830 ps
CPU time 1.19 seconds
Started Jun 24 06:02:49 PM PDT 24
Finished Jun 24 06:02:51 PM PDT 24
Peak memory 196272 kb
Host smart-c0383dc3-4b75-4199-8dfb-463dcca3ec63
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205568880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3205568880
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2099608772
Short name T915
Test name
Test status
Simulation time 185656261 ps
CPU time 0.89 seconds
Started Jun 24 06:02:52 PM PDT 24
Finished Jun 24 06:02:54 PM PDT 24
Peak memory 195388 kb
Host smart-61006b83-7d41-4418-ac89-a868d6c53b5e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2099608772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2099608772
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4021303922
Short name T846
Test name
Test status
Simulation time 1072304871 ps
CPU time 1.16 seconds
Started Jun 24 06:02:51 PM PDT 24
Finished Jun 24 06:02:53 PM PDT 24
Peak memory 197788 kb
Host smart-23cbc03a-fe2d-420d-8eb3-6b4e8c05a972
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021303922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4021303922
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3553301649
Short name T898
Test name
Test status
Simulation time 125850517 ps
CPU time 1.18 seconds
Started Jun 24 06:02:52 PM PDT 24
Finished Jun 24 06:02:54 PM PDT 24
Peak memory 196640 kb
Host smart-040f9be0-0fd4-4a96-8650-976272052be5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3553301649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3553301649
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1678079612
Short name T913
Test name
Test status
Simulation time 122040405 ps
CPU time 0.8 seconds
Started Jun 24 06:02:57 PM PDT 24
Finished Jun 24 06:02:58 PM PDT 24
Peak memory 195328 kb
Host smart-0880f125-de6e-4a07-b468-61740b33ea38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678079612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1678079612
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.967982746
Short name T926
Test name
Test status
Simulation time 36344878 ps
CPU time 0.99 seconds
Started Jun 24 06:02:52 PM PDT 24
Finished Jun 24 06:02:54 PM PDT 24
Peak memory 195672 kb
Host smart-e3bf1664-aa3b-43fd-b0ed-02fbe0917bf3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=967982746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.967982746
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3398172286
Short name T904
Test name
Test status
Simulation time 35133530 ps
CPU time 0.83 seconds
Started Jun 24 06:02:54 PM PDT 24
Finished Jun 24 06:02:56 PM PDT 24
Peak memory 195608 kb
Host smart-bf7abdec-9677-4160-8e48-29313b6e59f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398172286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3398172286
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1647925810
Short name T856
Test name
Test status
Simulation time 115810754 ps
CPU time 0.8 seconds
Started Jun 24 06:02:56 PM PDT 24
Finished Jun 24 06:02:58 PM PDT 24
Peak memory 196028 kb
Host smart-50959696-508f-4cfc-bcd9-7184bd38a0d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1647925810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1647925810
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2915475113
Short name T936
Test name
Test status
Simulation time 57708743 ps
CPU time 0.99 seconds
Started Jun 24 06:02:51 PM PDT 24
Finished Jun 24 06:02:53 PM PDT 24
Peak memory 195576 kb
Host smart-c3cc91a3-523c-4859-9f9a-57f13e5fb8f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915475113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2915475113
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4072489584
Short name T941
Test name
Test status
Simulation time 65174053 ps
CPU time 0.98 seconds
Started Jun 24 06:02:51 PM PDT 24
Finished Jun 24 06:02:53 PM PDT 24
Peak memory 195752 kb
Host smart-f9490c93-73fe-4df7-a80e-d9dd7cfd0eb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4072489584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.4072489584
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1527564510
Short name T859
Test name
Test status
Simulation time 80474640 ps
CPU time 1.36 seconds
Started Jun 24 06:02:53 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 196760 kb
Host smart-fdc447c5-5875-42aa-b9f7-06b48f466f7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527564510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1527564510
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1565881564
Short name T865
Test name
Test status
Simulation time 115686471 ps
CPU time 0.98 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 196248 kb
Host smart-00e6dc4d-1aa9-401d-b977-430a92487d3d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1565881564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1565881564
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2061761336
Short name T927
Test name
Test status
Simulation time 93704136 ps
CPU time 1.41 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:33 PM PDT 24
Peak memory 196488 kb
Host smart-0f71e511-24b8-4fbb-8edc-5b84506a722a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061761336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2061761336
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.730466144
Short name T943
Test name
Test status
Simulation time 70078711 ps
CPU time 1.23 seconds
Started Jun 24 06:02:50 PM PDT 24
Finished Jun 24 06:02:52 PM PDT 24
Peak memory 197824 kb
Host smart-79cfa7dd-8a4e-4c3e-b169-2e01a9285f41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=730466144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.730466144
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2320926857
Short name T907
Test name
Test status
Simulation time 57533663 ps
CPU time 0.96 seconds
Started Jun 24 06:02:53 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 195716 kb
Host smart-4ea6e408-21a9-4eb6-9bf3-f8e98db63b86
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320926857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2320926857
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3107678236
Short name T906
Test name
Test status
Simulation time 195700490 ps
CPU time 1.08 seconds
Started Jun 24 06:02:52 PM PDT 24
Finished Jun 24 06:02:54 PM PDT 24
Peak memory 196660 kb
Host smart-0b2acdb0-96b2-4a10-b568-ec935fff8df2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3107678236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3107678236
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.894653465
Short name T852
Test name
Test status
Simulation time 74786568 ps
CPU time 0.77 seconds
Started Jun 24 06:02:57 PM PDT 24
Finished Jun 24 06:02:58 PM PDT 24
Peak memory 195248 kb
Host smart-74d7e2f1-a6a7-4c1f-b39a-1803d5fbfad5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894653465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.894653465
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4042420186
Short name T933
Test name
Test status
Simulation time 197336698 ps
CPU time 1.04 seconds
Started Jun 24 06:02:54 PM PDT 24
Finished Jun 24 06:02:56 PM PDT 24
Peak memory 196352 kb
Host smart-496ee868-cb10-48f7-994b-37e88b058058
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4042420186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4042420186
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2574738747
Short name T928
Test name
Test status
Simulation time 29166073 ps
CPU time 0.73 seconds
Started Jun 24 06:02:50 PM PDT 24
Finished Jun 24 06:02:52 PM PDT 24
Peak memory 194192 kb
Host smart-dabed69b-260f-4f4f-8036-b3c4f6d4902d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574738747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2574738747
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.770749742
Short name T885
Test name
Test status
Simulation time 130157244 ps
CPU time 1.19 seconds
Started Jun 24 06:02:52 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 196180 kb
Host smart-a9bb6da7-46c2-4565-ac59-2000246d8fbf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=770749742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.770749742
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.735263849
Short name T879
Test name
Test status
Simulation time 32954382 ps
CPU time 1.06 seconds
Started Jun 24 06:02:57 PM PDT 24
Finished Jun 24 06:02:59 PM PDT 24
Peak memory 196252 kb
Host smart-ddf97d24-b4b4-4d39-bad9-f97968f93d58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735263849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.735263849
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4117712998
Short name T844
Test name
Test status
Simulation time 188527904 ps
CPU time 0.99 seconds
Started Jun 24 06:02:53 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 196308 kb
Host smart-78976056-db85-40c6-9a78-d072b84b5a6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4117712998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4117712998
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2846184533
Short name T938
Test name
Test status
Simulation time 31113928 ps
CPU time 0.95 seconds
Started Jun 24 06:02:50 PM PDT 24
Finished Jun 24 06:02:52 PM PDT 24
Peak memory 197784 kb
Host smart-aedd3bce-45a5-4861-b5db-4166b7d170f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846184533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2846184533
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1695025092
Short name T903
Test name
Test status
Simulation time 613722678 ps
CPU time 0.98 seconds
Started Jun 24 06:02:53 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 196264 kb
Host smart-82920616-823a-4774-a0b5-a73acde63d98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1695025092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1695025092
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1332437476
Short name T923
Test name
Test status
Simulation time 70730131 ps
CPU time 1.04 seconds
Started Jun 24 06:02:51 PM PDT 24
Finished Jun 24 06:02:53 PM PDT 24
Peak memory 195580 kb
Host smart-35ccb5fe-0953-408b-9c3b-7bf186144efb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332437476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1332437476
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1105529243
Short name T905
Test name
Test status
Simulation time 292172191 ps
CPU time 1.39 seconds
Started Jun 24 06:02:53 PM PDT 24
Finished Jun 24 06:02:55 PM PDT 24
Peak memory 195404 kb
Host smart-b14c75d3-01ea-4c2a-8d4e-462c3a482012
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1105529243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1105529243
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2986800685
Short name T847
Test name
Test status
Simulation time 38367457 ps
CPU time 0.94 seconds
Started Jun 24 06:02:54 PM PDT 24
Finished Jun 24 06:02:56 PM PDT 24
Peak memory 195928 kb
Host smart-49cb9c98-eb7f-403e-b93a-9f57efa60e3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986800685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2986800685
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2981255240
Short name T871
Test name
Test status
Simulation time 855248032 ps
CPU time 1.26 seconds
Started Jun 24 06:02:50 PM PDT 24
Finished Jun 24 06:02:52 PM PDT 24
Peak memory 197120 kb
Host smart-a8037c31-18c2-4665-bd4e-b560539c4abc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2981255240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2981255240
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2977500144
Short name T896
Test name
Test status
Simulation time 273828175 ps
CPU time 1.12 seconds
Started Jun 24 06:02:50 PM PDT 24
Finished Jun 24 06:02:52 PM PDT 24
Peak memory 196344 kb
Host smart-474a6ab1-4d83-4321-8890-9a839f002234
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977500144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2977500144
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4112481328
Short name T883
Test name
Test status
Simulation time 34648922 ps
CPU time 1.04 seconds
Started Jun 24 06:03:00 PM PDT 24
Finished Jun 24 06:03:02 PM PDT 24
Peak memory 196400 kb
Host smart-2ebfa969-a3a8-4e23-bfb6-33f743e9f8d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4112481328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4112481328
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2126436103
Short name T931
Test name
Test status
Simulation time 93208778 ps
CPU time 0.97 seconds
Started Jun 24 06:03:01 PM PDT 24
Finished Jun 24 06:03:03 PM PDT 24
Peak memory 195368 kb
Host smart-4a2c6813-e991-4105-9028-d026163f13fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126436103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2126436103
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3685144449
Short name T902
Test name
Test status
Simulation time 44640707 ps
CPU time 1.18 seconds
Started Jun 24 06:03:03 PM PDT 24
Finished Jun 24 06:03:05 PM PDT 24
Peak memory 196400 kb
Host smart-2209d6ee-691c-4a6b-83b2-5f4c3362e8a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3685144449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3685144449
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3392124
Short name T858
Test name
Test status
Simulation time 111948513 ps
CPU time 1.13 seconds
Started Jun 24 06:03:00 PM PDT 24
Finished Jun 24 06:03:01 PM PDT 24
Peak memory 196332 kb
Host smart-251f606f-5470-4f8a-896c-847d08cd0e4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.3392124
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3395647260
Short name T932
Test name
Test status
Simulation time 126216701 ps
CPU time 1.5 seconds
Started Jun 24 06:02:34 PM PDT 24
Finished Jun 24 06:02:37 PM PDT 24
Peak memory 197856 kb
Host smart-42c26a53-f845-4f1a-9fa4-2970a5d073eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3395647260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3395647260
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.686506011
Short name T880
Test name
Test status
Simulation time 305428080 ps
CPU time 1.42 seconds
Started Jun 24 06:02:34 PM PDT 24
Finished Jun 24 06:02:36 PM PDT 24
Peak memory 196660 kb
Host smart-1566ead5-404b-4d19-b488-7ce5d5132e8f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686506011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.686506011
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1875497545
Short name T909
Test name
Test status
Simulation time 72894555 ps
CPU time 0.91 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 196508 kb
Host smart-b8eeb9ee-edee-46e6-b991-9a2f0863afcc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1875497545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1875497545
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2170479011
Short name T861
Test name
Test status
Simulation time 44035402 ps
CPU time 1.31 seconds
Started Jun 24 06:02:30 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 196664 kb
Host smart-f16019b5-04f9-4291-b8a5-b1f45fd7240b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170479011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2170479011
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3334490812
Short name T942
Test name
Test status
Simulation time 119753795 ps
CPU time 0.9 seconds
Started Jun 24 06:02:37 PM PDT 24
Finished Jun 24 06:02:38 PM PDT 24
Peak memory 195416 kb
Host smart-c989b485-58b3-4f2d-afe2-511d2a74f190
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3334490812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3334490812
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1852977582
Short name T899
Test name
Test status
Simulation time 54413405 ps
CPU time 1.37 seconds
Started Jun 24 06:02:29 PM PDT 24
Finished Jun 24 06:02:32 PM PDT 24
Peak memory 196372 kb
Host smart-03c22470-7d05-4598-8c6f-2c53aa2a100f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852977582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1852977582
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2767407223
Short name T939
Test name
Test status
Simulation time 137769617 ps
CPU time 0.93 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:35 PM PDT 24
Peak memory 196444 kb
Host smart-07ec4bfe-24b6-49bc-95cd-70441a61e215
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2767407223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2767407223
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3643167907
Short name T850
Test name
Test status
Simulation time 277570475 ps
CPU time 0.77 seconds
Started Jun 24 06:02:32 PM PDT 24
Finished Jun 24 06:02:34 PM PDT 24
Peak memory 195108 kb
Host smart-3a74c14b-f134-47b0-8094-1e516747095d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643167907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3643167907
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.230308863
Short name T872
Test name
Test status
Simulation time 87276982 ps
CPU time 1.48 seconds
Started Jun 24 06:02:31 PM PDT 24
Finished Jun 24 06:02:33 PM PDT 24
Peak memory 196700 kb
Host smart-6764f7bb-1b9b-42ae-8a81-fc2d4681fb0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=230308863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.230308863
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.681916249
Short name T882
Test name
Test status
Simulation time 182448367 ps
CPU time 1.04 seconds
Started Jun 24 06:02:35 PM PDT 24
Finished Jun 24 06:02:37 PM PDT 24
Peak memory 196368 kb
Host smart-4d481df9-c853-4f98-a5b2-904e6026f84b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681916249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.681916249
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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