Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3794477	1			T20	1		T21	1		T1	27887
all_pins[1]	3794477	1			T20	1		T21	1		T1	27887
all_pins[2]	3794477	1			T20	1		T21	1		T1	27887
all_pins[3]	3794477	1			T20	1		T21	1		T1	27887
all_pins[4]	3794477	1			T20	1		T21	1		T1	27887
all_pins[5]	3794477	1			T20	1		T21	1		T1	27887
all_pins[6]	3794477	1			T20	1		T21	1		T1	27887
all_pins[7]	3794477	1			T20	1		T21	1		T1	27887
all_pins[8]	3794477	1			T20	1		T21	1		T1	27887
all_pins[9]	3794477	1			T20	1		T21	1		T1	27887
all_pins[10]	3794477	1			T20	1		T21	1		T1	27887
all_pins[11]	3794477	1			T20	1		T21	1		T1	27887
all_pins[12]	3794477	1			T20	1		T21	1		T1	27887
all_pins[13]	3794477	1			T20	1		T21	1		T1	27887
all_pins[14]	3794477	1			T20	1		T21	1		T1	27887
all_pins[15]	3794477	1			T20	1		T21	1		T1	27887
all_pins[16]	3794477	1			T20	1		T21	1		T1	27887
all_pins[17]	3794477	1			T20	1		T21	1		T1	27887
all_pins[18]	3794477	1			T20	1		T21	1		T1	27887
all_pins[19]	3794477	1			T20	1		T21	1		T1	27887
all_pins[20]	3794477	1			T20	1		T21	1		T1	27887
all_pins[21]	3794477	1			T20	1		T21	1		T1	27887
all_pins[22]	3794477	1			T20	1		T21	1		T1	27887
all_pins[23]	3794477	1			T20	1		T21	1		T1	27887
all_pins[24]	3794477	1			T20	1		T21	1		T1	27887
all_pins[25]	3794477	1			T20	1		T21	1		T1	27887
all_pins[26]	3794477	1			T20	1		T21	1		T1	27887
all_pins[27]	3794477	1			T20	1		T21	1		T1	27887
all_pins[28]	3794477	1			T20	1		T21	1		T1	27887
all_pins[29]	3794477	1			T20	1		T21	1		T1	27887
all_pins[30]	3794477	1			T20	1		T21	1		T1	27887
all_pins[31]	3794477	1			T20	1		T21	1		T1	27887

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	75407047	1			T20	32		T21	32		T1	549708
values[0x1]	46016217	1			T1	342676		T11	305		T13	524
transitions[0x0=>0x1]	27571264	1			T1	202960		T11	190		T13	340
transitions[0x1=>0x0]	27571114	1			T1	202959		T11	190		T13	340

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2355838	1			T20	1		T21	1		T1	17107
all_pins[0]	values[0x1]	1438639	1			T1	10780		T11	14		T13	20
all_pins[0]	transitions[0x0=>0x1]	893412	1			T1	6625		T11	9		T13	10
all_pins[0]	transitions[0x1=>0x0]	891352	1			T1	6437		T11	5		T13	15
all_pins[1]	values[0x0]	2354384	1			T20	1		T21	1		T1	17378
all_pins[1]	values[0x1]	1440093	1			T1	10509		T11	14		T13	10
all_pins[1]	transitions[0x0=>0x1]	859423	1			T1	6119		T11	7		T13	6
all_pins[1]	transitions[0x1=>0x0]	857969	1			T1	6390		T11	7		T13	16
all_pins[2]	values[0x0]	2354743	1			T20	1		T21	1		T1	17268
all_pins[2]	values[0x1]	1439734	1			T1	10619		T11	11		T13	20
all_pins[2]	transitions[0x0=>0x1]	859485	1			T1	6352		T11	4		T13	16
all_pins[2]	transitions[0x1=>0x0]	859844	1			T1	6242		T11	7		T13	6
all_pins[3]	values[0x0]	2353274	1			T20	1		T21	1		T1	16958
all_pins[3]	values[0x1]	1441203	1			T1	10929		T11	13		T13	12
all_pins[3]	transitions[0x0=>0x1]	862585	1			T1	6484		T11	10		T13	5
all_pins[3]	transitions[0x1=>0x0]	861116	1			T1	6174		T11	8		T13	13
all_pins[4]	values[0x0]	2352472	1			T20	1		T21	1		T1	17397
all_pins[4]	values[0x1]	1442005	1			T1	10490		T11	14		T13	22
all_pins[4]	transitions[0x0=>0x1]	861213	1			T1	6126		T11	9		T13	13
all_pins[4]	transitions[0x1=>0x0]	860411	1			T1	6565		T11	8		T13	3
all_pins[5]	values[0x0]	2356845	1			T20	1		T21	1		T1	17701
all_pins[5]	values[0x1]	1437632	1			T1	10186		T11	17		T13	9
all_pins[5]	transitions[0x0=>0x1]	858214	1			T1	6191		T11	9		T13	1
all_pins[5]	transitions[0x1=>0x0]	862587	1			T1	6495		T11	6		T13	14
all_pins[6]	values[0x0]	2356423	1			T20	1		T21	1		T1	17162
all_pins[6]	values[0x1]	1438054	1			T1	10725		T11	5		T13	17
all_pins[6]	transitions[0x0=>0x1]	861658	1			T1	6508		T11	2		T13	15
all_pins[6]	transitions[0x1=>0x0]	861236	1			T1	5969		T11	14		T13	7
all_pins[7]	values[0x0]	2358337	1			T20	1		T21	1		T1	16578
all_pins[7]	values[0x1]	1436140	1			T1	11309		T11	14		T13	8
all_pins[7]	transitions[0x0=>0x1]	859523	1			T1	6812		T11	11		T14	24412
all_pins[7]	transitions[0x1=>0x0]	861437	1			T1	6228		T11	2		T13	9
all_pins[8]	values[0x0]	2352535	1			T20	1		T21	1		T1	17038
all_pins[8]	values[0x1]	1441942	1			T1	10849		T11	4		T13	15
all_pins[8]	transitions[0x0=>0x1]	864342	1			T1	6138		T13	9		T14	26298
all_pins[8]	transitions[0x1=>0x0]	858540	1			T1	6598		T11	10		T13	2
all_pins[9]	values[0x0]	2353881	1			T20	1		T21	1		T1	17282
all_pins[9]	values[0x1]	1440596	1			T1	10605		T11	10		T13	30
all_pins[9]	transitions[0x0=>0x1]	859903	1			T1	6231		T11	6		T13	18
all_pins[9]	transitions[0x1=>0x0]	861249	1			T1	6475		T13	3		T14	25142
all_pins[10]	values[0x0]	2353737	1			T20	1		T21	1		T1	17124
all_pins[10]	values[0x1]	1440740	1			T1	10763		T11	6		T13	13
all_pins[10]	transitions[0x0=>0x1]	861658	1			T1	6343		T11	6		T13	3
all_pins[10]	transitions[0x1=>0x0]	861514	1			T1	6185		T11	10		T13	20
all_pins[11]	values[0x0]	2361753	1			T20	1		T21	1		T1	17101
all_pins[11]	values[0x1]	1432724	1			T1	10786		T11	12		T13	18
all_pins[11]	transitions[0x0=>0x1]	855688	1			T1	6275		T11	8		T13	15
all_pins[11]	transitions[0x1=>0x0]	863704	1			T1	6252		T11	2		T13	10
all_pins[12]	values[0x0]	2354428	1			T20	1		T21	1		T1	17262
all_pins[12]	values[0x1]	1440049	1			T1	10625		T11	3		T13	19
all_pins[12]	transitions[0x0=>0x1]	864528	1			T1	6152		T11	1		T13	11
all_pins[12]	transitions[0x1=>0x0]	857203	1			T1	6313		T11	10		T13	10
all_pins[13]	values[0x0]	2352677	1			T20	1		T21	1		T1	17169
all_pins[13]	values[0x1]	1441800	1			T1	10718		T11	8		T13	10
all_pins[13]	transitions[0x0=>0x1]	863031	1			T1	6400		T11	6		T13	8
all_pins[13]	transitions[0x1=>0x0]	861280	1			T1	6307		T11	1		T13	17
all_pins[14]	values[0x0]	2356234	1			T20	1		T21	1		T1	17469
all_pins[14]	values[0x1]	1438243	1			T1	10418		T11	8		T13	3
all_pins[14]	transitions[0x0=>0x1]	858724	1			T1	6182		T11	5		T14	25040
all_pins[14]	transitions[0x1=>0x0]	862281	1			T1	6482		T11	5		T13	7
all_pins[15]	values[0x0]	2356708	1			T20	1		T21	1		T1	17329
all_pins[15]	values[0x1]	1437769	1			T1	10558		T11	13		T13	30
all_pins[15]	transitions[0x0=>0x1]	858837	1			T1	6299		T11	9		T13	30
all_pins[15]	transitions[0x1=>0x0]	859311	1			T1	6159		T11	4		T13	3
all_pins[16]	values[0x0]	2358446	1			T20	1		T21	1		T1	17517
all_pins[16]	values[0x1]	1436031	1			T1	10370		T11	4		T13	19
all_pins[16]	transitions[0x0=>0x1]	861247	1			T1	6162		T11	3		T13	7
all_pins[16]	transitions[0x1=>0x0]	862985	1			T1	6350		T11	12		T13	18
all_pins[17]	values[0x0]	2355835	1			T20	1		T21	1		T1	17365
all_pins[17]	values[0x1]	1438642	1			T1	10522		T11	9		T13	2
all_pins[17]	transitions[0x0=>0x1]	860787	1			T1	6445		T11	6		T14	25603
all_pins[17]	transitions[0x1=>0x0]	858176	1			T1	6293		T11	1		T13	17
all_pins[18]	values[0x0]	2358297	1			T20	1		T21	1		T1	17424
all_pins[18]	values[0x1]	1436180	1			T1	10463		T11	3		T13	4
all_pins[18]	transitions[0x0=>0x1]	859631	1			T1	6182		T11	1		T13	4
all_pins[18]	transitions[0x1=>0x0]	862093	1			T1	6241		T11	7		T13	2
all_pins[19]	values[0x0]	2357181	1			T20	1		T21	1		T1	16933
all_pins[19]	values[0x1]	1437296	1			T1	10954		T11	15		T13	17
all_pins[19]	transitions[0x0=>0x1]	861165	1			T1	6489		T11	15		T13	15
all_pins[19]	transitions[0x1=>0x0]	860049	1			T1	5998		T11	3		T13	2
all_pins[20]	values[0x0]	2355609	1			T20	1		T21	1		T1	17111
all_pins[20]	values[0x1]	1438868	1			T1	10776		T11	4		T13	28
all_pins[20]	transitions[0x0=>0x1]	860188	1			T1	6338		T11	2		T13	21
all_pins[20]	transitions[0x1=>0x0]	858616	1			T1	6516		T11	13		T13	10
all_pins[21]	values[0x0]	2362282	1			T20	1		T21	1		T1	16760
all_pins[21]	values[0x1]	1432195	1			T1	11127		T11	5		T13	7
all_pins[21]	transitions[0x0=>0x1]	854991	1			T1	6524		T11	3		T13	3
all_pins[21]	transitions[0x1=>0x0]	861664	1			T1	6173		T11	2		T13	24
all_pins[22]	values[0x0]	2355483	1			T20	1		T21	1		T1	16817
all_pins[22]	values[0x1]	1438994	1			T1	11070		T11	5		T13	19
all_pins[22]	transitions[0x0=>0x1]	865420	1			T1	6421		T11	5		T13	16
all_pins[22]	transitions[0x1=>0x0]	858621	1			T1	6478		T11	5		T13	4
all_pins[23]	values[0x0]	2359304	1			T20	1		T21	1		T1	16964
all_pins[23]	values[0x1]	1435173	1			T1	10923		T11	12		T13	16
all_pins[23]	transitions[0x0=>0x1]	858719	1			T1	6460		T11	8		T13	11
all_pins[23]	transitions[0x1=>0x0]	862540	1			T1	6607		T11	1		T13	14
all_pins[24]	values[0x0]	2360407	1			T20	1		T21	1		T1	17486
all_pins[24]	values[0x1]	1434070	1			T1	10401		T11	8		T13	33
all_pins[24]	transitions[0x0=>0x1]	861518	1			T1	6209		T11	5		T13	23
all_pins[24]	transitions[0x1=>0x0]	862621	1			T1	6731		T11	9		T13	6
all_pins[25]	values[0x0]	2358390	1			T20	1		T21	1		T1	17091
all_pins[25]	values[0x1]	1436087	1			T1	10796		T11	13		T13	14
all_pins[25]	transitions[0x0=>0x1]	859356	1			T1	6587		T11	9		T13	7
all_pins[25]	transitions[0x1=>0x0]	857339	1			T1	6192		T11	4		T13	26
all_pins[26]	values[0x0]	2356060	1			T20	1		T21	1		T1	17233
all_pins[26]	values[0x1]	1438417	1			T1	10654		T11	14		T13	10
all_pins[26]	transitions[0x0=>0x1]	862260	1			T1	6232		T11	4		T13	7
all_pins[26]	transitions[0x1=>0x0]	859930	1			T1	6374		T11	3		T13	11
all_pins[27]	values[0x0]	2355399	1			T20	1		T21	1		T1	16874
all_pins[27]	values[0x1]	1439078	1			T1	11013		T11	4		T13	14
all_pins[27]	transitions[0x0=>0x1]	862309	1			T1	6490		T11	2		T13	10
all_pins[27]	transitions[0x1=>0x0]	861648	1			T1	6131		T11	12		T13	6
all_pins[28]	values[0x0]	2355730	1			T20	1		T21	1		T1	17112
all_pins[28]	values[0x1]	1438747	1			T1	10775		T11	7		T13	24
all_pins[28]	transitions[0x0=>0x1]	860365	1			T1	6314		T11	5		T13	15
all_pins[28]	transitions[0x1=>0x0]	860696	1			T1	6552		T11	2		T13	5
all_pins[29]	values[0x0]	2362082	1			T20	1		T21	1		T1	17476
all_pins[29]	values[0x1]	1432395	1			T1	10411		T11	8		T13	12
all_pins[29]	transitions[0x0=>0x1]	860073	1			T1	6059		T11	4		T13	6
all_pins[29]	transitions[0x1=>0x0]	866425	1			T1	6423		T11	3		T13	18
all_pins[30]	values[0x0]	2354525	1			T20	1		T21	1		T1	16928
all_pins[30]	values[0x1]	1439952	1			T1	10959		T11	18		T13	24
all_pins[30]	transitions[0x0=>0x1]	863617	1			T1	6604		T11	13		T13	22
all_pins[30]	transitions[0x1=>0x0]	856060	1			T1	6056		T11	3		T13	10
all_pins[31]	values[0x0]	2357748	1			T20	1		T21	1		T1	17294
all_pins[31]	values[0x1]	1436729	1			T1	10593		T11	10		T13	25
all_pins[31]	transitions[0x0=>0x1]	857394	1			T1	6207		T11	3		T13	13
all_pins[31]	transitions[0x1=>0x0]	860617	1			T1	6573		T11	11		T13	12