Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[1]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[2]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[3]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[4]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[5]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[6]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[7]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[8]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[9]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[10]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[11]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[12]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[13]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[14]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[15]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[16]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[17]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[18]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[19]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[20]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[21]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[22]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[23]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[24]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[25]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[26]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[27]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[28]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[29]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[30]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[31]	12835008	1			T20	951		T21	91		T1	94622

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244635479

1

T20

21699

T21

2297

T1

105269

auto[1]

166084777

1

T20

8733

T21

615

T1

197521

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331400371

1

T20

18010

T21

2695

T1

239099

auto[1]

79319885

1

T20

12422

T21

217

T1

636905

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308084389

1

T20

18232

T21

1857

T1

218628

auto[1]

102635867

1

T20

12200

T21

1055

T1

841617

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4815285	1			T20	283		T21	69		T1	21703
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3569629	1			T20	84		T21	18		T1	36585
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1246202	1			T20	232		T21	4		T1	10167
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1583020	1			T20	176		T1	1086		T11	26
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	384670	1			T1	15539		T11	23		T12	43
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1236202	1			T20	176		T1	9542		T11	6
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4814258	1			T20	279		T21	26		T1	21746
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3567161	1			T20	86		T21	8		T1	35930
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1248192	1			T20	226		T21	1		T1	10208
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1586364	1			T20	154		T21	40		T1	1201
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	384887	1			T21	14		T1	15658		T11	28
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1234146	1			T20	206		T21	2		T1	9879
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4796750	1			T20	292		T21	22		T1	21851
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3580118	1			T20	90		T21	5		T1	36422
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1245105	1			T20	182		T21	2		T1	9556
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1591190	1			T20	200		T21	41		T1	1157
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	384494	1			T21	11		T1	15263		T11	11
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1237351	1			T20	187		T21	10		T1	10373
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4809574	1			T20	247		T21	23		T1	21733
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3571404	1			T20	87		T21	5		T1	36161
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1246677	1			T20	197		T21	1		T1	9693
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1583374	1			T20	200		T21	45		T1	1110
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	385592	1			T21	3		T1	15706		T11	22
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1238387	1			T20	220		T21	14		T1	10219
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4809470	1			T20	299		T21	25		T1	21664
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3567350	1			T20	91		T21	6		T1	36851
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1247349	1			T20	218		T21	4		T1	10176
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1586138	1			T20	181		T21	44		T1	1057
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	384384	1			T21	10		T1	15400		T11	31
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1240317	1			T20	162		T21	2		T1	9474
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4818719	1			T20	277		T21	61		T1	21604
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3567214	1			T20	79		T21	18		T1	36551
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1246317	1			T20	164		T21	12		T1	10009
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1584040	1			T20	222		T1	1220		T11	42
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	383922	1			T1	15355		T11	6		T12	39
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1234796	1			T20	209		T1	9883		T12	7
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4814305	1			T20	283		T21	68		T1	21616
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3563811	1			T20	84		T21	13		T1	37053
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1245233	1			T20	224		T21	4		T1	9904
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1583842	1			T20	192		T21	6		T1	1190
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	385093	1			T1	15160		T11	25		T12	26
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1242724	1			T20	168		T1	9699		T11	14
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4811746	1			T20	256		T21	71		T1	21569
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3570005	1			T20	89		T21	17		T1	36926
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1247390	1			T20	218		T21	3		T1	10070
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1586423	1			T20	154		T1	1061		T11	41
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	386155	1			T1	15159		T11	20		T12	39
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1233289	1			T20	234		T1	9837		T11	40
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4827545	1			T20	283		T21	30		T1	21821
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3558721	1			T20	81		T21	3		T1	37036
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1243612	1			T20	223		T21	2		T1	9835
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1585997	1			T20	190		T21	45		T1	1051
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	385475	1			T21	11		T1	15523		T11	12
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1233658	1			T20	174		T1	9356		T11	37
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4802384	1			T20	310		T21	26		T1	21615
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3577685	1			T20	89		T21	5		T1	36652
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1245071	1			T20	184		T21	4		T1	10016
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1587417	1			T20	224		T21	50		T1	1177
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	384920	1			T21	6		T1	15426		T11	31
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1237531	1			T20	144		T1	9736		T11	12
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4798751	1			T20	272		T21	24		T1	21944
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3578590	1			T20	83		T21	4		T1	36565
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1245165	1			T20	172		T21	1		T1	10129
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1588510	1			T20	184		T21	39		T1	1095
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	384016	1			T21	11		T1	15332		T11	16
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1239976	1			T20	240		T21	12		T1	9557
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4814058	1			T20	281		T21	64		T1	21785
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3570060	1			T20	90		T21	19		T1	36845
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1247962	1			T20	204		T21	8		T1	10343
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1582960	1			T20	188		T1	1056		T11	72
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	383749	1			T1	14797		T11	17		T12	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1236219	1			T20	188		T1	9796		T11	9
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4818536	1			T20	243		T21	67		T1	21759
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3557384	1			T20	75		T21	18		T1	36796
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1245904	1			T20	202		T1	10240		T11	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1589157	1			T20	180		T21	6		T1	1060
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	384867	1			T1	15078		T11	14		T12	36
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1239160	1			T20	251		T1	9689		T11	10
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4809499	1			T20	302		T21	67		T1	21721
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3573909	1			T20	82		T21	12		T1	36525
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1245798	1			T20	215		T21	6		T1	10158
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1586623	1			T20	186		T21	4		T1	1200
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	382651	1			T1	15635		T11	39		T12	30
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1236528	1			T20	166		T21	2		T1	9383
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4804982	1			T20	290		T21	29		T1	21866
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3575823	1			T20	82		T21	3		T1	36692
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1248371	1			T20	155		T21	3		T1	9969
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1586164	1			T20	230		T21	35		T1	1055
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	382941	1			T21	15		T1	15116		T11	23
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1236727	1			T20	194		T21	6		T1	9924
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4808759	1			T20	284		T21	20		T1	21653
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3570134	1			T20	72		T21	8		T1	36509
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1248204	1			T20	188		T21	1		T1	10143
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1587929	1			T20	187		T21	46		T1	1132
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	384772	1			T21	10		T1	15346		T11	31
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1235210	1			T20	220		T21	6		T1	9839
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4811526	1			T20	291		T21	66		T1	21547
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3574512	1			T20	87		T21	14		T1	36493
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1239275	1			T20	226		T21	1		T1	10001
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1592785	1			T20	161		T21	8		T1	1211
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	386985	1			T1	15635		T11	27		T12	38
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1229925	1			T20	186		T21	2		T1	9735
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4813291	1			T20	260		T21	28		T1	21678
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3568997	1			T20	82		T21	7		T1	36518
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1241399	1			T20	198		T21	1		T1	9896
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1591562	1			T20	189		T21	40		T1	1163
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	387325	1			T21	13		T1	15389		T11	16
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1232434	1			T20	222		T21	2		T1	9978
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4813634	1			T20	269		T21	57		T1	21510
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3572807	1			T20	85		T21	20		T1	36551
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1244531	1			T20	174		T21	1		T1	10216
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1586375	1			T20	232		T21	13		T1	1153
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	385362	1			T1	15527		T11	37		T12	62
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1232299	1			T20	191		T1	9665		T11	11
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4815261	1			T20	274		T21	53		T1	21840
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3568533	1			T20	78		T21	9		T1	36441
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1242486	1			T20	200		T21	3		T1	9800
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1591525	1			T20	206		T21	23		T1	1136
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	385501	1			T21	3		T1	15301		T11	39
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1231702	1			T20	193		T1	10104		T11	12
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4809473	1			T20	296		T21	24		T1	21691
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3574132	1			T20	88		T21	4		T1	36597
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1247793	1			T20	200		T21	5		T1	9851
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1590463	1			T20	211		T21	40		T1	1087
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	385487	1			T21	10		T1	15759		T11	30
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1227660	1			T20	156		T21	8		T1	9637
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4811144	1			T20	314		T21	65		T1	21736
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3573192	1			T20	70		T21	9		T1	36525
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1243157	1			T20	183		T21	5		T1	9917
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1589545	1			T20	218		T21	8		T1	1093
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	386581	1			T21	4		T1	14924		T11	30
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1231389	1			T20	166		T1	10427		T11	12
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4805627	1			T20	273		T21	35		T1	21917
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3573139	1			T20	87		T21	7		T1	36276
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1243493	1			T20	200		T21	14		T1	10380
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1590115	1			T20	207		T21	27		T1	1139
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	385529	1			T21	6		T1	15041		T11	28
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1237105	1			T20	184		T21	2		T1	9869
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4817387	1			T20	259		T21	42		T1	21515
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3571045	1			T20	85		T21	11		T1	36632
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1241502	1			T20	200		T21	3		T1	10131
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1588930	1			T20	183		T21	29		T1	1147
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	384988	1			T21	6		T1	15387		T11	24
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1231156	1			T20	224		T1	9810		T11	14
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4820288	1			T20	245		T21	62		T1	21946
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3564310	1			T20	93		T21	12		T1	36633
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1239494	1			T20	201		T21	4		T1	9922
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1592865	1			T20	200		T21	7		T1	1100
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	385109	1			T1	15311		T11	21		T12	19
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1232942	1			T20	212		T21	6		T1	9710
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4808595	1			T20	279		T21	39		T1	21734
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3575923	1			T20	85		T21	10		T1	36573
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1240831	1			T20	215		T21	2		T1	9704
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1589928	1			T20	190		T21	30		T1	1135
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	386439	1			T21	8		T1	15387		T11	21
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1233292	1			T20	182		T21	2		T1	10089
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4808899	1			T20	305		T21	54		T1	21641
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3578103	1			T20	85		T21	16		T1	36464
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1239712	1			T20	210		T21	2		T1	10162
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1590434	1			T20	193		T21	17		T1	1124
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	387135	1			T21	2		T1	15311		T11	39
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1230725	1			T20	158		T1	9920		T11	10
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4822132	1			T20	317		T21	20		T1	21806
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3568290	1			T20	99		T21	7		T1	36064
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1244220	1			T20	192		T21	2		T1	10091
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1586977	1			T20	211		T21	38		T1	1094
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	383185	1			T21	14		T1	15360		T11	31
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1230204	1			T20	132		T21	10		T1	10207
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4813987	1			T20	282		T21	59		T1	21853
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3569019	1			T20	82		T21	10		T1	35946
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1245651	1			T20	203		T21	3		T1	9972
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1590442	1			T20	194		T21	16		T1	1179
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	384496	1			T21	1		T1	15670		T11	16
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1231413	1			T20	190		T21	2		T1	10002
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4813171	1			T20	304		T21	19		T1	21619
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3577824	1			T20	92		T21	10		T1	36475
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1243498	1			T20	224		T21	5		T1	10332
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1586125	1			T20	155		T21	45		T1	1197
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	383063	1			T21	8		T1	15085		T11	15
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1231327	1			T20	176		T21	4		T1	9914
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4819166	1			T20	362		T21	25		T1	21751
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3568577	1			T20	92		T21	8		T1	36654
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1243974	1			T20	182		T21	9		T1	10347
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1590547	1			T20	197		T21	36		T1	1121
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	384855	1			T21	9		T1	14548		T11	22
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1227889	1			T20	118		T21	4		T1	10201
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4815645	1			T20	296		T21	56		T1	21788
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3570434	1			T20	84		T21	26		T1	36724
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1239139	1			T20	195		T21	3		T1	10062
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1591159	1			T20	190		T21	4		T1	1083
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	385136	1			T1	14914		T11	17		T12	42
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1233495	1			T20	186		T21	2		T1	10051

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal