Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[1]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[2]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[3]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[4]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[5]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[6]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[7]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[8]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[9]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[10]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[11]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[12]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[13]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[14]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[15]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[16]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[17]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[18]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[19]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[20]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[21]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[22]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[23]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[24]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[25]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[26]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[27]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[28]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[29]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[30]	12835008	1			T20	951		T21	91		T1	94622
bins_for_gpio_bits[31]	12835008	1			T20	951		T21	91		T1	94622

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244635479

1

T20

21699

T21

2297

T1

105269

auto[1]

166084777

1

T20

8733

T21

615

T1

197521

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

244627024

1

T20

21694

T21

2297

T1

105287

auto[1]

166093232

1

T20

8738

T21

615

T1

197503

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7422981	1			T20	638		T21	73		T1	31179
bins_for_gpio_bits[0]	auto[0]	auto[1]	221265	1			T20	53		T1	1779		T12	4
bins_for_gpio_bits[0]	auto[1]	auto[0]	221526	1			T20	53		T1	1777		T12	4
bins_for_gpio_bits[0]	auto[1]	auto[1]	4969236	1			T20	207		T21	18		T1	59887
bins_for_gpio_bits[1]	auto[0]	auto[0]	7427173	1			T20	614		T21	66		T1	31428
bins_for_gpio_bits[1]	auto[0]	auto[1]	221403	1			T20	45		T21	1		T1	1733
bins_for_gpio_bits[1]	auto[1]	auto[0]	221641	1			T20	45		T21	1		T1	1727
bins_for_gpio_bits[1]	auto[1]	auto[1]	4964791	1			T20	247		T21	23		T1	59734
bins_for_gpio_bits[2]	auto[0]	auto[0]	7411579	1			T20	627		T21	64		T1	30823
bins_for_gpio_bits[2]	auto[0]	auto[1]	221179	1			T20	46		T21	1		T1	1748
bins_for_gpio_bits[2]	auto[1]	auto[0]	221466	1			T20	47		T21	1		T1	1741
bins_for_gpio_bits[2]	auto[1]	auto[1]	4980784	1			T20	231		T21	25		T1	60310
bins_for_gpio_bits[3]	auto[0]	auto[0]	7418026	1			T20	590		T21	67		T1	30820
bins_for_gpio_bits[3]	auto[0]	auto[1]	221368	1			T20	54		T21	2		T1	1721
bins_for_gpio_bits[3]	auto[1]	auto[0]	221599	1			T20	54		T21	2		T1	1716
bins_for_gpio_bits[3]	auto[1]	auto[1]	4974015	1			T20	253		T21	20		T1	60365
bins_for_gpio_bits[4]	auto[0]	auto[0]	7420796	1			T20	654		T21	72		T1	31130
bins_for_gpio_bits[4]	auto[0]	auto[1]	221915	1			T20	44		T21	1		T1	1771
bins_for_gpio_bits[4]	auto[1]	auto[0]	222161	1			T20	44		T21	1		T1	1767
bins_for_gpio_bits[4]	auto[1]	auto[1]	4970136	1			T20	209		T21	17		T1	59954
bins_for_gpio_bits[5]	auto[0]	auto[0]	7427507	1			T20	612		T21	73		T1	31093
bins_for_gpio_bits[5]	auto[0]	auto[1]	221306	1			T20	50		T1	1743		T12	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	221569	1			T20	51		T1	1740		T12	5
bins_for_gpio_bits[5]	auto[1]	auto[1]	4964626	1			T20	238		T21	18		T1	60046
bins_for_gpio_bits[6]	auto[0]	auto[0]	7421431	1			T20	654		T21	78		T1	30958
bins_for_gpio_bits[6]	auto[0]	auto[1]	221658	1			T20	45		T1	1756		T11	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	221949	1			T20	45		T1	1752		T11	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	4969970	1			T20	207		T21	13		T1	60156
bins_for_gpio_bits[7]	auto[0]	auto[0]	7424454	1			T20	570		T21	74		T1	30919
bins_for_gpio_bits[7]	auto[0]	auto[1]	220864	1			T20	58		T1	1789		T12	6
bins_for_gpio_bits[7]	auto[1]	auto[0]	221105	1			T20	58		T1	1781		T12	6
bins_for_gpio_bits[7]	auto[1]	auto[1]	4968585	1			T20	265		T21	17		T1	60133
bins_for_gpio_bits[8]	auto[0]	auto[0]	7435854	1			T20	645		T21	77		T1	30983
bins_for_gpio_bits[8]	auto[0]	auto[1]	221023	1			T20	51		T1	1735		T11	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	221300	1			T20	51		T1	1724		T11	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	4956831	1			T20	204		T21	14		T1	60180
bins_for_gpio_bits[9]	auto[0]	auto[0]	7413117	1			T20	675		T21	80		T1	31007
bins_for_gpio_bits[9]	auto[0]	auto[1]	221502	1			T20	43		T1	1809		T12	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	221755	1			T20	43		T1	1801		T12	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	4978634	1			T20	190		T21	11		T1	60005
bins_for_gpio_bits[10]	auto[0]	auto[0]	7410443	1			T20	576		T21	63		T1	31380
bins_for_gpio_bits[10]	auto[0]	auto[1]	221730	1			T20	52		T21	1		T1	1792
bins_for_gpio_bits[10]	auto[1]	auto[0]	221983	1			T20	52		T21	1		T1	1788
bins_for_gpio_bits[10]	auto[1]	auto[1]	4980852	1			T20	271		T21	26		T1	59662
bins_for_gpio_bits[11]	auto[0]	auto[0]	7423431	1			T20	626		T21	72		T1	31400
bins_for_gpio_bits[11]	auto[0]	auto[1]	221304	1			T20	47		T1	1791		T12	5
bins_for_gpio_bits[11]	auto[1]	auto[0]	221549	1			T20	47		T1	1784		T12	5
bins_for_gpio_bits[11]	auto[1]	auto[1]	4968724	1			T20	231		T21	19		T1	59647
bins_for_gpio_bits[12]	auto[0]	auto[0]	7431593	1			T20	576		T21	73		T1	31288
bins_for_gpio_bits[12]	auto[0]	auto[1]	221732	1			T20	48		T1	1773		T11	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	222004	1			T20	49		T1	1771		T12	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	4959679	1			T20	278		T21	18		T1	59790
bins_for_gpio_bits[13]	auto[0]	auto[0]	7420213	1			T20	662		T21	76		T1	31300
bins_for_gpio_bits[13]	auto[0]	auto[1]	221432	1			T20	41		T21	1		T1	1785
bins_for_gpio_bits[13]	auto[1]	auto[0]	221707	1			T20	41		T21	1		T1	1779
bins_for_gpio_bits[13]	auto[1]	auto[1]	4971656	1			T20	207		T21	13		T1	59758
bins_for_gpio_bits[14]	auto[0]	auto[0]	7417451	1			T20	624		T21	66		T1	31099
bins_for_gpio_bits[14]	auto[0]	auto[1]	221808	1			T20	51		T21	1		T1	1795
bins_for_gpio_bits[14]	auto[1]	auto[0]	222066	1			T20	51		T21	1		T1	1791
bins_for_gpio_bits[14]	auto[1]	auto[1]	4973683	1			T20	225		T21	23		T1	59937
bins_for_gpio_bits[15]	auto[0]	auto[0]	7423244	1			T20	607		T21	66		T1	31136
bins_for_gpio_bits[15]	auto[0]	auto[1]	221425	1			T20	52		T21	1		T1	1801
bins_for_gpio_bits[15]	auto[1]	auto[0]	221648	1			T20	52		T21	1		T1	1792
bins_for_gpio_bits[15]	auto[1]	auto[1]	4968691	1			T20	240		T21	23		T1	59893
bins_for_gpio_bits[16]	auto[0]	auto[0]	7422628	1			T20	631		T21	74		T1	30998
bins_for_gpio_bits[16]	auto[0]	auto[1]	220660	1			T20	47		T21	1		T1	1769
bins_for_gpio_bits[16]	auto[1]	auto[0]	220958	1			T20	47		T21	1		T1	1761
bins_for_gpio_bits[16]	auto[1]	auto[1]	4970762	1			T20	226		T21	15		T1	60094
bins_for_gpio_bits[17]	auto[0]	auto[0]	7424461	1			T20	595		T21	68		T1	30935
bins_for_gpio_bits[17]	auto[0]	auto[1]	221553	1			T20	52		T21	1		T1	1804
bins_for_gpio_bits[17]	auto[1]	auto[0]	221791	1			T20	52		T21	1		T1	1802
bins_for_gpio_bits[17]	auto[1]	auto[1]	4967203	1			T20	252		T21	21		T1	60081
bins_for_gpio_bits[18]	auto[0]	auto[0]	7422799	1			T20	624		T21	71		T1	31104
bins_for_gpio_bits[18]	auto[0]	auto[1]	221458	1			T20	50		T1	1780		T11	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	221741	1			T20	51		T1	1775		T11	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	4969010	1			T20	226		T21	20		T1	59963
bins_for_gpio_bits[19]	auto[0]	auto[0]	7427642	1			T20	630		T21	79		T1	31008
bins_for_gpio_bits[19]	auto[0]	auto[1]	221349	1			T20	49		T1	1774		T11	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	221630	1			T20	50		T1	1768		T14	6012
bins_for_gpio_bits[19]	auto[1]	auto[1]	4964387	1			T20	222		T21	12		T1	60072
bins_for_gpio_bits[20]	auto[0]	auto[0]	7426463	1			T20	663		T21	66		T1	30882
bins_for_gpio_bits[20]	auto[0]	auto[1]	220996	1			T20	44		T21	3		T1	1753
bins_for_gpio_bits[20]	auto[1]	auto[0]	221266	1			T20	44		T21	3		T1	1747
bins_for_gpio_bits[20]	auto[1]	auto[1]	4966283	1			T20	200		T21	19		T1	60240
bins_for_gpio_bits[21]	auto[0]	auto[0]	7422324	1			T20	668		T21	78		T1	30959
bins_for_gpio_bits[21]	auto[0]	auto[1]	221250	1			T20	47		T1	1794		T12	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	221522	1			T20	47		T1	1787		T12	1
bins_for_gpio_bits[21]	auto[1]	auto[1]	4969912	1			T20	189		T21	13		T1	60082
bins_for_gpio_bits[22]	auto[0]	auto[0]	7417095	1			T20	638		T21	75		T1	31614
bins_for_gpio_bits[22]	auto[0]	auto[1]	221866	1			T20	42		T21	1		T1	1828
bins_for_gpio_bits[22]	auto[1]	auto[0]	222140	1			T20	42		T21	1		T1	1822
bins_for_gpio_bits[22]	auto[1]	auto[1]	4973907	1			T20	229		T21	14		T1	59358
bins_for_gpio_bits[23]	auto[0]	auto[0]	7425794	1			T20	588		T21	74		T1	31012
bins_for_gpio_bits[23]	auto[0]	auto[1]	221738	1			T20	54		T1	1783		T12	4
bins_for_gpio_bits[23]	auto[1]	auto[0]	222025	1			T20	54		T1	1781		T12	4
bins_for_gpio_bits[23]	auto[1]	auto[1]	4965451	1			T20	255		T21	17		T1	60046
bins_for_gpio_bits[24]	auto[0]	auto[0]	7430902	1			T20	594		T21	72		T1	31221
bins_for_gpio_bits[24]	auto[0]	auto[1]	221471	1			T20	52		T21	1		T1	1753
bins_for_gpio_bits[24]	auto[1]	auto[0]	221745	1			T20	52		T21	1		T1	1747
bins_for_gpio_bits[24]	auto[1]	auto[1]	4960890	1			T20	253		T21	17		T1	59901
bins_for_gpio_bits[25]	auto[0]	auto[0]	7417556	1			T20	634		T21	70		T1	30828
bins_for_gpio_bits[25]	auto[0]	auto[1]	221514	1			T20	50		T21	1		T1	1753
bins_for_gpio_bits[25]	auto[1]	auto[0]	221798	1			T20	50		T21	1		T1	1745
bins_for_gpio_bits[25]	auto[1]	auto[1]	4974140	1			T20	217		T21	19		T1	60296
bins_for_gpio_bits[26]	auto[0]	auto[0]	7417419	1			T20	666		T21	73		T1	31187
bins_for_gpio_bits[26]	auto[0]	auto[1]	221360	1			T20	42		T1	1744		T12	4
bins_for_gpio_bits[26]	auto[1]	auto[0]	221626	1			T20	42		T1	1740		T12	4
bins_for_gpio_bits[26]	auto[1]	auto[1]	4974603	1			T20	201		T21	18		T1	59951
bins_for_gpio_bits[27]	auto[0]	auto[0]	7431926	1			T20	681		T21	58		T1	31219
bins_for_gpio_bits[27]	auto[0]	auto[1]	221109	1			T20	39		T21	2		T1	1778
bins_for_gpio_bits[27]	auto[1]	auto[0]	221403	1			T20	39		T21	2		T1	1772
bins_for_gpio_bits[27]	auto[1]	auto[1]	4960570	1			T20	192		T21	29		T1	59853
bins_for_gpio_bits[28]	auto[0]	auto[0]	7428479	1			T20	628		T21	77		T1	31242
bins_for_gpio_bits[28]	auto[0]	auto[1]	221361	1			T20	51		T21	1		T1	1767
bins_for_gpio_bits[28]	auto[1]	auto[0]	221601	1			T20	51		T21	1		T1	1762
bins_for_gpio_bits[28]	auto[1]	auto[1]	4963567	1			T20	221		T21	12		T1	59851
bins_for_gpio_bits[29]	auto[0]	auto[0]	7421132	1			T20	638		T21	67		T1	31302
bins_for_gpio_bits[29]	auto[0]	auto[1]	221391	1			T20	45		T21	2		T1	1856
bins_for_gpio_bits[29]	auto[1]	auto[0]	221662	1			T20	45		T21	2		T1	1846
bins_for_gpio_bits[29]	auto[1]	auto[1]	4970823	1			T20	223		T21	20		T1	59618
bins_for_gpio_bits[30]	auto[0]	auto[0]	7432520	1			T20	704		T21	68		T1	31456
bins_for_gpio_bits[30]	auto[0]	auto[1]	220937	1			T20	37		T21	2		T1	1771
bins_for_gpio_bits[30]	auto[1]	auto[0]	221167	1			T20	37		T21	2		T1	1763
bins_for_gpio_bits[30]	auto[1]	auto[1]	4960384	1			T20	173		T21	19		T1	59632
bins_for_gpio_bits[31]	auto[0]	auto[0]	7423543	1			T20	632		T21	62		T1	31131
bins_for_gpio_bits[31]	auto[0]	auto[1]	222121	1			T20	49		T21	1		T1	1804
bins_for_gpio_bits[31]	auto[1]	auto[0]	222400	1			T20	49		T21	1		T1	1802
bins_for_gpio_bits[31]	auto[1]	auto[1]	4966944	1			T20	221		T21	27		T1	59885