Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7664002 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51800 |
| auto[1] |
5361399 |
1 |
|
|
T1 |
43993 |
|
T11 |
43 |
|
T13 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12341260 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90219 |
| auto[1] |
684141 |
1 |
|
|
T1 |
5574 |
|
T11 |
1 |
|
T13 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7659608 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53868 |
| auto[1] |
5365793 |
1 |
|
|
T1 |
41925 |
|
T11 |
10 |
|
T13 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2352616 |
1 |
|
|
T1 |
18311 |
|
T11 |
9 |
|
T13 |
17 |
| auto[1] |
auto[0] |
auto[1] |
344341 |
1 |
|
|
T1 |
2801 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2329036 |
1 |
|
|
T1 |
18040 |
|
T13 |
24 |
|
T14 |
70556 |
| auto[1] |
auto[1] |
auto[1] |
339800 |
1 |
|
|
T1 |
2773 |
|
T13 |
1 |
|
T14 |
10548 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7648993 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52886 |
| auto[1] |
5376408 |
1 |
|
|
T1 |
42907 |
|
T11 |
34 |
|
T13 |
29 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12342754 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
89896 |
| auto[1] |
682647 |
1 |
|
|
T1 |
5897 |
|
T11 |
2 |
|
T13 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7676536 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52367 |
| auto[1] |
5348865 |
1 |
|
|
T1 |
43426 |
|
T11 |
42 |
|
T13 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2336018 |
1 |
|
|
T1 |
18799 |
|
T11 |
16 |
|
T13 |
18 |
| auto[1] |
auto[0] |
auto[1] |
341875 |
1 |
|
|
T1 |
2948 |
|
T11 |
2 |
|
T13 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2330200 |
1 |
|
|
T1 |
18730 |
|
T11 |
24 |
|
T13 |
13 |
| auto[1] |
auto[1] |
auto[1] |
340772 |
1 |
|
|
T1 |
2949 |
|
T14 |
10435 |
|
T16 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7655196 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53227 |
| auto[1] |
5370205 |
1 |
|
|
T1 |
42566 |
|
T11 |
25 |
|
T13 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12342765 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90143 |
| auto[1] |
682636 |
1 |
|
|
T1 |
5650 |
|
T13 |
1 |
|
T14 |
20584 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7674982 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53023 |
| auto[1] |
5350419 |
1 |
|
|
T1 |
42770 |
|
T11 |
22 |
|
T13 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2328485 |
1 |
|
|
T1 |
19499 |
|
T11 |
18 |
|
T13 |
19 |
| auto[1] |
auto[0] |
auto[1] |
339425 |
1 |
|
|
T1 |
2976 |
|
T14 |
10294 |
|
T16 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2339298 |
1 |
|
|
T1 |
17621 |
|
T11 |
4 |
|
T13 |
16 |
| auto[1] |
auto[1] |
auto[1] |
343211 |
1 |
|
|
T1 |
2674 |
|
T13 |
1 |
|
T14 |
10290 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7707082 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53398 |
| auto[1] |
5318319 |
1 |
|
|
T1 |
42395 |
|
T11 |
51 |
|
T13 |
30 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12340180 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
89901 |
| auto[1] |
685221 |
1 |
|
|
T1 |
5892 |
|
T13 |
1 |
|
T14 |
19985 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7659981 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51137 |
| auto[1] |
5365420 |
1 |
|
|
T1 |
44656 |
|
T11 |
29 |
|
T13 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2362017 |
1 |
|
|
T1 |
19919 |
|
T11 |
13 |
|
T13 |
17 |
| auto[1] |
auto[0] |
auto[1] |
346235 |
1 |
|
|
T1 |
3013 |
|
T14 |
10100 |
|
T16 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2318182 |
1 |
|
|
T1 |
18845 |
|
T11 |
16 |
|
T13 |
6 |
| auto[1] |
auto[1] |
auto[1] |
338986 |
1 |
|
|
T1 |
2879 |
|
T13 |
1 |
|
T14 |
9885 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7634598 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53364 |
| auto[1] |
5390803 |
1 |
|
|
T1 |
42429 |
|
T11 |
6 |
|
T13 |
57 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12342598 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90257 |
| auto[1] |
682803 |
1 |
|
|
T1 |
5536 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7672858 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54390 |
| auto[1] |
5352543 |
1 |
|
|
T1 |
41403 |
|
T11 |
18 |
|
T13 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2318035 |
1 |
|
|
T1 |
17713 |
|
T11 |
17 |
|
T13 |
18 |
| auto[1] |
auto[0] |
auto[1] |
338430 |
1 |
|
|
T1 |
2606 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2351705 |
1 |
|
|
T1 |
18154 |
|
T13 |
20 |
|
T14 |
65127 |
| auto[1] |
auto[1] |
auto[1] |
344373 |
1 |
|
|
T1 |
2930 |
|
T14 |
9373 |
|
T16 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7642645 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53299 |
| auto[1] |
5382756 |
1 |
|
|
T1 |
42494 |
|
T11 |
30 |
|
T13 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12343974 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90193 |
| auto[1] |
681427 |
1 |
|
|
T1 |
5600 |
|
T11 |
2 |
|
T13 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7674392 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53801 |
| auto[1] |
5351009 |
1 |
|
|
T1 |
41992 |
|
T11 |
40 |
|
T13 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2322495 |
1 |
|
|
T1 |
18092 |
|
T11 |
14 |
|
T13 |
13 |
| auto[1] |
auto[0] |
auto[1] |
338091 |
1 |
|
|
T1 |
2855 |
|
T13 |
1 |
|
T14 |
9597 |
| auto[1] |
auto[1] |
auto[0] |
2347087 |
1 |
|
|
T1 |
18300 |
|
T11 |
24 |
|
T13 |
23 |
| auto[1] |
auto[1] |
auto[1] |
343336 |
1 |
|
|
T1 |
2745 |
|
T11 |
2 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7631748 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
55607 |
| auto[1] |
5393653 |
1 |
|
|
T1 |
40186 |
|
T11 |
13 |
|
T13 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12340055 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90164 |
| auto[1] |
685346 |
1 |
|
|
T1 |
5629 |
|
T11 |
1 |
|
T14 |
21100 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7653080 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54366 |
| auto[1] |
5372321 |
1 |
|
|
T1 |
41427 |
|
T11 |
51 |
|
T13 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2338534 |
1 |
|
|
T1 |
19540 |
|
T11 |
50 |
|
T13 |
25 |
| auto[1] |
auto[0] |
auto[1] |
340622 |
1 |
|
|
T1 |
3110 |
|
T11 |
1 |
|
T14 |
10411 |
| auto[1] |
auto[1] |
auto[0] |
2348441 |
1 |
|
|
T1 |
16258 |
|
T14 |
70878 |
|
T16 |
62 |
| auto[1] |
auto[1] |
auto[1] |
344724 |
1 |
|
|
T1 |
2519 |
|
T14 |
10689 |
|
T16 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7631253 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53161 |
| auto[1] |
5394148 |
1 |
|
|
T1 |
42632 |
|
T11 |
35 |
|
T13 |
59 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12338438 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90242 |
| auto[1] |
686963 |
1 |
|
|
T1 |
5551 |
|
T11 |
3 |
|
T14 |
19764 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7642976 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54422 |
| auto[1] |
5382425 |
1 |
|
|
T1 |
41371 |
|
T11 |
54 |
|
T13 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2332492 |
1 |
|
|
T1 |
18010 |
|
T11 |
31 |
|
T13 |
8 |
| auto[1] |
auto[0] |
auto[1] |
340658 |
1 |
|
|
T1 |
2772 |
|
T11 |
2 |
|
T14 |
9217 |
| auto[1] |
auto[1] |
auto[0] |
2362970 |
1 |
|
|
T1 |
17810 |
|
T11 |
20 |
|
T13 |
19 |
| auto[1] |
auto[1] |
auto[1] |
346305 |
1 |
|
|
T1 |
2779 |
|
T11 |
1 |
|
T14 |
10547 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7682134 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53426 |
| auto[1] |
5343267 |
1 |
|
|
T1 |
42367 |
|
T11 |
20 |
|
T13 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12339633 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90276 |
| auto[1] |
685768 |
1 |
|
|
T1 |
5517 |
|
T11 |
1 |
|
T14 |
20121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7652936 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54360 |
| auto[1] |
5372465 |
1 |
|
|
T1 |
41433 |
|
T11 |
42 |
|
T13 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2350919 |
1 |
|
|
T1 |
17022 |
|
T11 |
34 |
|
T13 |
13 |
| auto[1] |
auto[0] |
auto[1] |
344530 |
1 |
|
|
T1 |
2709 |
|
T11 |
1 |
|
T14 |
10203 |
| auto[1] |
auto[1] |
auto[0] |
2335778 |
1 |
|
|
T1 |
18894 |
|
T11 |
7 |
|
T13 |
17 |
| auto[1] |
auto[1] |
auto[1] |
341238 |
1 |
|
|
T1 |
2808 |
|
T14 |
9918 |
|
T16 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7654640 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
55030 |
| auto[1] |
5370761 |
1 |
|
|
T1 |
40763 |
|
T11 |
32 |
|
T13 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12344829 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90280 |
| auto[1] |
680572 |
1 |
|
|
T1 |
5513 |
|
T11 |
1 |
|
T14 |
20489 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7680600 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54389 |
| auto[1] |
5344801 |
1 |
|
|
T1 |
41404 |
|
T11 |
22 |
|
T13 |
33 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2329623 |
1 |
|
|
T1 |
17833 |
|
T11 |
20 |
|
T13 |
33 |
| auto[1] |
auto[0] |
auto[1] |
339222 |
1 |
|
|
T1 |
2778 |
|
T11 |
1 |
|
T14 |
10021 |
| auto[1] |
auto[1] |
auto[0] |
2334606 |
1 |
|
|
T1 |
18058 |
|
T11 |
1 |
|
T14 |
70294 |
| auto[1] |
auto[1] |
auto[1] |
341350 |
1 |
|
|
T1 |
2735 |
|
T14 |
10468 |
|
T16 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7645353 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54305 |
| auto[1] |
5380048 |
1 |
|
|
T1 |
41488 |
|
T11 |
6 |
|
T13 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12344104 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
89888 |
| auto[1] |
681297 |
1 |
|
|
T1 |
5905 |
|
T11 |
3 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7671413 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51797 |
| auto[1] |
5353988 |
1 |
|
|
T1 |
43996 |
|
T11 |
36 |
|
T13 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2328852 |
1 |
|
|
T1 |
19405 |
|
T11 |
33 |
|
T13 |
36 |
| auto[1] |
auto[0] |
auto[1] |
339685 |
1 |
|
|
T1 |
3036 |
|
T11 |
3 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2343839 |
1 |
|
|
T1 |
18686 |
|
T13 |
8 |
|
T14 |
67594 |
| auto[1] |
auto[1] |
auto[1] |
341612 |
1 |
|
|
T1 |
2869 |
|
T14 |
9953 |
|
T16 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7671153 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52529 |
| auto[1] |
5354248 |
1 |
|
|
T1 |
43264 |
|
T11 |
45 |
|
T13 |
36 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12344984 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90133 |
| auto[1] |
680417 |
1 |
|
|
T1 |
5660 |
|
T14 |
19805 |
|
T16 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7690494 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53038 |
| auto[1] |
5334907 |
1 |
|
|
T1 |
42755 |
|
T11 |
18 |
|
T13 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2339189 |
1 |
|
|
T1 |
18514 |
|
T11 |
4 |
|
T13 |
14 |
| auto[1] |
auto[0] |
auto[1] |
342654 |
1 |
|
|
T1 |
2832 |
|
T14 |
10143 |
|
T16 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2315301 |
1 |
|
|
T1 |
18581 |
|
T11 |
14 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[1] |
337763 |
1 |
|
|
T1 |
2828 |
|
T14 |
9662 |
|
T16 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7638642 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51703 |
| auto[1] |
5386759 |
1 |
|
|
T1 |
44090 |
|
T11 |
33 |
|
T13 |
66 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12341018 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90069 |
| auto[1] |
684383 |
1 |
|
|
T1 |
5724 |
|
T11 |
3 |
|
T13 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7669489 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52855 |
| auto[1] |
5355912 |
1 |
|
|
T1 |
42938 |
|
T11 |
55 |
|
T13 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2323564 |
1 |
|
|
T1 |
17612 |
|
T11 |
34 |
|
T14 |
68950 |
| auto[1] |
auto[0] |
auto[1] |
340401 |
1 |
|
|
T1 |
2661 |
|
T11 |
3 |
|
T14 |
10239 |
| auto[1] |
auto[1] |
auto[0] |
2347965 |
1 |
|
|
T1 |
19602 |
|
T11 |
18 |
|
T13 |
35 |
| auto[1] |
auto[1] |
auto[1] |
343982 |
1 |
|
|
T1 |
3063 |
|
T13 |
3 |
|
T14 |
9975 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7671082 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53641 |
| auto[1] |
5354319 |
1 |
|
|
T1 |
42152 |
|
T11 |
25 |
|
T13 |
76 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12344634 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90309 |
| auto[1] |
680767 |
1 |
|
|
T1 |
5484 |
|
T13 |
2 |
|
T14 |
20074 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7677154 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53926 |
| auto[1] |
5348247 |
1 |
|
|
T1 |
41867 |
|
T11 |
18 |
|
T13 |
23 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2336553 |
1 |
|
|
T1 |
18701 |
|
T11 |
15 |
|
T13 |
4 |
| auto[1] |
auto[0] |
auto[1] |
340974 |
1 |
|
|
T1 |
2816 |
|
T13 |
1 |
|
T14 |
9527 |
| auto[1] |
auto[1] |
auto[0] |
2330927 |
1 |
|
|
T1 |
17682 |
|
T11 |
3 |
|
T13 |
17 |
| auto[1] |
auto[1] |
auto[1] |
339793 |
1 |
|
|
T1 |
2668 |
|
T13 |
1 |
|
T14 |
10547 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7658470 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51782 |
| auto[1] |
5366931 |
1 |
|
|
T1 |
44011 |
|
T11 |
21 |
|
T13 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12342288 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
89810 |
| auto[1] |
683113 |
1 |
|
|
T1 |
5983 |
|
T11 |
4 |
|
T13 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7672744 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52773 |
| auto[1] |
5352657 |
1 |
|
|
T1 |
43020 |
|
T11 |
49 |
|
T13 |
27 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2323625 |
1 |
|
|
T1 |
18064 |
|
T11 |
37 |
|
T13 |
12 |
| auto[1] |
auto[0] |
auto[1] |
339706 |
1 |
|
|
T1 |
2844 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2345919 |
1 |
|
|
T1 |
18973 |
|
T11 |
8 |
|
T13 |
13 |
| auto[1] |
auto[1] |
auto[1] |
343407 |
1 |
|
|
T1 |
3139 |
|
T11 |
2 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7666451 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53611 |
| auto[1] |
5358950 |
1 |
|
|
T1 |
42182 |
|
T11 |
22 |
|
T13 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12342275 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90185 |
| auto[1] |
683126 |
1 |
|
|
T1 |
5608 |
|
T11 |
2 |
|
T14 |
21272 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7675550 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53796 |
| auto[1] |
5349851 |
1 |
|
|
T1 |
41997 |
|
T11 |
44 |
|
T13 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2328396 |
1 |
|
|
T1 |
18276 |
|
T11 |
27 |
|
T13 |
22 |
| auto[1] |
auto[0] |
auto[1] |
339965 |
1 |
|
|
T1 |
2849 |
|
T11 |
2 |
|
T14 |
10418 |
| auto[1] |
auto[1] |
auto[0] |
2338329 |
1 |
|
|
T1 |
18113 |
|
T11 |
15 |
|
T13 |
8 |
| auto[1] |
auto[1] |
auto[1] |
343161 |
1 |
|
|
T1 |
2759 |
|
T14 |
10854 |
|
T16 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7649125 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52890 |
| auto[1] |
5376276 |
1 |
|
|
T1 |
42903 |
|
T11 |
28 |
|
T13 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12344791 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
89949 |
| auto[1] |
680610 |
1 |
|
|
T1 |
5844 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7691689 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52895 |
| auto[1] |
5333712 |
1 |
|
|
T1 |
42898 |
|
T11 |
47 |
|
T13 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2319862 |
1 |
|
|
T1 |
17684 |
|
T11 |
34 |
|
T13 |
20 |
| auto[1] |
auto[0] |
auto[1] |
340042 |
1 |
|
|
T1 |
2851 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2333240 |
1 |
|
|
T1 |
19370 |
|
T11 |
11 |
|
T13 |
4 |
| auto[1] |
auto[1] |
auto[1] |
340568 |
1 |
|
|
T1 |
2993 |
|
T11 |
1 |
|
T14 |
10379 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7667592 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52611 |
| auto[1] |
5357809 |
1 |
|
|
T1 |
43182 |
|
T11 |
19 |
|
T13 |
66 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12342233 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90362 |
| auto[1] |
683168 |
1 |
|
|
T1 |
5431 |
|
T11 |
2 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7669329 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54243 |
| auto[1] |
5356072 |
1 |
|
|
T1 |
41550 |
|
T11 |
29 |
|
T13 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2336915 |
1 |
|
|
T1 |
18396 |
|
T11 |
22 |
|
T13 |
4 |
| auto[1] |
auto[0] |
auto[1] |
341624 |
1 |
|
|
T1 |
2716 |
|
T11 |
2 |
|
T14 |
10023 |
| auto[1] |
auto[1] |
auto[0] |
2335989 |
1 |
|
|
T1 |
17723 |
|
T11 |
5 |
|
T13 |
6 |
| auto[1] |
auto[1] |
auto[1] |
341544 |
1 |
|
|
T1 |
2715 |
|
T13 |
1 |
|
T14 |
9114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7655706 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52910 |
| auto[1] |
5369695 |
1 |
|
|
T1 |
42883 |
|
T11 |
32 |
|
T13 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12339528 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90083 |
| auto[1] |
685873 |
1 |
|
|
T1 |
5710 |
|
T11 |
1 |
|
T14 |
20547 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7649307 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53092 |
| auto[1] |
5376094 |
1 |
|
|
T1 |
42701 |
|
T11 |
16 |
|
T13 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2349044 |
1 |
|
|
T1 |
17554 |
|
T11 |
15 |
|
T13 |
5 |
| auto[1] |
auto[0] |
auto[1] |
343363 |
1 |
|
|
T1 |
2652 |
|
T11 |
1 |
|
T14 |
10706 |
| auto[1] |
auto[1] |
auto[0] |
2341177 |
1 |
|
|
T1 |
19437 |
|
T13 |
4 |
|
T14 |
68644 |
| auto[1] |
auto[1] |
auto[1] |
342510 |
1 |
|
|
T1 |
3058 |
|
T14 |
9841 |
|
T16 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7649613 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53362 |
| auto[1] |
5375788 |
1 |
|
|
T1 |
42431 |
|
T11 |
41 |
|
T13 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12343406 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90123 |
| auto[1] |
681995 |
1 |
|
|
T1 |
5670 |
|
T11 |
2 |
|
T14 |
20597 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7679302 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53068 |
| auto[1] |
5346099 |
1 |
|
|
T1 |
42725 |
|
T11 |
32 |
|
T13 |
19 |