Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7679155 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
55180 |
| auto[1] |
5346246 |
1 |
|
|
T1 |
40613 |
|
T11 |
34 |
|
T13 |
23 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12337362 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90410 |
| auto[1] |
688039 |
1 |
|
|
T1 |
5383 |
|
T11 |
1 |
|
T13 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7640340 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
55335 |
| auto[1] |
5385061 |
1 |
|
|
T1 |
40458 |
|
T11 |
44 |
|
T13 |
41 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2365962 |
1 |
|
|
T1 |
17995 |
|
T11 |
19 |
|
T13 |
39 |
| auto[1] |
auto[0] |
auto[1] |
346484 |
1 |
|
|
T1 |
2765 |
|
T13 |
2 |
|
T14 |
10168 |
| auto[1] |
auto[1] |
auto[0] |
2331060 |
1 |
|
|
T1 |
17080 |
|
T11 |
24 |
|
T14 |
66514 |
| auto[1] |
auto[1] |
auto[1] |
341555 |
1 |
|
|
T1 |
2618 |
|
T11 |
1 |
|
T14 |
9550 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |