Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7625626 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52663 |
| auto[1] |
5399775 |
1 |
|
|
T1 |
43130 |
|
T11 |
18 |
|
T13 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12347652 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90169 |
| auto[1] |
677749 |
1 |
|
|
T1 |
5624 |
|
T11 |
2 |
|
T13 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7692903 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53912 |
| auto[1] |
5332498 |
1 |
|
|
T1 |
41881 |
|
T11 |
39 |
|
T13 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2313288 |
1 |
|
|
T1 |
17757 |
|
T11 |
36 |
|
T13 |
18 |
| auto[1] |
auto[0] |
auto[1] |
336000 |
1 |
|
|
T1 |
2765 |
|
T11 |
2 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2341461 |
1 |
|
|
T1 |
18500 |
|
T11 |
1 |
|
T13 |
16 |
| auto[1] |
auto[1] |
auto[1] |
341749 |
1 |
|
|
T1 |
2859 |
|
T13 |
1 |
|
T14 |
10212 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |