Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7634598 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53364 |
| auto[1] |
5390803 |
1 |
|
|
T1 |
42429 |
|
T11 |
6 |
|
T13 |
57 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10815444 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
70420 |
| auto[1] |
2209957 |
1 |
|
|
T1 |
25373 |
|
T11 |
33 |
|
T13 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7656663 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53443 |
| auto[1] |
5368738 |
1 |
|
|
T1 |
42350 |
|
T11 |
56 |
|
T13 |
56 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1567301 |
1 |
|
|
T1 |
8103 |
|
T11 |
23 |
|
T13 |
14 |
| auto[1] |
auto[0] |
auto[1] |
1098600 |
1 |
|
|
T1 |
12175 |
|
T11 |
27 |
|
T13 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1591480 |
1 |
|
|
T1 |
8874 |
|
T13 |
10 |
|
T14 |
47166 |
| auto[1] |
auto[1] |
auto[1] |
1111357 |
1 |
|
|
T1 |
13198 |
|
T11 |
6 |
|
T13 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |