Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7642645 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53299 |
| auto[1] |
5382756 |
1 |
|
|
T1 |
42494 |
|
T11 |
30 |
|
T13 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10823013 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
70369 |
| auto[1] |
2202388 |
1 |
|
|
T1 |
25424 |
|
T11 |
23 |
|
T13 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7676093 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54146 |
| auto[1] |
5349308 |
1 |
|
|
T1 |
41647 |
|
T11 |
37 |
|
T13 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1569272 |
1 |
|
|
T1 |
8327 |
|
T11 |
14 |
|
T13 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1101275 |
1 |
|
|
T1 |
12970 |
|
T11 |
19 |
|
T13 |
29 |
| auto[1] |
auto[1] |
auto[0] |
1577648 |
1 |
|
|
T1 |
7896 |
|
T13 |
1 |
|
T14 |
49237 |
| auto[1] |
auto[1] |
auto[1] |
1101113 |
1 |
|
|
T1 |
12454 |
|
T11 |
4 |
|
T13 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |