Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7654640 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
55030 |
| auto[1] |
5370761 |
1 |
|
|
T1 |
40763 |
|
T11 |
32 |
|
T13 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10826870 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
69610 |
| auto[1] |
2198531 |
1 |
|
|
T1 |
26183 |
|
T11 |
10 |
|
T13 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7678426 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53273 |
| auto[1] |
5346975 |
1 |
|
|
T1 |
42520 |
|
T11 |
20 |
|
T13 |
28 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1576673 |
1 |
|
|
T1 |
8577 |
|
T11 |
10 |
|
T13 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1097563 |
1 |
|
|
T1 |
13810 |
|
T11 |
10 |
|
T13 |
15 |
| auto[1] |
auto[1] |
auto[0] |
1571771 |
1 |
|
|
T1 |
7760 |
|
T14 |
46774 |
|
T16 |
58 |
| auto[1] |
auto[1] |
auto[1] |
1100968 |
1 |
|
|
T1 |
12373 |
|
T14 |
28864 |
|
T16 |
48 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |