Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7645353 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54305 |
| auto[1] |
5380048 |
1 |
|
|
T1 |
41488 |
|
T11 |
6 |
|
T13 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10814924 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
70509 |
| auto[1] |
2210477 |
1 |
|
|
T1 |
25284 |
|
T11 |
40 |
|
T13 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7664352 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54538 |
| auto[1] |
5361049 |
1 |
|
|
T1 |
41255 |
|
T11 |
53 |
|
T13 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1570835 |
1 |
|
|
T1 |
8244 |
|
T11 |
13 |
|
T13 |
11 |
| auto[1] |
auto[0] |
auto[1] |
1108167 |
1 |
|
|
T1 |
12964 |
|
T11 |
40 |
|
T13 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1579737 |
1 |
|
|
T1 |
7727 |
|
T13 |
3 |
|
T14 |
48789 |
| auto[1] |
auto[1] |
auto[1] |
1102310 |
1 |
|
|
T1 |
12320 |
|
T14 |
29164 |
|
T16 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |