Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7658470 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51782 |
| auto[1] |
5366931 |
1 |
|
|
T1 |
44011 |
|
T11 |
21 |
|
T13 |
26 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10814774 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
70996 |
| auto[1] |
2210627 |
1 |
|
|
T1 |
24797 |
|
T11 |
21 |
|
T13 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7648509 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54928 |
| auto[1] |
5376892 |
1 |
|
|
T1 |
40865 |
|
T11 |
28 |
|
T13 |
35 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1575553 |
1 |
|
|
T1 |
7888 |
|
T11 |
7 |
|
T13 |
19 |
| auto[1] |
auto[0] |
auto[1] |
1103854 |
1 |
|
|
T1 |
12727 |
|
T11 |
21 |
|
T13 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1590712 |
1 |
|
|
T1 |
8180 |
|
T13 |
2 |
|
T14 |
49302 |
| auto[1] |
auto[1] |
auto[1] |
1106773 |
1 |
|
|
T1 |
12070 |
|
T14 |
29864 |
|
T16 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |