Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7675157 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51728 |
| auto[1] |
5350244 |
1 |
|
|
T1 |
44065 |
|
T11 |
22 |
|
T13 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12339728 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
89832 |
| auto[1] |
685673 |
1 |
|
|
T1 |
5961 |
|
T11 |
1 |
|
T14 |
20121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7650619 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
51666 |
| auto[1] |
5374782 |
1 |
|
|
T1 |
44127 |
|
T11 |
32 |
|
T13 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2346863 |
1 |
|
|
T1 |
18165 |
|
T11 |
29 |
|
T13 |
6 |
| auto[1] |
auto[0] |
auto[1] |
342617 |
1 |
|
|
T1 |
2783 |
|
T11 |
1 |
|
T14 |
10021 |
| auto[1] |
auto[1] |
auto[0] |
2342246 |
1 |
|
|
T1 |
20001 |
|
T11 |
2 |
|
T13 |
8 |
| auto[1] |
auto[1] |
auto[1] |
343056 |
1 |
|
|
T1 |
3178 |
|
T14 |
10100 |
|
T16 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |