Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7666451 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53611 |
| auto[1] |
5358950 |
1 |
|
|
T1 |
42182 |
|
T11 |
22 |
|
T13 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10830962 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
69676 |
| auto[1] |
2194439 |
1 |
|
|
T1 |
26117 |
|
T11 |
20 |
|
T13 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7708490 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52355 |
| auto[1] |
5316911 |
1 |
|
|
T1 |
43438 |
|
T11 |
36 |
|
T13 |
16 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1558463 |
1 |
|
|
T1 |
8872 |
|
T11 |
3 |
|
T13 |
3 |
| auto[1] |
auto[0] |
auto[1] |
1096861 |
1 |
|
|
T1 |
13493 |
|
T11 |
20 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1564009 |
1 |
|
|
T1 |
8449 |
|
T11 |
13 |
|
T13 |
7 |
| auto[1] |
auto[1] |
auto[1] |
1097578 |
1 |
|
|
T1 |
12624 |
|
T13 |
5 |
|
T14 |
28370 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |