Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7649125 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52890 |
| auto[1] |
5376276 |
1 |
|
|
T1 |
42903 |
|
T11 |
28 |
|
T13 |
35 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10821237 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
69933 |
| auto[1] |
2204164 |
1 |
|
|
T1 |
25860 |
|
T11 |
20 |
|
T13 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7661295 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53196 |
| auto[1] |
5364106 |
1 |
|
|
T1 |
42597 |
|
T11 |
28 |
|
T13 |
31 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1576119 |
1 |
|
|
T1 |
8326 |
|
T11 |
8 |
|
T13 |
13 |
| auto[1] |
auto[0] |
auto[1] |
1099578 |
1 |
|
|
T1 |
12975 |
|
T11 |
17 |
|
T13 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1583823 |
1 |
|
|
T1 |
8411 |
|
T13 |
6 |
|
T14 |
51634 |
| auto[1] |
auto[1] |
auto[1] |
1104586 |
1 |
|
|
T1 |
12885 |
|
T11 |
3 |
|
T13 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |