Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7683043 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52858 |
| auto[1] |
5342358 |
1 |
|
|
T1 |
42935 |
|
T11 |
17 |
|
T13 |
24 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12341547 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90210 |
| auto[1] |
683854 |
1 |
|
|
T1 |
5583 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7660722 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53754 |
| auto[1] |
5364679 |
1 |
|
|
T1 |
42039 |
|
T11 |
43 |
|
T13 |
21 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2364439 |
1 |
|
|
T1 |
17913 |
|
T11 |
37 |
|
T13 |
20 |
| auto[1] |
auto[0] |
auto[1] |
346638 |
1 |
|
|
T1 |
2849 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2316386 |
1 |
|
|
T1 |
18543 |
|
T11 |
5 |
|
T14 |
68873 |
| auto[1] |
auto[1] |
auto[1] |
337216 |
1 |
|
|
T1 |
2734 |
|
T14 |
9836 |
|
T16 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |