Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7642813 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53542 |
| auto[1] |
5382588 |
1 |
|
|
T1 |
42251 |
|
T11 |
34 |
|
T13 |
44 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12344979 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
89940 |
| auto[1] |
680422 |
1 |
|
|
T1 |
5853 |
|
T11 |
1 |
|
T13 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7696269 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
52533 |
| auto[1] |
5329132 |
1 |
|
|
T1 |
43260 |
|
T11 |
42 |
|
T13 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2308933 |
1 |
|
|
T1 |
19403 |
|
T11 |
24 |
|
T13 |
22 |
| auto[1] |
auto[0] |
auto[1] |
337240 |
1 |
|
|
T1 |
3000 |
|
T11 |
1 |
|
T13 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2339777 |
1 |
|
|
T1 |
18004 |
|
T11 |
17 |
|
T13 |
9 |
| auto[1] |
auto[1] |
auto[1] |
343182 |
1 |
|
|
T1 |
2853 |
|
T14 |
10425 |
|
T16 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |