Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7666972 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
54225 |
| auto[1] |
5358429 |
1 |
|
|
T1 |
41568 |
|
T11 |
47 |
|
T13 |
60 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12345259 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
90141 |
| auto[1] |
680142 |
1 |
|
|
T1 |
5652 |
|
T11 |
1 |
|
T14 |
19810 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7691801 |
1 |
|
|
T20 |
561 |
|
T21 |
50 |
|
T1 |
53894 |
| auto[1] |
5333600 |
1 |
|
|
T1 |
41899 |
|
T11 |
38 |
|
T13 |
15 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2335530 |
1 |
|
|
T1 |
19108 |
|
T11 |
11 |
|
T13 |
1 |
| auto[1] |
auto[0] |
auto[1] |
341572 |
1 |
|
|
T1 |
3014 |
|
T11 |
1 |
|
T14 |
10328 |
| auto[1] |
auto[1] |
auto[0] |
2317928 |
1 |
|
|
T1 |
17139 |
|
T11 |
26 |
|
T13 |
14 |
| auto[1] |
auto[1] |
auto[1] |
338570 |
1 |
|
|
T1 |
2638 |
|
T14 |
9482 |
|
T16 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |