Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 942
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T762 /workspace/coverage/cover_reg_top/24.gpio_intr_test.95669526 Jun 25 05:39:47 PM PDT 24 Jun 25 05:39:50 PM PDT 24 40315502 ps
T763 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3742133388 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:53 PM PDT 24 25572693 ps
T764 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.165119094 Jun 25 05:39:33 PM PDT 24 Jun 25 05:39:37 PM PDT 24 208991102 ps
T765 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3232922464 Jun 25 05:39:33 PM PDT 24 Jun 25 05:39:35 PM PDT 24 20934944 ps
T766 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3176894123 Jun 25 05:39:45 PM PDT 24 Jun 25 05:39:49 PM PDT 24 40343542 ps
T767 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.104609456 Jun 25 05:39:34 PM PDT 24 Jun 25 05:39:39 PM PDT 24 690735106 ps
T768 /workspace/coverage/cover_reg_top/10.gpio_intr_test.3268345892 Jun 25 05:39:42 PM PDT 24 Jun 25 05:39:44 PM PDT 24 11850305 ps
T39 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1862149358 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:47 PM PDT 24 444457868 ps
T77 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.184557255 Jun 25 05:39:27 PM PDT 24 Jun 25 05:39:29 PM PDT 24 13742077 ps
T769 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3773951154 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:40 PM PDT 24 21436277 ps
T78 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2743104612 Jun 25 05:39:45 PM PDT 24 Jun 25 05:39:48 PM PDT 24 15614247 ps
T770 /workspace/coverage/cover_reg_top/49.gpio_intr_test.480147066 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:53 PM PDT 24 23684793 ps
T37 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4020864283 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:54 PM PDT 24 794598449 ps
T771 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1212538211 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:47 PM PDT 24 69280097 ps
T772 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2923852467 Jun 25 05:39:32 PM PDT 24 Jun 25 05:39:35 PM PDT 24 140769988 ps
T773 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3809105486 Jun 25 05:39:34 PM PDT 24 Jun 25 05:39:38 PM PDT 24 196344883 ps
T38 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.31423557 Jun 25 05:39:24 PM PDT 24 Jun 25 05:39:27 PM PDT 24 421982628 ps
T774 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2754270860 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:47 PM PDT 24 198732591 ps
T775 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2001194576 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:54 PM PDT 24 45975409 ps
T776 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1591597871 Jun 25 05:39:50 PM PDT 24 Jun 25 05:39:53 PM PDT 24 29780931 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3140485512 Jun 25 05:39:41 PM PDT 24 Jun 25 05:39:43 PM PDT 24 16044122 ps
T778 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2827358980 Jun 25 05:39:39 PM PDT 24 Jun 25 05:39:42 PM PDT 24 91980443 ps
T79 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2324949748 Jun 25 05:39:33 PM PDT 24 Jun 25 05:39:35 PM PDT 24 45403172 ps
T40 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4149582464 Jun 25 05:39:32 PM PDT 24 Jun 25 05:39:34 PM PDT 24 79856658 ps
T779 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3650984117 Jun 25 05:39:35 PM PDT 24 Jun 25 05:39:38 PM PDT 24 44652042 ps
T780 /workspace/coverage/cover_reg_top/43.gpio_intr_test.4219274523 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:56 PM PDT 24 27929040 ps
T781 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2847551623 Jun 25 05:39:41 PM PDT 24 Jun 25 05:39:44 PM PDT 24 96034938 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1785654206 Jun 25 05:39:34 PM PDT 24 Jun 25 05:39:37 PM PDT 24 38459121 ps
T783 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3204501460 Jun 25 05:39:25 PM PDT 24 Jun 25 05:39:27 PM PDT 24 47778610 ps
T784 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1000433616 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:39 PM PDT 24 150103125 ps
T785 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1412723430 Jun 25 05:39:47 PM PDT 24 Jun 25 05:39:50 PM PDT 24 53925559 ps
T786 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1775491146 Jun 25 05:39:39 PM PDT 24 Jun 25 05:39:42 PM PDT 24 38071649 ps
T787 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.36035682 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:40 PM PDT 24 21636390 ps
T788 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.594497500 Jun 25 05:39:33 PM PDT 24 Jun 25 05:39:36 PM PDT 24 116726585 ps
T789 /workspace/coverage/cover_reg_top/25.gpio_intr_test.270063401 Jun 25 05:39:50 PM PDT 24 Jun 25 05:39:53 PM PDT 24 15123225 ps
T790 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.23982324 Jun 25 05:39:40 PM PDT 24 Jun 25 05:39:43 PM PDT 24 93118850 ps
T791 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.220183088 Jun 25 05:39:37 PM PDT 24 Jun 25 05:39:41 PM PDT 24 1380757677 ps
T792 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1279274992 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:46 PM PDT 24 49105238 ps
T793 /workspace/coverage/cover_reg_top/14.gpio_intr_test.3218927934 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:45 PM PDT 24 14505698 ps
T794 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2989539034 Jun 25 05:39:45 PM PDT 24 Jun 25 05:39:49 PM PDT 24 144697263 ps
T795 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2588636487 Jun 25 05:39:25 PM PDT 24 Jun 25 05:39:28 PM PDT 24 32752712 ps
T796 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1412984645 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:47 PM PDT 24 71080978 ps
T797 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3296450067 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 27932620 ps
T798 /workspace/coverage/cover_reg_top/16.gpio_intr_test.171793919 Jun 25 05:39:45 PM PDT 24 Jun 25 05:39:48 PM PDT 24 34073872 ps
T799 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1974903593 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:40 PM PDT 24 14273939 ps
T800 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3817524939 Jun 25 05:39:46 PM PDT 24 Jun 25 05:39:49 PM PDT 24 25536406 ps
T80 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3662095019 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:40 PM PDT 24 141553802 ps
T801 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1098576305 Jun 25 05:39:44 PM PDT 24 Jun 25 05:39:48 PM PDT 24 115227706 ps
T802 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3957763153 Jun 25 05:39:42 PM PDT 24 Jun 25 05:39:47 PM PDT 24 548641633 ps
T803 /workspace/coverage/cover_reg_top/34.gpio_intr_test.799974439 Jun 25 05:39:50 PM PDT 24 Jun 25 05:39:53 PM PDT 24 22439400 ps
T81 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1450276552 Jun 25 05:39:28 PM PDT 24 Jun 25 05:39:32 PM PDT 24 43463877 ps
T804 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.302349470 Jun 25 05:39:35 PM PDT 24 Jun 25 05:39:39 PM PDT 24 124353179 ps
T805 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3755152809 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:45 PM PDT 24 55482643 ps
T806 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1080211391 Jun 25 05:39:42 PM PDT 24 Jun 25 05:39:44 PM PDT 24 20093414 ps
T807 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3548857946 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:57 PM PDT 24 38221931 ps
T808 /workspace/coverage/cover_reg_top/44.gpio_intr_test.2056204681 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:58 PM PDT 24 13812476 ps
T83 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.789526833 Jun 25 05:39:33 PM PDT 24 Jun 25 05:39:34 PM PDT 24 13728625 ps
T82 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1793166023 Jun 25 05:39:27 PM PDT 24 Jun 25 05:39:30 PM PDT 24 35190286 ps
T809 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2308420849 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 14528288 ps
T810 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.412161538 Jun 25 05:39:45 PM PDT 24 Jun 25 05:39:49 PM PDT 24 36347386 ps
T811 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.682153524 Jun 25 05:39:32 PM PDT 24 Jun 25 05:39:34 PM PDT 24 13406849 ps
T812 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.622530746 Jun 25 05:39:34 PM PDT 24 Jun 25 05:39:36 PM PDT 24 39715917 ps
T813 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3501064020 Jun 25 05:39:47 PM PDT 24 Jun 25 05:39:51 PM PDT 24 115342853 ps
T814 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3564918712 Jun 25 05:39:39 PM PDT 24 Jun 25 05:39:42 PM PDT 24 56145485 ps
T815 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3975172618 Jun 25 05:39:44 PM PDT 24 Jun 25 05:39:48 PM PDT 24 33443137 ps
T816 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1429156078 Jun 25 05:39:44 PM PDT 24 Jun 25 05:39:48 PM PDT 24 30510996 ps
T817 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2430843623 Jun 25 05:39:26 PM PDT 24 Jun 25 05:39:29 PM PDT 24 24788159 ps
T818 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1586106315 Jun 25 05:39:44 PM PDT 24 Jun 25 05:39:47 PM PDT 24 106866695 ps
T819 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1517672698 Jun 25 05:39:39 PM PDT 24 Jun 25 05:39:42 PM PDT 24 45223603 ps
T820 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2071834866 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:55 PM PDT 24 14884352 ps
T821 /workspace/coverage/cover_reg_top/48.gpio_intr_test.3582201062 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 44199804 ps
T822 /workspace/coverage/cover_reg_top/11.gpio_intr_test.101120131 Jun 25 05:39:46 PM PDT 24 Jun 25 05:39:49 PM PDT 24 30761613 ps
T823 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1209189182 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:47 PM PDT 24 172905538 ps
T824 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2883189746 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:40 PM PDT 24 100125495 ps
T825 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1115246597 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:41 PM PDT 24 186963858 ps
T826 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4066592711 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:46 PM PDT 24 103941620 ps
T827 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.786470357 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:48 PM PDT 24 148152086 ps
T828 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1471453538 Jun 25 05:39:34 PM PDT 24 Jun 25 05:39:36 PM PDT 24 53151589 ps
T829 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3609724893 Jun 25 05:39:45 PM PDT 24 Jun 25 05:39:49 PM PDT 24 30683029 ps
T830 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2359262129 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:46 PM PDT 24 15871131 ps
T831 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1837819377 Jun 25 05:39:32 PM PDT 24 Jun 25 05:39:34 PM PDT 24 11269394 ps
T832 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2607790987 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 37275138 ps
T833 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2097901097 Jun 25 05:39:36 PM PDT 24 Jun 25 05:39:39 PM PDT 24 69839580 ps
T834 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4016185407 Jun 25 05:39:42 PM PDT 24 Jun 25 05:39:45 PM PDT 24 83353020 ps
T835 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.4059262581 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:45 PM PDT 24 14477413 ps
T836 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4180801323 Jun 25 05:39:45 PM PDT 24 Jun 25 05:39:48 PM PDT 24 90135604 ps
T837 /workspace/coverage/cover_reg_top/12.gpio_intr_test.4089808950 Jun 25 05:39:42 PM PDT 24 Jun 25 05:39:45 PM PDT 24 14263312 ps
T838 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2704216069 Jun 25 05:39:50 PM PDT 24 Jun 25 05:39:53 PM PDT 24 18438729 ps
T839 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3201027544 Jun 25 05:39:34 PM PDT 24 Jun 25 05:39:37 PM PDT 24 50049430 ps
T840 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.685094412 Jun 25 05:39:34 PM PDT 24 Jun 25 05:39:37 PM PDT 24 56166769 ps
T841 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2644344858 Jun 25 05:39:43 PM PDT 24 Jun 25 05:39:51 PM PDT 24 93393642 ps
T842 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1713155146 Jun 25 05:39:42 PM PDT 24 Jun 25 05:39:46 PM PDT 24 261293228 ps
T843 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.645361026 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 77215360 ps
T844 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1470476543 Jun 25 05:39:55 PM PDT 24 Jun 25 05:39:58 PM PDT 24 99308546 ps
T845 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.263632842 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:54 PM PDT 24 80336793 ps
T846 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.877859494 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 44109638 ps
T847 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2633171811 Jun 25 05:40:04 PM PDT 24 Jun 25 05:40:07 PM PDT 24 263694446 ps
T848 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4010498866 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:57 PM PDT 24 121819708 ps
T849 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1669660746 Jun 25 05:40:13 PM PDT 24 Jun 25 05:40:16 PM PDT 24 77314736 ps
T850 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1130525757 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:58 PM PDT 24 39495280 ps
T851 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.85403385 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 146046293 ps
T852 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1124987916 Jun 25 05:40:00 PM PDT 24 Jun 25 05:40:03 PM PDT 24 145384807 ps
T853 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4134228540 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 46250096 ps
T854 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3113065774 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:05 PM PDT 24 150619609 ps
T855 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.845872902 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 75736590 ps
T856 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.585018952 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 81066419 ps
T857 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.664440346 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:58 PM PDT 24 109706240 ps
T858 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2895344535 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:53 PM PDT 24 54779187 ps
T859 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1463499483 Jun 25 05:40:00 PM PDT 24 Jun 25 05:40:04 PM PDT 24 65186149 ps
T860 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2113741486 Jun 25 05:39:58 PM PDT 24 Jun 25 05:40:01 PM PDT 24 68026334 ps
T861 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.316765682 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:57 PM PDT 24 223698509 ps
T862 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3145163340 Jun 25 05:40:09 PM PDT 24 Jun 25 05:40:12 PM PDT 24 134757078 ps
T863 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2436127094 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:58 PM PDT 24 52785317 ps
T864 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1858878277 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:03 PM PDT 24 122936336 ps
T865 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1327884353 Jun 25 05:40:05 PM PDT 24 Jun 25 05:40:08 PM PDT 24 129825184 ps
T866 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4205174915 Jun 25 05:40:05 PM PDT 24 Jun 25 05:40:08 PM PDT 24 259331072 ps
T867 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3145301351 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:55 PM PDT 24 39497055 ps
T868 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2900655741 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:05 PM PDT 24 65614299 ps
T869 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.112610543 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:53 PM PDT 24 233180074 ps
T870 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2376666647 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:58 PM PDT 24 56079798 ps
T871 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2576813782 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 46882290 ps
T872 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127164412 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:55 PM PDT 24 72947722 ps
T873 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3651175504 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:56 PM PDT 24 98673849 ps
T874 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2737056343 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:56 PM PDT 24 29132840 ps
T875 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.158407180 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:04 PM PDT 24 231211619 ps
T876 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3531728009 Jun 25 05:40:06 PM PDT 24 Jun 25 05:40:08 PM PDT 24 45865713 ps
T877 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1554964375 Jun 25 05:39:56 PM PDT 24 Jun 25 05:39:59 PM PDT 24 24910019 ps
T878 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2560487447 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:02 PM PDT 24 41377460 ps
T879 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2478669870 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:05 PM PDT 24 194549279 ps
T880 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858157572 Jun 25 05:40:05 PM PDT 24 Jun 25 05:40:07 PM PDT 24 40550115 ps
T881 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1337595803 Jun 25 05:40:00 PM PDT 24 Jun 25 05:40:03 PM PDT 24 26632182 ps
T882 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.847883116 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 38867822 ps
T883 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3679528118 Jun 25 05:40:02 PM PDT 24 Jun 25 05:40:06 PM PDT 24 838459990 ps
T884 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1907497601 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:05 PM PDT 24 380185303 ps
T885 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098751472 Jun 25 05:39:58 PM PDT 24 Jun 25 05:40:01 PM PDT 24 96993453 ps
T886 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3901957335 Jun 25 05:40:03 PM PDT 24 Jun 25 05:40:06 PM PDT 24 96823229 ps
T887 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2313464450 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 88363694 ps
T888 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1420260535 Jun 25 05:40:05 PM PDT 24 Jun 25 05:40:07 PM PDT 24 41676058 ps
T889 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983363892 Jun 25 05:40:16 PM PDT 24 Jun 25 05:40:18 PM PDT 24 116870514 ps
T890 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731822922 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 34326213 ps
T891 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1402339313 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:01 PM PDT 24 47447000 ps
T892 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.479193108 Jun 25 05:40:03 PM PDT 24 Jun 25 05:40:06 PM PDT 24 85968242 ps
T893 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2684001581 Jun 25 05:40:02 PM PDT 24 Jun 25 05:40:06 PM PDT 24 49746269 ps
T894 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1496620424 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:04 PM PDT 24 86485786 ps
T895 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.938075779 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:53 PM PDT 24 18008241 ps
T896 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4203903601 Jun 25 05:40:00 PM PDT 24 Jun 25 05:40:04 PM PDT 24 267661485 ps
T897 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.915757676 Jun 25 05:40:00 PM PDT 24 Jun 25 05:40:04 PM PDT 24 66103575 ps
T898 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.755061247 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:53 PM PDT 24 63633007 ps
T899 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3754682168 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 178935238 ps
T900 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.392734953 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 264909721 ps
T901 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4019433145 Jun 25 05:40:02 PM PDT 24 Jun 25 05:40:06 PM PDT 24 339325127 ps
T902 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1222625371 Jun 25 05:40:03 PM PDT 24 Jun 25 05:40:06 PM PDT 24 117316687 ps
T903 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3301287090 Jun 25 05:40:04 PM PDT 24 Jun 25 05:40:07 PM PDT 24 232569205 ps
T904 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1487315040 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 75567224 ps
T905 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.658459110 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:02 PM PDT 24 69597193 ps
T906 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.195170002 Jun 25 05:40:02 PM PDT 24 Jun 25 05:40:06 PM PDT 24 38205993 ps
T907 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2516317319 Jun 25 05:40:06 PM PDT 24 Jun 25 05:40:09 PM PDT 24 382064712 ps
T908 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3847378883 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:02 PM PDT 24 179885821 ps
T909 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.117663768 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 51897689 ps
T910 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.563940833 Jun 25 05:40:08 PM PDT 24 Jun 25 05:40:10 PM PDT 24 469598313 ps
T911 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.891763682 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:03 PM PDT 24 105714899 ps
T912 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2060204667 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 68143802 ps
T913 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.159865037 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:54 PM PDT 24 145324844 ps
T914 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.151216523 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:02 PM PDT 24 339705000 ps
T915 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1099085867 Jun 25 05:39:56 PM PDT 24 Jun 25 05:39:59 PM PDT 24 122178309 ps
T916 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2446337542 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:58 PM PDT 24 296104745 ps
T917 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2900603261 Jun 25 05:39:56 PM PDT 24 Jun 25 05:40:00 PM PDT 24 55928539 ps
T918 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3988975819 Jun 25 05:40:00 PM PDT 24 Jun 25 05:40:04 PM PDT 24 80816424 ps
T919 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2919075174 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 88792563 ps
T920 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.913010305 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:05 PM PDT 24 41477222 ps
T921 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2908316766 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:03 PM PDT 24 62593856 ps
T922 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1466106946 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 199503807 ps
T923 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3684386079 Jun 25 05:39:58 PM PDT 24 Jun 25 05:40:00 PM PDT 24 154251894 ps
T924 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3417381109 Jun 25 05:40:06 PM PDT 24 Jun 25 05:40:09 PM PDT 24 46059847 ps
T925 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4038549337 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:54 PM PDT 24 38636964 ps
T926 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3067033901 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 124895490 ps
T927 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2921667501 Jun 25 05:40:04 PM PDT 24 Jun 25 05:40:07 PM PDT 24 51017891 ps
T928 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1640066990 Jun 25 05:40:01 PM PDT 24 Jun 25 05:40:05 PM PDT 24 61754624 ps
T929 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1124218871 Jun 25 05:39:53 PM PDT 24 Jun 25 05:39:57 PM PDT 24 48114718 ps
T930 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2426629771 Jun 25 05:40:06 PM PDT 24 Jun 25 05:40:09 PM PDT 24 273069450 ps
T931 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.477643673 Jun 25 05:39:54 PM PDT 24 Jun 25 05:39:57 PM PDT 24 131718166 ps
T932 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3201183102 Jun 25 05:40:06 PM PDT 24 Jun 25 05:40:08 PM PDT 24 36814114 ps
T933 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3183754141 Jun 25 05:40:04 PM PDT 24 Jun 25 05:40:07 PM PDT 24 121441970 ps
T934 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2673091379 Jun 25 05:39:55 PM PDT 24 Jun 25 05:39:59 PM PDT 24 189847143 ps
T935 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2952348180 Jun 25 05:40:05 PM PDT 24 Jun 25 05:40:08 PM PDT 24 306714108 ps
T936 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3843290792 Jun 25 05:40:04 PM PDT 24 Jun 25 05:40:06 PM PDT 24 58623168 ps
T937 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1524097379 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:54 PM PDT 24 116451541 ps
T938 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2666443260 Jun 25 05:40:03 PM PDT 24 Jun 25 05:40:06 PM PDT 24 60944452 ps
T939 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1535051215 Jun 25 05:39:51 PM PDT 24 Jun 25 05:39:54 PM PDT 24 141287899 ps
T940 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3107775937 Jun 25 05:39:52 PM PDT 24 Jun 25 05:39:56 PM PDT 24 188216856 ps
T941 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3770564766 Jun 25 05:39:59 PM PDT 24 Jun 25 05:40:02 PM PDT 24 132456799 ps
T942 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.952362907 Jun 25 05:40:11 PM PDT 24 Jun 25 05:40:13 PM PDT 24 48505765 ps

Test location /workspace/coverage/default/28.gpio_full_random.3001437243
Short name T13
Test name
Test status
Simulation time 78636915 ps
CPU time 1.01 seconds
Started Jun 25 05:41:03 PM PDT 24
Finished Jun 25 05:41:06 PM PDT 24
Peak memory 198380 kb
Host smart-3573203a-32b2-4852-8ca4-de3a0add6cb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001437243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3001437243
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2485001535
Short name T167
Test name
Test status
Simulation time 39245017 ps
CPU time 1.73 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:30 PM PDT 24
Peak memory 198660 kb
Host smart-44742380-9704-49f9-8355-f58a2860ede1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485001535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2485001535
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2046270991
Short name T14
Test name
Test status
Simulation time 132282077057 ps
CPU time 710.09 seconds
Started Jun 25 05:41:03 PM PDT 24
Finished Jun 25 05:52:55 PM PDT 24
Peak memory 207192 kb
Host smart-b14b1f4b-ccc4-43c5-89a2-c9b3b174fa4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2046270991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2046270991
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.550165622
Short name T27
Test name
Test status
Simulation time 481331077 ps
CPU time 1.01 seconds
Started Jun 25 05:40:22 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 215392 kb
Host smart-26ac7b80-5ea7-437d-877d-18565347a060
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550165622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.550165622
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.543718038
Short name T65
Test name
Test status
Simulation time 45823634 ps
CPU time 0.76 seconds
Started Jun 25 05:39:32 PM PDT 24
Finished Jun 25 05:39:34 PM PDT 24
Peak memory 196752 kb
Host smart-aa9ebce1-ef23-4673-8485-358735ed01d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543718038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.543718038
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1392014943
Short name T34
Test name
Test status
Simulation time 113805283 ps
CPU time 1.52 seconds
Started Jun 25 05:39:39 PM PDT 24
Finished Jun 25 05:39:42 PM PDT 24
Peak memory 198764 kb
Host smart-7a4d32a9-f780-45f6-be80-4e213b93ec7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392014943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1392014943
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3136266533
Short name T2
Test name
Test status
Simulation time 2418980517 ps
CPU time 26.9 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:39 PM PDT 24
Peak memory 198840 kb
Host smart-2f535905-ae92-4073-946d-383f51d5f2f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136266533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3136266533
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2581294370
Short name T227
Test name
Test status
Simulation time 36551416 ps
CPU time 0.59 seconds
Started Jun 25 05:40:39 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 195376 kb
Host smart-71c66ce0-c2cc-46e9-9171-162cd1e0a19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581294370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2581294370
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1398770185
Short name T74
Test name
Test status
Simulation time 17618305 ps
CPU time 0.63 seconds
Started Jun 25 05:39:32 PM PDT 24
Finished Jun 25 05:39:34 PM PDT 24
Peak memory 195700 kb
Host smart-bd646064-971c-4c3e-b42a-9910be88ce48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398770185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1398770185
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.778798491
Short name T69
Test name
Test status
Simulation time 19483482 ps
CPU time 0.66 seconds
Started Jun 25 05:39:26 PM PDT 24
Finished Jun 25 05:39:28 PM PDT 24
Peak memory 195204 kb
Host smart-2965379b-b785-40ca-b41f-f444a6447a44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778798491 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.778798491
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.31423557
Short name T38
Test name
Test status
Simulation time 421982628 ps
CPU time 1.51 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:27 PM PDT 24
Peak memory 198688 kb
Host smart-253fe763-3c52-4093-bd04-d4d86b1d2d13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31423557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_tl_intg_err.31423557
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1793166023
Short name T82
Test name
Test status
Simulation time 35190286 ps
CPU time 0.82 seconds
Started Jun 25 05:39:27 PM PDT 24
Finished Jun 25 05:39:30 PM PDT 24
Peak memory 197148 kb
Host smart-f1a6b892-76da-4986-8f4b-e9830086d174
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793166023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1793166023
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3286624061
Short name T742
Test name
Test status
Simulation time 355254776 ps
CPU time 1.46 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:27 PM PDT 24
Peak memory 197212 kb
Host smart-6ccb7aa5-ffcf-4207-9044-e06fa24d2979
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286624061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3286624061
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.815648090
Short name T750
Test name
Test status
Simulation time 64039771 ps
CPU time 1.64 seconds
Started Jun 25 05:39:27 PM PDT 24
Finished Jun 25 05:39:30 PM PDT 24
Peak memory 198804 kb
Host smart-71566774-53a9-4a04-90cf-58611ffddb7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815648090 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.815648090
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2852996523
Short name T739
Test name
Test status
Simulation time 15350621 ps
CPU time 0.64 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:27 PM PDT 24
Peak memory 196136 kb
Host smart-0de856c7-a8f1-4a00-8382-c9e340182918
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852996523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2852996523
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2437227765
Short name T754
Test name
Test status
Simulation time 11042952 ps
CPU time 0.61 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:38 PM PDT 24
Peak memory 194584 kb
Host smart-8577310c-4f3d-43e6-ab7f-f2e9c26ee322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437227765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2437227765
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3693483400
Short name T736
Test name
Test status
Simulation time 113451377 ps
CPU time 2.25 seconds
Started Jun 25 05:39:28 PM PDT 24
Finished Jun 25 05:39:32 PM PDT 24
Peak memory 198736 kb
Host smart-2287508b-703b-4251-b0c2-eb2f8e804e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693483400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3693483400
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.394050527
Short name T734
Test name
Test status
Simulation time 33183811 ps
CPU time 1.35 seconds
Started Jun 25 05:39:29 PM PDT 24
Finished Jun 25 05:39:33 PM PDT 24
Peak memory 197380 kb
Host smart-8adb2201-f275-445c-8255-3bc78eb49314
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394050527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.394050527
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3154772711
Short name T759
Test name
Test status
Simulation time 28646873 ps
CPU time 0.66 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:36 PM PDT 24
Peak memory 195048 kb
Host smart-a325f57a-f0ba-4e3c-9e8b-1e278029cc25
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154772711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3154772711
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2588636487
Short name T795
Test name
Test status
Simulation time 32752712 ps
CPU time 0.94 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:39:28 PM PDT 24
Peak memory 198536 kb
Host smart-87a9f337-fe36-4adb-a12c-a3c107232af2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588636487 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2588636487
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.184557255
Short name T77
Test name
Test status
Simulation time 13742077 ps
CPU time 0.61 seconds
Started Jun 25 05:39:27 PM PDT 24
Finished Jun 25 05:39:29 PM PDT 24
Peak memory 195568 kb
Host smart-4c8110c9-ce32-4a80-9a8f-2bd3db3b1c15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184557255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.184557255
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3204501460
Short name T783
Test name
Test status
Simulation time 47778610 ps
CPU time 0.63 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:39:27 PM PDT 24
Peak memory 194496 kb
Host smart-47be8a2b-eb7f-413d-86bc-ee34d032f5e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204501460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3204501460
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1650938779
Short name T63
Test name
Test status
Simulation time 109254441 ps
CPU time 0.93 seconds
Started Jun 25 05:39:24 PM PDT 24
Finished Jun 25 05:39:27 PM PDT 24
Peak memory 196988 kb
Host smart-480f099d-7e7a-473e-8e1c-fb800e75395a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650938779 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1650938779
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.460507105
Short name T727
Test name
Test status
Simulation time 24114636 ps
CPU time 1.27 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 198860 kb
Host smart-c58fbe51-8a64-43e1-8b23-472347d1015d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460507105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.460507105
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.220183088
Short name T791
Test name
Test status
Simulation time 1380757677 ps
CPU time 1.14 seconds
Started Jun 25 05:39:37 PM PDT 24
Finished Jun 25 05:39:41 PM PDT 24
Peak memory 198852 kb
Host smart-7d671707-feb2-4e35-9f20-77cc112f05fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220183088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.220183088
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.824723687
Short name T732
Test name
Test status
Simulation time 20341533 ps
CPU time 0.7 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 197572 kb
Host smart-43fd10bf-797f-4dc9-8feb-fd3c913c4d70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824723687 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.824723687
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.4059262581
Short name T835
Test name
Test status
Simulation time 14477413 ps
CPU time 0.58 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 194012 kb
Host smart-ce25e749-64c8-48a9-acea-b8bfe300d666
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059262581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.4059262581
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3268345892
Short name T768
Test name
Test status
Simulation time 11850305 ps
CPU time 0.6 seconds
Started Jun 25 05:39:42 PM PDT 24
Finished Jun 25 05:39:44 PM PDT 24
Peak memory 195080 kb
Host smart-88e82fc6-033f-4849-8627-69eb4c2d1123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268345892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3268345892
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3817524939
Short name T800
Test name
Test status
Simulation time 25536406 ps
CPU time 0.76 seconds
Started Jun 25 05:39:46 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 196848 kb
Host smart-f5b2c3f3-b85e-4d5a-b509-6eba4e7795b6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817524939 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3817524939
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3957763153
Short name T802
Test name
Test status
Simulation time 548641633 ps
CPU time 2.32 seconds
Started Jun 25 05:39:42 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 198740 kb
Host smart-3283da4a-dfc8-4651-9708-0076ccad5727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957763153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3957763153
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4020864283
Short name T37
Test name
Test status
Simulation time 794598449 ps
CPU time 1.06 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:54 PM PDT 24
Peak memory 198692 kb
Host smart-43d30e12-a2cc-4c24-b847-b8cd19a70dc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020864283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4020864283
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3975172618
Short name T815
Test name
Test status
Simulation time 33443137 ps
CPU time 1.55 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 198816 kb
Host smart-4585d960-177d-4860-98c7-d2bdc344877f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975172618 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3975172618
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3321545622
Short name T75
Test name
Test status
Simulation time 40285280 ps
CPU time 0.59 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 195200 kb
Host smart-b6b1f9d2-8498-4c02-bc96-5c56141a52d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321545622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3321545622
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.101120131
Short name T822
Test name
Test status
Simulation time 30761613 ps
CPU time 0.6 seconds
Started Jun 25 05:39:46 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 194376 kb
Host smart-16c55e6c-db22-4cd0-b5c6-18f9449968ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101120131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.101120131
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2167104598
Short name T88
Test name
Test status
Simulation time 34123986 ps
CPU time 0.76 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 196680 kb
Host smart-7d9865fd-f349-4d97-8757-94489dfd573c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167104598 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2167104598
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3863677500
Short name T753
Test name
Test status
Simulation time 105631176 ps
CPU time 2.48 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 198760 kb
Host smart-0d646495-f85d-4e4d-8435-91a553acf1ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863677500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3863677500
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.511186509
Short name T35
Test name
Test status
Simulation time 105599443 ps
CPU time 1.41 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 198748 kb
Host smart-665b4943-1e0c-4c07-93e5-d8ed5012ab44
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511186509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.511186509
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.23982324
Short name T790
Test name
Test status
Simulation time 93118850 ps
CPU time 0.86 seconds
Started Jun 25 05:39:40 PM PDT 24
Finished Jun 25 05:39:43 PM PDT 24
Peak memory 198640 kb
Host smart-d22e23c0-eb35-4bfc-bed8-cb3735165040
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23982324 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.23982324
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.412161538
Short name T810
Test name
Test status
Simulation time 36347386 ps
CPU time 0.61 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 195536 kb
Host smart-c910d781-c1e7-414e-9688-8b7f38f55856
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412161538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.412161538
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.4089808950
Short name T837
Test name
Test status
Simulation time 14263312 ps
CPU time 0.64 seconds
Started Jun 25 05:39:42 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 194472 kb
Host smart-c01432c2-8165-4eb4-bb14-5bd76c349360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089808950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.4089808950
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2797931286
Short name T72
Test name
Test status
Simulation time 83292242 ps
CPU time 0.8 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 196548 kb
Host smart-c87c86dc-e2da-468d-9c89-c7c89b11a4f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797931286 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2797931286
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1212538211
Short name T771
Test name
Test status
Simulation time 69280097 ps
CPU time 2 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 198752 kb
Host smart-3987cb91-5f90-43c1-8f73-4ceb2684c47c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212538211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1212538211
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1066054677
Short name T24
Test name
Test status
Simulation time 259599135 ps
CPU time 0.91 seconds
Started Jun 25 05:39:41 PM PDT 24
Finished Jun 25 05:39:44 PM PDT 24
Peak memory 197816 kb
Host smart-1d038b1a-5630-454f-9afa-ecbfdb40910f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066054677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1066054677
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2847551623
Short name T781
Test name
Test status
Simulation time 96034938 ps
CPU time 1.25 seconds
Started Jun 25 05:39:41 PM PDT 24
Finished Jun 25 05:39:44 PM PDT 24
Peak memory 198772 kb
Host smart-eee264d6-1ec1-43e9-b846-b0eb12d7f120
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847551623 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2847551623
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1009437451
Short name T67
Test name
Test status
Simulation time 11471188 ps
CPU time 0.61 seconds
Started Jun 25 05:39:41 PM PDT 24
Finished Jun 25 05:39:43 PM PDT 24
Peak memory 194012 kb
Host smart-a29db65f-0686-4327-9b37-ffc91eff0068
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009437451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1009437451
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1816112872
Short name T746
Test name
Test status
Simulation time 67928615 ps
CPU time 0.57 seconds
Started Jun 25 05:39:40 PM PDT 24
Finished Jun 25 05:39:43 PM PDT 24
Peak memory 194428 kb
Host smart-38b80b58-be00-4ab3-8e45-bc99dc522732
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816112872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1816112872
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3140485512
Short name T777
Test name
Test status
Simulation time 16044122 ps
CPU time 0.68 seconds
Started Jun 25 05:39:41 PM PDT 24
Finished Jun 25 05:39:43 PM PDT 24
Peak memory 196452 kb
Host smart-7fe2ac4d-043e-407c-8686-b20188580b09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140485512 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3140485512
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3365451934
Short name T725
Test name
Test status
Simulation time 117543122 ps
CPU time 2.2 seconds
Started Jun 25 05:39:47 PM PDT 24
Finished Jun 25 05:39:52 PM PDT 24
Peak memory 198740 kb
Host smart-01db8572-7500-4c76-82d7-73d81cbd0db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365451934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3365451934
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4016185407
Short name T834
Test name
Test status
Simulation time 83353020 ps
CPU time 0.92 seconds
Started Jun 25 05:39:42 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 198452 kb
Host smart-db7f56e9-7ddb-471b-ba46-217ce63c8729
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016185407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4016185407
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1080211391
Short name T806
Test name
Test status
Simulation time 20093414 ps
CPU time 0.85 seconds
Started Jun 25 05:39:42 PM PDT 24
Finished Jun 25 05:39:44 PM PDT 24
Peak memory 198636 kb
Host smart-61ad8ef3-f1d6-499d-a1d1-4bc982793a09
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080211391 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1080211391
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3755152809
Short name T805
Test name
Test status
Simulation time 55482643 ps
CPU time 0.65 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 195648 kb
Host smart-04edab4f-1626-4ca4-b5cf-3fa90ee028b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755152809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3755152809
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3218927934
Short name T793
Test name
Test status
Simulation time 14505698 ps
CPU time 0.59 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 195028 kb
Host smart-059a0526-712c-4f04-b348-5e3ed181cedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218927934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3218927934
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1967586025
Short name T87
Test name
Test status
Simulation time 59737076 ps
CPU time 0.82 seconds
Started Jun 25 05:39:41 PM PDT 24
Finished Jun 25 05:39:43 PM PDT 24
Peak memory 196484 kb
Host smart-9ba770bd-7d82-4a72-82b8-34b3cb06e77c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967586025 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1967586025
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1209189182
Short name T823
Test name
Test status
Simulation time 172905538 ps
CPU time 2.86 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 198736 kb
Host smart-48325ef8-28a2-4522-a301-d88aec267820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209189182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1209189182
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3377059099
Short name T26
Test name
Test status
Simulation time 80345820 ps
CPU time 0.86 seconds
Started Jun 25 05:39:46 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 197940 kb
Host smart-f9710e0e-e3ce-4fb2-8cd0-438502dafbcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377059099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3377059099
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1098576305
Short name T801
Test name
Test status
Simulation time 115227706 ps
CPU time 1.61 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 198804 kb
Host smart-15d98fe3-44b6-4030-bbce-366a073ce648
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098576305 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1098576305
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1381534102
Short name T70
Test name
Test status
Simulation time 16725032 ps
CPU time 0.63 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 195116 kb
Host smart-2103131d-0268-4f0d-a2c9-479b2d2f9404
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381534102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1381534102
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2090994818
Short name T730
Test name
Test status
Simulation time 60504919 ps
CPU time 0.64 seconds
Started Jun 25 05:39:41 PM PDT 24
Finished Jun 25 05:39:43 PM PDT 24
Peak memory 194972 kb
Host smart-d28b8675-3dcd-4d12-95b2-2d18b7d86fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090994818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2090994818
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2308420849
Short name T809
Test name
Test status
Simulation time 14528288 ps
CPU time 0.65 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 195312 kb
Host smart-efa5d6be-f4d1-4104-8a24-64aae54af772
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308420849 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2308420849
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2859697717
Short name T729
Test name
Test status
Simulation time 124095467 ps
CPU time 1.66 seconds
Started Jun 25 05:39:46 PM PDT 24
Finished Jun 25 05:39:50 PM PDT 24
Peak memory 198696 kb
Host smart-664eaa0f-7fca-42d8-aca7-29e95416b340
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859697717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2859697717
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1862149358
Short name T39
Test name
Test status
Simulation time 444457868 ps
CPU time 1.46 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 198768 kb
Host smart-cc4ca293-ae34-40bc-8c0e-e22ee1ee6a9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862149358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1862149358
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4066592711
Short name T826
Test name
Test status
Simulation time 103941620 ps
CPU time 0.79 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 198552 kb
Host smart-c062172d-0bc4-4429-92f1-379db10102e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066592711 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.4066592711
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2743104612
Short name T78
Test name
Test status
Simulation time 15614247 ps
CPU time 0.64 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 195028 kb
Host smart-131f40fc-4bf6-42f3-b26a-7760fe14105a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743104612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2743104612
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.171793919
Short name T798
Test name
Test status
Simulation time 34073872 ps
CPU time 0.62 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 194196 kb
Host smart-6eaac7cb-027e-4ff1-8176-397240335eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171793919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.171793919
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.4180801323
Short name T836
Test name
Test status
Simulation time 90135604 ps
CPU time 0.7 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 195484 kb
Host smart-437a66f7-b72e-4a09-b819-0ef60ecb0ea7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180801323 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.4180801323
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2754270860
Short name T774
Test name
Test status
Simulation time 198732591 ps
CPU time 1.4 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 198720 kb
Host smart-a1a0e241-0237-4b27-9c0d-7133c0517b95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754270860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2754270860
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2989539034
Short name T794
Test name
Test status
Simulation time 144697263 ps
CPU time 0.86 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 197700 kb
Host smart-60146a7f-b6b1-4f95-b4b3-902d91c079db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989539034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2989539034
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2586185809
Short name T744
Test name
Test status
Simulation time 19296661 ps
CPU time 0.82 seconds
Started Jun 25 05:39:47 PM PDT 24
Finished Jun 25 05:39:50 PM PDT 24
Peak memory 198572 kb
Host smart-0f4478df-1121-42b0-a7db-e28c860b8a99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586185809 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2586185809
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3698839050
Short name T76
Test name
Test status
Simulation time 37989971 ps
CPU time 0.66 seconds
Started Jun 25 05:39:41 PM PDT 24
Finished Jun 25 05:39:43 PM PDT 24
Peak memory 195056 kb
Host smart-8df347ae-e5bb-4a84-b634-9c2fb7ef2973
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698839050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3698839050
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.4096305183
Short name T735
Test name
Test status
Simulation time 12842386 ps
CPU time 0.62 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 194476 kb
Host smart-375a7674-5382-4a9e-8796-bdc189bebf15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096305183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.4096305183
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1412984645
Short name T796
Test name
Test status
Simulation time 71080978 ps
CPU time 0.82 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 196716 kb
Host smart-a96dbb65-d761-4b37-8625-48f9d6a55b8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412984645 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1412984645
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1995322097
Short name T720
Test name
Test status
Simulation time 219893879 ps
CPU time 1.41 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 198792 kb
Host smart-ae937929-934a-4878-a04f-8e0a641b72fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995322097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1995322097
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2257328623
Short name T743
Test name
Test status
Simulation time 310726235 ps
CPU time 1.14 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 198768 kb
Host smart-752c443a-f037-4316-a1e9-9768c3cae633
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257328623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2257328623
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2403164301
Short name T738
Test name
Test status
Simulation time 69575661 ps
CPU time 0.89 seconds
Started Jun 25 05:39:42 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 198564 kb
Host smart-35f98d15-8cd5-4237-8381-91d789af97cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403164301 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2403164301
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2644372347
Short name T99
Test name
Test status
Simulation time 40856691 ps
CPU time 0.6 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:45 PM PDT 24
Peak memory 195100 kb
Host smart-b245ed5f-de0d-4314-b8a5-93756427b9cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644372347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2644372347
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2607790987
Short name T832
Test name
Test status
Simulation time 37275138 ps
CPU time 0.62 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 195104 kb
Host smart-49c18df3-99dd-4f38-9bef-9a61190b052a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607790987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2607790987
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1412723430
Short name T785
Test name
Test status
Simulation time 53925559 ps
CPU time 0.9 seconds
Started Jun 25 05:39:47 PM PDT 24
Finished Jun 25 05:39:50 PM PDT 24
Peak memory 197124 kb
Host smart-07200674-137e-4ccc-864b-2e440a12467f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412723430 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1412723430
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.786470357
Short name T827
Test name
Test status
Simulation time 148152086 ps
CPU time 2.41 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 198756 kb
Host smart-3f6d0028-1d43-40ba-8bae-4e61f237d166
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786470357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.786470357
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2644344858
Short name T841
Test name
Test status
Simulation time 93393642 ps
CPU time 1.39 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:51 PM PDT 24
Peak memory 198764 kb
Host smart-776aa1e5-f14e-4ccb-8b08-1ed72f7be95b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644344858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2644344858
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2609905095
Short name T745
Test name
Test status
Simulation time 18382763 ps
CPU time 0.71 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 197216 kb
Host smart-27793e1e-c926-4b94-ba33-d10fcefd4acf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609905095 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2609905095
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4117731217
Short name T68
Test name
Test status
Simulation time 47284714 ps
CPU time 0.58 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 195496 kb
Host smart-2ac6f2a3-7d6d-4ed4-a65a-fc6002abc57e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117731217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4117731217
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3554032746
Short name T752
Test name
Test status
Simulation time 16062712 ps
CPU time 0.63 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 194536 kb
Host smart-3300ade9-01f2-4b92-8cb7-4a8de1b41a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554032746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3554032746
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2934727894
Short name T85
Test name
Test status
Simulation time 98684544 ps
CPU time 0.85 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 197608 kb
Host smart-54b6d734-4fed-4734-868c-c0c152851960
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934727894 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2934727894
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1929735997
Short name T737
Test name
Test status
Simulation time 91690766 ps
CPU time 1.86 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 198748 kb
Host smart-af2f71b0-397b-456b-a676-2bc79738dd56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929735997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1929735997
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3501064020
Short name T813
Test name
Test status
Simulation time 115342853 ps
CPU time 1.56 seconds
Started Jun 25 05:39:47 PM PDT 24
Finished Jun 25 05:39:51 PM PDT 24
Peak memory 198740 kb
Host smart-dfd924b4-2e5a-4763-960b-e1625f5e2e33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501064020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3501064020
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3662095019
Short name T80
Test name
Test status
Simulation time 141553802 ps
CPU time 0.88 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 196700 kb
Host smart-7aec171f-3c57-4e5b-85d6-0cf6e5565230
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662095019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3662095019
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4132046325
Short name T757
Test name
Test status
Simulation time 37823468 ps
CPU time 1.42 seconds
Started Jun 25 05:39:26 PM PDT 24
Finished Jun 25 05:39:29 PM PDT 24
Peak memory 197468 kb
Host smart-6e734d78-14ec-439d-8498-ed4beeeaee84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132046325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4132046325
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1450276552
Short name T81
Test name
Test status
Simulation time 43463877 ps
CPU time 0.7 seconds
Started Jun 25 05:39:28 PM PDT 24
Finished Jun 25 05:39:32 PM PDT 24
Peak memory 195812 kb
Host smart-a4c73732-54ce-4a6f-8950-9743ef5d0c39
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450276552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1450276552
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2430843623
Short name T817
Test name
Test status
Simulation time 24788159 ps
CPU time 1.06 seconds
Started Jun 25 05:39:26 PM PDT 24
Finished Jun 25 05:39:29 PM PDT 24
Peak memory 198604 kb
Host smart-d6388b8b-3548-4e02-ba95-94f9895ebb30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430843623 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2430843623
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.682153524
Short name T811
Test name
Test status
Simulation time 13406849 ps
CPU time 0.61 seconds
Started Jun 25 05:39:32 PM PDT 24
Finished Jun 25 05:39:34 PM PDT 24
Peak memory 195364 kb
Host smart-a68f2a5b-f3d4-4501-b4b3-5f8f8e64f707
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682153524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.682153524
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1837819377
Short name T831
Test name
Test status
Simulation time 11269394 ps
CPU time 0.64 seconds
Started Jun 25 05:39:32 PM PDT 24
Finished Jun 25 05:39:34 PM PDT 24
Peak memory 194472 kb
Host smart-97618202-98c4-48c4-9d02-6faa3d56043d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837819377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1837819377
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2461218630
Short name T86
Test name
Test status
Simulation time 25667667 ps
CPU time 0.74 seconds
Started Jun 25 05:39:27 PM PDT 24
Finished Jun 25 05:39:29 PM PDT 24
Peak memory 195588 kb
Host smart-4501fd47-d23d-4994-8024-acaaf43fd1d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461218630 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2461218630
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2923852467
Short name T772
Test name
Test status
Simulation time 140769988 ps
CPU time 2.08 seconds
Started Jun 25 05:39:32 PM PDT 24
Finished Jun 25 05:39:35 PM PDT 24
Peak memory 198784 kb
Host smart-b3605062-c0fe-4c46-81ae-059ce89ffb58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923852467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2923852467
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.994033754
Short name T25
Test name
Test status
Simulation time 127563683 ps
CPU time 1.18 seconds
Started Jun 25 05:39:25 PM PDT 24
Finished Jun 25 05:39:28 PM PDT 24
Peak memory 198744 kb
Host smart-fd16c107-1709-403d-95e2-0845add0a655
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994033754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.994033754
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3035937330
Short name T751
Test name
Test status
Simulation time 37057458 ps
CPU time 0.6 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 194412 kb
Host smart-301a35a7-c2d3-4f60-9532-78fdc081a548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035937330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3035937330
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2359262129
Short name T830
Test name
Test status
Simulation time 15871131 ps
CPU time 0.63 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 194464 kb
Host smart-701037b6-f93d-41cd-b857-efa51b8da8bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359262129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2359262129
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1279274992
Short name T792
Test name
Test status
Simulation time 49105238 ps
CPU time 0.64 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 194484 kb
Host smart-b11c2833-b9c3-45e1-95bb-1bbc1edb3fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279274992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1279274992
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3230063203
Short name T747
Test name
Test status
Simulation time 46239362 ps
CPU time 0.64 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 194752 kb
Host smart-e25ad748-49a4-4af0-9a7f-5a02408c60a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230063203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3230063203
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.95669526
Short name T762
Test name
Test status
Simulation time 40315502 ps
CPU time 0.62 seconds
Started Jun 25 05:39:47 PM PDT 24
Finished Jun 25 05:39:50 PM PDT 24
Peak memory 194488 kb
Host smart-28d5908b-118f-413a-bb20-89f795f2eb67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95669526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.95669526
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.270063401
Short name T789
Test name
Test status
Simulation time 15123225 ps
CPU time 0.61 seconds
Started Jun 25 05:39:50 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 194476 kb
Host smart-1f3781a5-2c3d-47e1-8ec7-7fd42ee11288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270063401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.270063401
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3099257227
Short name T733
Test name
Test status
Simulation time 47339020 ps
CPU time 0.59 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 194400 kb
Host smart-038d4ff5-3aed-43e5-83c6-41e845df692e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099257227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3099257227
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3376475213
Short name T723
Test name
Test status
Simulation time 104812290 ps
CPU time 0.61 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 194464 kb
Host smart-dcfe677d-be44-49af-b16a-ab6c625ee6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376475213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3376475213
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2384896531
Short name T719
Test name
Test status
Simulation time 16386097 ps
CPU time 0.63 seconds
Started Jun 25 05:39:43 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 195168 kb
Host smart-828b3cb1-97cd-4e5c-89fb-2c3822d66110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384896531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2384896531
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2001194576
Short name T775
Test name
Test status
Simulation time 45975409 ps
CPU time 0.58 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:54 PM PDT 24
Peak memory 194440 kb
Host smart-111391d7-e7e4-487e-848b-2f98f1f15701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001194576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2001194576
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1471453538
Short name T828
Test name
Test status
Simulation time 53151589 ps
CPU time 0.67 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:36 PM PDT 24
Peak memory 194884 kb
Host smart-2c47dae4-8aab-4945-b95b-cac72c555efc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471453538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1471453538
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1115246597
Short name T825
Test name
Test status
Simulation time 186963858 ps
CPU time 1.53 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:41 PM PDT 24
Peak memory 197556 kb
Host smart-6ed43870-87c2-4a8c-8c3c-34e187dc0407
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115246597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1115246597
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2827358980
Short name T778
Test name
Test status
Simulation time 91980443 ps
CPU time 0.65 seconds
Started Jun 25 05:39:39 PM PDT 24
Finished Jun 25 05:39:42 PM PDT 24
Peak memory 195488 kb
Host smart-013b8b0b-a05c-4550-b64a-d3c7cbcde100
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827358980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2827358980
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3564918712
Short name T814
Test name
Test status
Simulation time 56145485 ps
CPU time 1.08 seconds
Started Jun 25 05:39:39 PM PDT 24
Finished Jun 25 05:39:42 PM PDT 24
Peak memory 198568 kb
Host smart-8d499243-b8dc-4353-899a-8736d6c67920
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564918712 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3564918712
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3773951154
Short name T769
Test name
Test status
Simulation time 21436277 ps
CPU time 0.65 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 195560 kb
Host smart-df751a51-ad42-456f-878c-05ab1ea19493
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773951154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3773951154
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3650984117
Short name T779
Test name
Test status
Simulation time 44652042 ps
CPU time 0.61 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:38 PM PDT 24
Peak memory 194468 kb
Host smart-9dffc7cb-a3ba-408b-9655-6eebf5e030ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650984117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3650984117
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.484942766
Short name T66
Test name
Test status
Simulation time 82147137 ps
CPU time 0.77 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 197480 kb
Host smart-20a03c58-15ef-49b3-9674-c7a1972d2d5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484942766 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.484942766
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.165119094
Short name T764
Test name
Test status
Simulation time 208991102 ps
CPU time 2.84 seconds
Started Jun 25 05:39:33 PM PDT 24
Finished Jun 25 05:39:37 PM PDT 24
Peak memory 198716 kb
Host smart-b089e720-b0d7-4f0a-84e4-34c8062638c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165119094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.165119094
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3296450067
Short name T797
Test name
Test status
Simulation time 27932620 ps
CPU time 0.59 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 195056 kb
Host smart-5d0127a6-e9e0-4cd9-a7e9-df27520cf305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296450067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3296450067
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3227452232
Short name T721
Test name
Test status
Simulation time 95353854 ps
CPU time 0.63 seconds
Started Jun 25 05:39:50 PM PDT 24
Finished Jun 25 05:39:52 PM PDT 24
Peak memory 194432 kb
Host smart-835b4ae7-44ec-423e-8db5-fa505c44a52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227452232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3227452232
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3609724893
Short name T829
Test name
Test status
Simulation time 30683029 ps
CPU time 0.61 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 194424 kb
Host smart-58a1a043-8172-4cca-abf0-984d920b5991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609724893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3609724893
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3176894123
Short name T766
Test name
Test status
Simulation time 40343542 ps
CPU time 0.58 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 194416 kb
Host smart-48112e1e-3731-42a2-b2e3-347cd4e67431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176894123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3176894123
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.799974439
Short name T803
Test name
Test status
Simulation time 22439400 ps
CPU time 0.63 seconds
Started Jun 25 05:39:50 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 194444 kb
Host smart-f3a086bc-2a52-4b85-a9bd-838e97876197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799974439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.799974439
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3727178866
Short name T760
Test name
Test status
Simulation time 12347885 ps
CPU time 0.63 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 195120 kb
Host smart-992d6aa7-beb9-41c4-88cc-39cbf7dec70c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727178866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3727178866
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.482676855
Short name T722
Test name
Test status
Simulation time 14576707 ps
CPU time 0.59 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 194440 kb
Host smart-a90b461d-1c83-4984-aa18-87c0ea055b88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482676855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.482676855
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1586106315
Short name T818
Test name
Test status
Simulation time 106866695 ps
CPU time 0.67 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:47 PM PDT 24
Peak memory 195056 kb
Host smart-de424446-b450-42c0-8138-b791f0ff48e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586106315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1586106315
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2704216069
Short name T838
Test name
Test status
Simulation time 18438729 ps
CPU time 0.62 seconds
Started Jun 25 05:39:50 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 195080 kb
Host smart-caa60705-3d41-491c-a045-82d354b4b50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704216069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2704216069
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1742557201
Short name T740
Test name
Test status
Simulation time 22880504 ps
CPU time 0.62 seconds
Started Jun 25 05:39:50 PM PDT 24
Finished Jun 25 05:39:52 PM PDT 24
Peak memory 195000 kb
Host smart-40681466-7c70-4d1b-a8cb-3e9bcf52700d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742557201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1742557201
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2078790351
Short name T64
Test name
Test status
Simulation time 104117215 ps
CPU time 0.83 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 197292 kb
Host smart-6239d908-a97f-42be-a0b8-a11464a71ab1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078790351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2078790351
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3809105486
Short name T773
Test name
Test status
Simulation time 196344883 ps
CPU time 1.47 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:38 PM PDT 24
Peak memory 197512 kb
Host smart-c0e6b393-25c8-47c3-add8-075050481064
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809105486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3809105486
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1775491146
Short name T786
Test name
Test status
Simulation time 38071649 ps
CPU time 0.68 seconds
Started Jun 25 05:39:39 PM PDT 24
Finished Jun 25 05:39:42 PM PDT 24
Peak memory 195312 kb
Host smart-1e958d7f-73f3-4a7b-80b2-d0f382edded2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775491146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1775491146
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.36035682
Short name T787
Test name
Test status
Simulation time 21636390 ps
CPU time 0.81 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 198064 kb
Host smart-653b01a6-d5ab-47ee-bb02-fb7951184f62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36035682 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.36035682
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2324949748
Short name T79
Test name
Test status
Simulation time 45403172 ps
CPU time 0.62 seconds
Started Jun 25 05:39:33 PM PDT 24
Finished Jun 25 05:39:35 PM PDT 24
Peak memory 196152 kb
Host smart-8360347b-3cc8-4a2d-9e84-0c2bf90869a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324949748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2324949748
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1166481510
Short name T748
Test name
Test status
Simulation time 62831231 ps
CPU time 0.63 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:38 PM PDT 24
Peak memory 194544 kb
Host smart-bd4cb804-f2e3-4d7e-b965-9f9a73c94310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166481510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1166481510
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.302349470
Short name T804
Test name
Test status
Simulation time 124353179 ps
CPU time 0.79 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 198524 kb
Host smart-bae214ed-6f86-4e4e-8eef-6e31eb8a57ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302349470 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.302349470
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1785654206
Short name T782
Test name
Test status
Simulation time 38459121 ps
CPU time 2.08 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:37 PM PDT 24
Peak memory 198780 kb
Host smart-e721eefa-626d-477a-a8b4-14ed7f8d1e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785654206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1785654206
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.873149323
Short name T33
Test name
Test status
Simulation time 326796134 ps
CPU time 1.22 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 198716 kb
Host smart-f38d76cb-530c-403c-9f25-9c8e5731a89a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873149323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.873149323
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1429156078
Short name T816
Test name
Test status
Simulation time 30510996 ps
CPU time 0.6 seconds
Started Jun 25 05:39:44 PM PDT 24
Finished Jun 25 05:39:48 PM PDT 24
Peak memory 194476 kb
Host smart-5560e480-bb13-4136-9d1c-410840105f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429156078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1429156078
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2071834866
Short name T820
Test name
Test status
Simulation time 14884352 ps
CPU time 0.58 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:55 PM PDT 24
Peak memory 194436 kb
Host smart-f8a3db06-3659-4079-92b9-2e74615aed2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071834866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2071834866
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1399455081
Short name T731
Test name
Test status
Simulation time 61684322 ps
CPU time 0.63 seconds
Started Jun 25 05:39:50 PM PDT 24
Finished Jun 25 05:39:52 PM PDT 24
Peak memory 194460 kb
Host smart-2a3b1f76-1f48-46ed-8d3d-6c975de919ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399455081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1399455081
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4219274523
Short name T780
Test name
Test status
Simulation time 27929040 ps
CPU time 0.62 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 194504 kb
Host smart-45a9f315-34f1-413c-b626-058fafcc449e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219274523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4219274523
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2056204681
Short name T808
Test name
Test status
Simulation time 13812476 ps
CPU time 0.6 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:58 PM PDT 24
Peak memory 194404 kb
Host smart-53f72e52-82b3-4b87-bb0b-1842385436ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056204681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2056204681
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1591597871
Short name T776
Test name
Test status
Simulation time 29780931 ps
CPU time 0.63 seconds
Started Jun 25 05:39:50 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 194520 kb
Host smart-a4f684e8-7088-4203-96c8-d98eaa2de116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591597871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1591597871
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3742133388
Short name T763
Test name
Test status
Simulation time 25572693 ps
CPU time 0.65 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 194472 kb
Host smart-3cc227da-1043-4e5f-8b02-174b7091f1c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742133388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3742133388
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3548857946
Short name T807
Test name
Test status
Simulation time 38221931 ps
CPU time 0.59 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 195032 kb
Host smart-c0e0c6b5-0976-4371-8bd1-e1db8b6972be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548857946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3548857946
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3582201062
Short name T821
Test name
Test status
Simulation time 44199804 ps
CPU time 0.6 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 194432 kb
Host smart-93b3cac8-857e-41ba-bb91-e67a6612112d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582201062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3582201062
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.480147066
Short name T770
Test name
Test status
Simulation time 23684793 ps
CPU time 0.61 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 194528 kb
Host smart-bb095af0-040b-4c16-b414-704c97d99d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480147066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.480147066
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1000433616
Short name T784
Test name
Test status
Simulation time 150103125 ps
CPU time 0.97 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 198612 kb
Host smart-89147121-d9fc-480d-a6d3-618cb07caeb5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000433616 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1000433616
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3914546600
Short name T755
Test name
Test status
Simulation time 38412303 ps
CPU time 0.59 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:38 PM PDT 24
Peak memory 195376 kb
Host smart-13dcc8f2-9bfb-41c5-89ad-b824d9d8a85f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914546600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3914546600
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3201027544
Short name T839
Test name
Test status
Simulation time 50049430 ps
CPU time 0.6 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:37 PM PDT 24
Peak memory 194388 kb
Host smart-eb754d24-ce54-473f-94e1-074a41e24cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201027544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3201027544
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.622530746
Short name T812
Test name
Test status
Simulation time 39715917 ps
CPU time 0.72 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:36 PM PDT 24
Peak memory 195872 kb
Host smart-bd9e3800-1649-45ff-9176-5c4ee1ea3867
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622530746 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.622530746
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1171503588
Short name T749
Test name
Test status
Simulation time 29236020 ps
CPU time 1.43 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:37 PM PDT 24
Peak memory 198756 kb
Host smart-ca45681e-7279-451c-8fd5-8f434e282b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171503588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1171503588
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3190993495
Short name T36
Test name
Test status
Simulation time 109677847 ps
CPU time 1.44 seconds
Started Jun 25 05:39:35 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 198768 kb
Host smart-7a5ba004-eaf7-4a8c-85e5-ab48af69b6bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190993495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3190993495
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1517672698
Short name T819
Test name
Test status
Simulation time 45223603 ps
CPU time 1.04 seconds
Started Jun 25 05:39:39 PM PDT 24
Finished Jun 25 05:39:42 PM PDT 24
Peak memory 198420 kb
Host smart-85d6af28-c442-4b10-80ef-69178cdfb0cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517672698 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1517672698
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1079537903
Short name T761
Test name
Test status
Simulation time 15394199 ps
CPU time 0.59 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 195364 kb
Host smart-af6dd364-98fc-47c9-960c-44c592a4c1ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079537903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1079537903
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.233234086
Short name T717
Test name
Test status
Simulation time 26743000 ps
CPU time 0.63 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 194532 kb
Host smart-71e9b1e9-1c21-4dbe-a2b5-5781ef81ff77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233234086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.233234086
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.685094412
Short name T840
Test name
Test status
Simulation time 56166769 ps
CPU time 0.68 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:37 PM PDT 24
Peak memory 195708 kb
Host smart-5064e5d3-6f57-4c80-8bec-0c49b8140dff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685094412 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.685094412
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2502999018
Short name T728
Test name
Test status
Simulation time 85765842 ps
CPU time 2.05 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 198804 kb
Host smart-c3229025-6524-49da-9681-5b25cae846e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502999018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2502999018
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.4149582464
Short name T40
Test name
Test status
Simulation time 79856658 ps
CPU time 1.22 seconds
Started Jun 25 05:39:32 PM PDT 24
Finished Jun 25 05:39:34 PM PDT 24
Peak memory 198708 kb
Host smart-2a0d3c73-8bed-4c9d-b3e0-6320eb5bce18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149582464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.4149582464
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1619672244
Short name T724
Test name
Test status
Simulation time 164231864 ps
CPU time 0.66 seconds
Started Jun 25 05:39:37 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 197072 kb
Host smart-29267c94-c710-4457-95f1-205f78e34379
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619672244 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1619672244
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.789526833
Short name T83
Test name
Test status
Simulation time 13728625 ps
CPU time 0.65 seconds
Started Jun 25 05:39:33 PM PDT 24
Finished Jun 25 05:39:34 PM PDT 24
Peak memory 195388 kb
Host smart-c1692e1c-44a1-46e6-b38d-4f2ae703c1a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789526833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.789526833
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1974903593
Short name T799
Test name
Test status
Simulation time 14273939 ps
CPU time 0.61 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 195080 kb
Host smart-79587496-d1bb-48da-a340-c5b8649c186b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974903593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1974903593
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3909630282
Short name T71
Test name
Test status
Simulation time 37933027 ps
CPU time 0.65 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:37 PM PDT 24
Peak memory 195668 kb
Host smart-3601e73a-27c2-489d-b57f-57125372699c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909630282 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3909630282
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.104609456
Short name T767
Test name
Test status
Simulation time 690735106 ps
CPU time 2.69 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 198708 kb
Host smart-f08df997-2bbb-494b-a82f-143a92b7307d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104609456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.104609456
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.594497500
Short name T788
Test name
Test status
Simulation time 116726585 ps
CPU time 1.55 seconds
Started Jun 25 05:39:33 PM PDT 24
Finished Jun 25 05:39:36 PM PDT 24
Peak memory 198740 kb
Host smart-9ea426ad-5ec5-4cab-abd9-5fd3815564fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594497500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.594497500
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1794387158
Short name T726
Test name
Test status
Simulation time 40465585 ps
CPU time 1.06 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 198608 kb
Host smart-bde9b54b-72e7-4609-ba68-1e662848ec66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794387158 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1794387158
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1811272382
Short name T758
Test name
Test status
Simulation time 30630371 ps
CPU time 0.62 seconds
Started Jun 25 05:39:39 PM PDT 24
Finished Jun 25 05:39:42 PM PDT 24
Peak memory 195928 kb
Host smart-fd7b8446-87ae-405c-ae3f-542a4731b6d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811272382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1811272382
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3232922464
Short name T765
Test name
Test status
Simulation time 20934944 ps
CPU time 0.65 seconds
Started Jun 25 05:39:33 PM PDT 24
Finished Jun 25 05:39:35 PM PDT 24
Peak memory 194528 kb
Host smart-62ca64b8-8359-48ca-ac2e-339da56b679f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232922464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3232922464
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.925847860
Short name T84
Test name
Test status
Simulation time 35128462 ps
CPU time 0.84 seconds
Started Jun 25 05:39:34 PM PDT 24
Finished Jun 25 05:39:36 PM PDT 24
Peak memory 197016 kb
Host smart-8f5e6ed0-4ecb-4187-9c01-2391a9f14933
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925847860 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.925847860
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.4150601190
Short name T741
Test name
Test status
Simulation time 166583684 ps
CPU time 3.07 seconds
Started Jun 25 05:39:39 PM PDT 24
Finished Jun 25 05:39:44 PM PDT 24
Peak memory 198752 kb
Host smart-abd065e3-2a36-4431-819e-0cd1d3a2de00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150601190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.4150601190
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3560824755
Short name T100
Test name
Test status
Simulation time 70437237 ps
CPU time 1.11 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 198344 kb
Host smart-205f033c-c01a-4f7f-b4ef-123590f2cbbf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560824755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3560824755
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.311016585
Short name T756
Test name
Test status
Simulation time 14866466 ps
CPU time 0.75 seconds
Started Jun 25 05:39:37 PM PDT 24
Finished Jun 25 05:39:41 PM PDT 24
Peak memory 198572 kb
Host smart-ef5dad6d-4b79-4177-8c54-75730fe9155e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311016585 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.311016585
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2721884211
Short name T73
Test name
Test status
Simulation time 29917173 ps
CPU time 0.66 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 195488 kb
Host smart-2a883f7b-1bf7-41b0-915f-a189cfc99648
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721884211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2721884211
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.353930573
Short name T718
Test name
Test status
Simulation time 12808927 ps
CPU time 0.6 seconds
Started Jun 25 05:39:45 PM PDT 24
Finished Jun 25 05:39:49 PM PDT 24
Peak memory 195036 kb
Host smart-1b474fbb-984b-438b-804f-9e65b945396f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353930573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.353930573
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2097901097
Short name T833
Test name
Test status
Simulation time 69839580 ps
CPU time 0.71 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:39 PM PDT 24
Peak memory 196428 kb
Host smart-9b23c128-1f98-4d8b-872b-37fe555eccce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097901097 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2097901097
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1713155146
Short name T842
Test name
Test status
Simulation time 261293228 ps
CPU time 1.43 seconds
Started Jun 25 05:39:42 PM PDT 24
Finished Jun 25 05:39:46 PM PDT 24
Peak memory 198772 kb
Host smart-ef2e9514-72f6-4bbe-869e-861e4b655ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713155146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1713155146
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2883189746
Short name T824
Test name
Test status
Simulation time 100125495 ps
CPU time 0.88 seconds
Started Jun 25 05:39:36 PM PDT 24
Finished Jun 25 05:39:40 PM PDT 24
Peak memory 197636 kb
Host smart-3f774d06-f665-4baa-851a-be70eea696a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883189746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2883189746
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2246085874
Short name T661
Test name
Test status
Simulation time 16633792 ps
CPU time 0.57 seconds
Started Jun 25 05:40:22 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 195380 kb
Host smart-a2223c83-b148-4aa0-9445-3d377fe22834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246085874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2246085874
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.149400312
Short name T522
Test name
Test status
Simulation time 89974306 ps
CPU time 0.92 seconds
Started Jun 25 05:40:02 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 197288 kb
Host smart-0ee4aaa0-54fc-4b47-9ae8-24ec687b46a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149400312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.149400312
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.822532319
Short name T518
Test name
Test status
Simulation time 1555573613 ps
CPU time 4.97 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:12 PM PDT 24
Peak memory 197780 kb
Host smart-c336023d-ac8f-4c98-8e78-1d66c1fad8bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822532319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.822532319
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1981524306
Short name T540
Test name
Test status
Simulation time 448312138 ps
CPU time 0.78 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:13 PM PDT 24
Peak memory 196492 kb
Host smart-ac98829d-f3ac-4437-953c-8a0f895c263e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981524306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1981524306
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2082090569
Short name T616
Test name
Test status
Simulation time 38816992 ps
CPU time 0.78 seconds
Started Jun 25 05:40:12 PM PDT 24
Finished Jun 25 05:40:14 PM PDT 24
Peak memory 196216 kb
Host smart-5c6e8f95-7840-472a-933c-1e7178999cc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082090569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2082090569
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.879202266
Short name T180
Test name
Test status
Simulation time 72301556 ps
CPU time 2.79 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 196996 kb
Host smart-180c4f92-b9a3-4e22-95db-c9140c69ff9a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879202266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.879202266
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2610808930
Short name T267
Test name
Test status
Simulation time 138675190 ps
CPU time 2.22 seconds
Started Jun 25 05:40:07 PM PDT 24
Finished Jun 25 05:40:11 PM PDT 24
Peak memory 196540 kb
Host smart-9a07fb91-7331-4365-be15-2ea2b8827ea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610808930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2610808930
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3125785645
Short name T447
Test name
Test status
Simulation time 36148295 ps
CPU time 0.89 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 196160 kb
Host smart-9c4e16ca-bd28-4ac3-b9b4-ccb5e756fc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125785645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3125785645
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1871335749
Short name T622
Test name
Test status
Simulation time 113652309 ps
CPU time 0.94 seconds
Started Jun 25 05:40:04 PM PDT 24
Finished Jun 25 05:40:07 PM PDT 24
Peak memory 196632 kb
Host smart-df4b8f13-16dc-4133-9dc9-a9174c82958a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871335749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1871335749
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2504354050
Short name T620
Test name
Test status
Simulation time 1318856595 ps
CPU time 3.75 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 198676 kb
Host smart-4510f705-b80d-4327-8873-beaca0cb18dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504354050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2504354050
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2214262256
Short name T42
Test name
Test status
Simulation time 253374741 ps
CPU time 0.89 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:40:18 PM PDT 24
Peak memory 214380 kb
Host smart-769a8ef9-416b-44cf-8d38-b2d490eddfd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214262256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2214262256
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.4281766362
Short name T608
Test name
Test status
Simulation time 210099468 ps
CPU time 1.02 seconds
Started Jun 25 05:40:02 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 196544 kb
Host smart-01752040-c529-4f6d-8ea8-8e16d66652be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281766362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.4281766362
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4136367130
Short name T359
Test name
Test status
Simulation time 85034605 ps
CPU time 0.82 seconds
Started Jun 25 05:40:02 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 196608 kb
Host smart-a0c1aa61-cb75-4712-ab77-80b5c378b9bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136367130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4136367130
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3066524123
Short name T330
Test name
Test status
Simulation time 5956806598 ps
CPU time 41.57 seconds
Started Jun 25 05:40:18 PM PDT 24
Finished Jun 25 05:41:00 PM PDT 24
Peak memory 198760 kb
Host smart-1e2e9c53-0c90-4339-8f82-0448939258ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066524123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3066524123
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.2291248794
Short name T54
Test name
Test status
Simulation time 206583062521 ps
CPU time 1321.41 seconds
Started Jun 25 05:40:07 PM PDT 24
Finished Jun 25 06:02:10 PM PDT 24
Peak memory 198940 kb
Host smart-4d84a49b-be27-41a8-9b25-0be33a429459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2291248794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.2291248794
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2219252220
Short name T360
Test name
Test status
Simulation time 11925357 ps
CPU time 0.64 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 195380 kb
Host smart-4ab221c6-0a97-4a46-bc7a-c272989add1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219252220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2219252220
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.982410332
Short name T621
Test name
Test status
Simulation time 91572648 ps
CPU time 0.72 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 195532 kb
Host smart-1fd9d2bd-5694-43ea-a0b3-8af63b06fc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982410332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.982410332
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.375969984
Short name T561
Test name
Test status
Simulation time 310839254 ps
CPU time 14.18 seconds
Started Jun 25 05:40:11 PM PDT 24
Finished Jun 25 05:40:27 PM PDT 24
Peak memory 197700 kb
Host smart-38901002-57db-4154-97b6-3edcbc56c1f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375969984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.375969984
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.4226075400
Short name T336
Test name
Test status
Simulation time 105102352 ps
CPU time 1.01 seconds
Started Jun 25 05:40:07 PM PDT 24
Finished Jun 25 05:40:10 PM PDT 24
Peak memory 197272 kb
Host smart-473daa3e-8aff-43ab-aea6-6fb61a7f5f68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226075400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.4226075400
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1761464200
Short name T16
Test name
Test status
Simulation time 50329640 ps
CPU time 1.52 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:13 PM PDT 24
Peak memory 196516 kb
Host smart-83d36d32-4a86-42cf-a6af-16e70f804c85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761464200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1761464200
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.606892712
Short name T184
Test name
Test status
Simulation time 39676907 ps
CPU time 1.48 seconds
Started Jun 25 05:40:09 PM PDT 24
Finished Jun 25 05:40:12 PM PDT 24
Peak memory 197148 kb
Host smart-9bbcc064-1412-4e27-ac52-f06f24fd467a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606892712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.606892712
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3134876700
Short name T697
Test name
Test status
Simulation time 564548545 ps
CPU time 3.14 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:22 PM PDT 24
Peak memory 197728 kb
Host smart-1f8ab1eb-5254-4bb4-9814-d8578a2f58a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134876700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3134876700
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3283996857
Short name T137
Test name
Test status
Simulation time 210113905 ps
CPU time 1.09 seconds
Started Jun 25 05:40:11 PM PDT 24
Finished Jun 25 05:40:14 PM PDT 24
Peak memory 197428 kb
Host smart-801d6773-051e-4d04-b1b0-29d2b296c179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283996857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3283996857
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1225920212
Short name T207
Test name
Test status
Simulation time 43009237 ps
CPU time 0.78 seconds
Started Jun 25 05:40:18 PM PDT 24
Finished Jun 25 05:40:21 PM PDT 24
Peak memory 196884 kb
Host smart-3b8a5cc6-1437-40e6-8509-c8d04a3b862e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225920212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1225920212
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1445224441
Short name T521
Test name
Test status
Simulation time 1351620101 ps
CPU time 4.66 seconds
Started Jun 25 05:40:08 PM PDT 24
Finished Jun 25 05:40:14 PM PDT 24
Peak memory 198660 kb
Host smart-4293fae5-a9f7-4b1f-8f3e-aa7e05ee53bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445224441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1445224441
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2207117530
Short name T29
Test name
Test status
Simulation time 106986715 ps
CPU time 0.87 seconds
Started Jun 25 05:40:20 PM PDT 24
Finished Jun 25 05:40:23 PM PDT 24
Peak memory 214272 kb
Host smart-9f14748a-c4f1-40e0-98e7-934591b3384a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207117530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2207117530
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3599795894
Short name T239
Test name
Test status
Simulation time 685000835 ps
CPU time 1.3 seconds
Started Jun 25 05:40:19 PM PDT 24
Finished Jun 25 05:40:21 PM PDT 24
Peak memory 197328 kb
Host smart-57b60e48-8942-4cef-9e07-710a5645d5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599795894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3599795894
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3542373768
Short name T585
Test name
Test status
Simulation time 127832962 ps
CPU time 1.04 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:12 PM PDT 24
Peak memory 196524 kb
Host smart-45ddfced-2a4f-4ccb-aacf-315696ffff2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542373768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3542373768
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1507326732
Short name T342
Test name
Test status
Simulation time 15779237620 ps
CPU time 210.38 seconds
Started Jun 25 05:40:09 PM PDT 24
Finished Jun 25 05:43:41 PM PDT 24
Peak memory 198804 kb
Host smart-4c1332d8-077c-4076-88c4-ad0f54aa6501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507326732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1507326732
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.111893181
Short name T261
Test name
Test status
Simulation time 11908857 ps
CPU time 0.56 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:30 PM PDT 24
Peak memory 194676 kb
Host smart-35dff8d0-1c2f-49c4-905b-75812e1405e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111893181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.111893181
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1434788722
Short name T297
Test name
Test status
Simulation time 146718281 ps
CPU time 0.88 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:40:28 PM PDT 24
Peak memory 196512 kb
Host smart-9bca89d4-8fc0-4b90-b845-58a031e8241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434788722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1434788722
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2761476582
Short name T143
Test name
Test status
Simulation time 2394600195 ps
CPU time 19.56 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:51 PM PDT 24
Peak memory 197716 kb
Host smart-dee6fb9d-e3c2-4332-b6a2-ff36254cc96e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761476582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2761476582
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1762612112
Short name T638
Test name
Test status
Simulation time 224781326 ps
CPU time 0.74 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:40:44 PM PDT 24
Peak memory 195348 kb
Host smart-1dd8ed10-ee3c-49fb-be1d-5a3488510944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762612112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1762612112
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4135930750
Short name T108
Test name
Test status
Simulation time 116234249 ps
CPU time 1.14 seconds
Started Jun 25 05:40:32 PM PDT 24
Finished Jun 25 05:40:34 PM PDT 24
Peak memory 196468 kb
Host smart-6c3437a0-dff3-493f-bfed-60ca7c9c79f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135930750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4135930750
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1147471402
Short name T155
Test name
Test status
Simulation time 163384583 ps
CPU time 1.92 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 196664 kb
Host smart-1cf3dcea-69af-4b1c-9b26-cd95598f0d53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147471402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1147471402
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3713935221
Short name T163
Test name
Test status
Simulation time 254836063 ps
CPU time 0.99 seconds
Started Jun 25 05:40:24 PM PDT 24
Finished Jun 25 05:40:26 PM PDT 24
Peak memory 196720 kb
Host smart-ed0a87e7-9620-4258-b5a3-a3798250aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713935221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3713935221
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3176095240
Short name T480
Test name
Test status
Simulation time 238794705 ps
CPU time 1.08 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:40:27 PM PDT 24
Peak memory 196724 kb
Host smart-8a9601ea-78cd-4730-9aee-762da6a309d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176095240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3176095240
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1714894223
Short name T266
Test name
Test status
Simulation time 665092587 ps
CPU time 5.34 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 198712 kb
Host smart-9b7f7f3e-9725-4464-be69-da92b0683d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714894223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1714894223
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.13335424
Short name T338
Test name
Test status
Simulation time 31428831 ps
CPU time 0.94 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:33 PM PDT 24
Peak memory 197252 kb
Host smart-d79e3117-570e-46ef-af90-08a147d1ef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13335424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.13335424
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2775379638
Short name T535
Test name
Test status
Simulation time 104214327 ps
CPU time 0.96 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:40:28 PM PDT 24
Peak memory 196432 kb
Host smart-d403fe12-ea67-4d1d-8e4e-f6e770777303
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775379638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2775379638
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2168329149
Short name T619
Test name
Test status
Simulation time 2264694759 ps
CPU time 32.79 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 198812 kb
Host smart-be14e38e-09b0-428e-a0aa-8846947b11e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168329149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2168329149
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1699930002
Short name T602
Test name
Test status
Simulation time 17943748 ps
CPU time 0.61 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:30 PM PDT 24
Peak memory 194896 kb
Host smart-9c263ed4-7abe-40c7-b90a-050a10571b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699930002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1699930002
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3964242093
Short name T199
Test name
Test status
Simulation time 42668671 ps
CPU time 0.77 seconds
Started Jun 25 05:40:33 PM PDT 24
Finished Jun 25 05:40:35 PM PDT 24
Peak memory 196636 kb
Host smart-53fde8ff-660d-4663-8d80-a9fe955a1660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964242093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3964242093
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1190618222
Short name T453
Test name
Test status
Simulation time 289496889 ps
CPU time 15.64 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:40:42 PM PDT 24
Peak memory 197832 kb
Host smart-60e37b54-6918-45ab-a795-70e69df6280b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190618222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1190618222
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.949831087
Short name T110
Test name
Test status
Simulation time 142559136 ps
CPU time 0.99 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 198424 kb
Host smart-dbe1206b-65eb-4a66-9647-25341e1838e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949831087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.949831087
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3952619913
Short name T232
Test name
Test status
Simulation time 168515473 ps
CPU time 0.92 seconds
Started Jun 25 05:40:30 PM PDT 24
Finished Jun 25 05:40:33 PM PDT 24
Peak memory 197916 kb
Host smart-19332420-8d92-453f-ad83-601855db02ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952619913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3952619913
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2373082710
Short name T547
Test name
Test status
Simulation time 172415050 ps
CPU time 1.95 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:34 PM PDT 24
Peak memory 198740 kb
Host smart-8d336bb5-b4f9-4e6c-b41c-cc81024191dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373082710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2373082710
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1010439482
Short name T123
Test name
Test status
Simulation time 336568737 ps
CPU time 2.65 seconds
Started Jun 25 05:40:33 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 198720 kb
Host smart-38c2054f-fff8-422b-a886-1d1a907c0b87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010439482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1010439482
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1166905512
Short name T221
Test name
Test status
Simulation time 405696152 ps
CPU time 1.21 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 196772 kb
Host smart-f259f2f2-2664-4c88-bd27-0506ecd284af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166905512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1166905512
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2349030919
Short name T217
Test name
Test status
Simulation time 81022190 ps
CPU time 1.14 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 198684 kb
Host smart-27f14902-7ab9-4ae7-9360-f48f0f539995
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349030919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2349030919
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3627538275
Short name T407
Test name
Test status
Simulation time 703909819 ps
CPU time 2.97 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:33 PM PDT 24
Peak memory 198656 kb
Host smart-b81cb16d-be1b-4c05-9959-4502124c61df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627538275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3627538275
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2620561988
Short name T47
Test name
Test status
Simulation time 208584046 ps
CPU time 0.88 seconds
Started Jun 25 05:40:31 PM PDT 24
Finished Jun 25 05:40:34 PM PDT 24
Peak memory 197172 kb
Host smart-331b4173-06dc-4853-b581-1a7930a88b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620561988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2620561988
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.1037466754
Short name T97
Test name
Test status
Simulation time 219456441 ps
CPU time 1.13 seconds
Started Jun 25 05:40:33 PM PDT 24
Finished Jun 25 05:40:35 PM PDT 24
Peak memory 196224 kb
Host smart-53e4d7c5-d942-4c69-8bf0-13657ae8d681
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037466754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.1037466754
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.642785637
Short name T341
Test name
Test status
Simulation time 6484346913 ps
CPU time 36.6 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 198816 kb
Host smart-77033957-d365-44f1-8316-e30eca1334b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642785637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.642785637
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2830077521
Short name T703
Test name
Test status
Simulation time 47267129 ps
CPU time 0.69 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 194712 kb
Host smart-962defe3-37d1-458d-aa5c-3cc889036de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830077521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2830077521
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.338520289
Short name T625
Test name
Test status
Simulation time 807028416 ps
CPU time 24.6 seconds
Started Jun 25 05:40:30 PM PDT 24
Finished Jun 25 05:40:57 PM PDT 24
Peak memory 198700 kb
Host smart-4dfc9527-9b36-47e6-a5b6-b13d93ecea8a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338520289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.338520289
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1355781846
Short name T209
Test name
Test status
Simulation time 60537566 ps
CPU time 0.72 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:29 PM PDT 24
Peak memory 197268 kb
Host smart-f82b0e9a-a69d-4781-b21c-e60ba056a7e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355781846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1355781846
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.384813423
Short name T460
Test name
Test status
Simulation time 35653887 ps
CPU time 0.85 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:40:29 PM PDT 24
Peak memory 196992 kb
Host smart-d137e079-8948-4954-b1a5-a1fecead4cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384813423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.384813423
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3246611974
Short name T415
Test name
Test status
Simulation time 285680215 ps
CPU time 3.14 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:33 PM PDT 24
Peak memory 198804 kb
Host smart-bd73dc64-2cea-4b6d-b784-86b6f4e3f4e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246611974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3246611974
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.348627383
Short name T194
Test name
Test status
Simulation time 421778187 ps
CPU time 2.17 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 196784 kb
Host smart-b963eaa3-83a4-46dc-aef6-ea315c7c3a25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348627383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
348627383
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2471849916
Short name T319
Test name
Test status
Simulation time 27638369 ps
CPU time 1.11 seconds
Started Jun 25 05:40:33 PM PDT 24
Finished Jun 25 05:40:35 PM PDT 24
Peak memory 196696 kb
Host smart-d6570a19-835d-416e-8bec-ef95a8995dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471849916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2471849916
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1807132322
Short name T634
Test name
Test status
Simulation time 67340966 ps
CPU time 1.45 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 196808 kb
Host smart-fb56d32f-d49a-4366-9d20-ce187b6af4a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807132322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1807132322
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.198772982
Short name T434
Test name
Test status
Simulation time 964304012 ps
CPU time 3.5 seconds
Started Jun 25 05:40:33 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 198640 kb
Host smart-12ef1521-0edc-4550-bdc9-3e9fb7cfbb57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198772982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.198772982
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1883546402
Short name T109
Test name
Test status
Simulation time 70727978 ps
CPU time 1.18 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 197512 kb
Host smart-378d3fef-b4c7-4080-b34e-528f674cbdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883546402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1883546402
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2678354406
Short name T219
Test name
Test status
Simulation time 91168271 ps
CPU time 1.32 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 197136 kb
Host smart-4cc3f879-54f9-437b-98e4-e37558b04b3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678354406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2678354406
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.454638429
Short name T10
Test name
Test status
Simulation time 75015562843 ps
CPU time 162.14 seconds
Started Jun 25 05:40:35 PM PDT 24
Finished Jun 25 05:43:18 PM PDT 24
Peak memory 198780 kb
Host smart-21510d02-f558-4712-a840-0775865cc491
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454638429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.454638429
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.3425960720
Short name T684
Test name
Test status
Simulation time 616202799386 ps
CPU time 1984.15 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 06:13:50 PM PDT 24
Peak memory 198928 kb
Host smart-1e7d8aac-0224-4c70-8c64-a3b662e30692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3425960720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.3425960720
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1533399278
Short name T241
Test name
Test status
Simulation time 22029790 ps
CPU time 0.62 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:48 PM PDT 24
Peak memory 194868 kb
Host smart-7db4938f-0b70-4698-86e4-2dd29f336149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533399278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1533399278
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2778512577
Short name T21
Test name
Test status
Simulation time 24099302 ps
CPU time 0.74 seconds
Started Jun 25 05:40:48 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 194656 kb
Host smart-5f295e2e-b402-4cc1-a8a0-97ee299f2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778512577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2778512577
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2264678379
Short name T549
Test name
Test status
Simulation time 716651896 ps
CPU time 26.16 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:41:15 PM PDT 24
Peak memory 197892 kb
Host smart-0ab2ae1b-532c-4096-8575-75fb4b22d287
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264678379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2264678379
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3728253679
Short name T285
Test name
Test status
Simulation time 85381277 ps
CPU time 1.1 seconds
Started Jun 25 05:40:39 PM PDT 24
Finished Jun 25 05:40:41 PM PDT 24
Peak memory 197320 kb
Host smart-f527c4cb-d927-4527-b642-711d4db80a1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728253679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3728253679
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1240892846
Short name T527
Test name
Test status
Simulation time 388757008 ps
CPU time 1.4 seconds
Started Jun 25 05:40:32 PM PDT 24
Finished Jun 25 05:40:35 PM PDT 24
Peak memory 197628 kb
Host smart-d2397e62-202f-415e-a0ec-f75c93e4df78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240892846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1240892846
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2809228123
Short name T272
Test name
Test status
Simulation time 535861238 ps
CPU time 3.55 seconds
Started Jun 25 05:40:38 PM PDT 24
Finished Jun 25 05:40:43 PM PDT 24
Peak memory 198724 kb
Host smart-46f804c7-32fe-439d-81e2-d7fad9fee542
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809228123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2809228123
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.722378447
Short name T125
Test name
Test status
Simulation time 530280032 ps
CPU time 2.97 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:51 PM PDT 24
Peak memory 198732 kb
Host smart-9bc2e4e5-5784-4187-bf28-f0c98c6005e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722378447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
722378447
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.4283358245
Short name T62
Test name
Test status
Simulation time 19045321 ps
CPU time 0.84 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 196960 kb
Host smart-2c67be8e-d62e-4d3e-8af4-aff79b7bf2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283358245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.4283358245
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3171613629
Short name T671
Test name
Test status
Simulation time 31654801 ps
CPU time 1.07 seconds
Started Jun 25 05:40:36 PM PDT 24
Finished Jun 25 05:40:38 PM PDT 24
Peak memory 196560 kb
Host smart-aa20df63-ed46-48e9-9ac0-edf858ac5e34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171613629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3171613629
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1244143924
Short name T667
Test name
Test status
Simulation time 78495291 ps
CPU time 2.19 seconds
Started Jun 25 05:40:36 PM PDT 24
Finished Jun 25 05:40:39 PM PDT 24
Peak memory 198680 kb
Host smart-e08558ba-5e98-43f2-abdd-c9c2dc347222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244143924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1244143924
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3320584444
Short name T15
Test name
Test status
Simulation time 76901873 ps
CPU time 1.03 seconds
Started Jun 25 05:40:35 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 196252 kb
Host smart-967113ca-c745-4075-8755-9489cb8bf939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320584444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3320584444
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1107976049
Short name T140
Test name
Test status
Simulation time 152669281 ps
CPU time 1.15 seconds
Started Jun 25 05:40:34 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 196428 kb
Host smart-1fdeedef-2612-4231-b4a8-af12c0b2615c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107976049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1107976049
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2863668818
Short name T425
Test name
Test status
Simulation time 33678600172 ps
CPU time 177.15 seconds
Started Jun 25 05:40:50 PM PDT 24
Finished Jun 25 05:43:48 PM PDT 24
Peak memory 198868 kb
Host smart-42508fb9-53c1-4d4c-a4f8-40aab3b0f74a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863668818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2863668818
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.501272568
Short name T23
Test name
Test status
Simulation time 79925593886 ps
CPU time 708.41 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:52:36 PM PDT 24
Peak memory 198876 kb
Host smart-6e7fb1f9-6409-4beb-8dd7-b7ddb9b11ba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=501272568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.501272568
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1505882415
Short name T353
Test name
Test status
Simulation time 14805508 ps
CPU time 0.65 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:40:39 PM PDT 24
Peak memory 195360 kb
Host smart-96337848-df28-4374-b65d-99193befe643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505882415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1505882415
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1156392958
Short name T408
Test name
Test status
Simulation time 27894349 ps
CPU time 0.68 seconds
Started Jun 25 05:40:48 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 195316 kb
Host smart-8057ada5-e808-411c-bc12-2d5c88312f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156392958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1156392958
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3987843929
Short name T368
Test name
Test status
Simulation time 3116941693 ps
CPU time 28.24 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:41:07 PM PDT 24
Peak memory 198732 kb
Host smart-daee1c44-da1a-4591-89bb-be6ae50f3b08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987843929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3987843929
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2242941349
Short name T663
Test name
Test status
Simulation time 86875694 ps
CPU time 0.94 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196724 kb
Host smart-b9ef0af5-b5cd-418a-929d-1ae4253b9063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242941349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2242941349
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3261430094
Short name T134
Test name
Test status
Simulation time 208265500 ps
CPU time 1.36 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 196508 kb
Host smart-6e7d4674-4078-41b3-a213-8df66e5598c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261430094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3261430094
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2612180269
Short name T569
Test name
Test status
Simulation time 724007469 ps
CPU time 3.4 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 198632 kb
Host smart-5143a1e6-d430-4b91-84df-a633f10752b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612180269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2612180269
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2308559552
Short name T252
Test name
Test status
Simulation time 88824914 ps
CPU time 1.81 seconds
Started Jun 25 05:40:34 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 196744 kb
Host smart-8d86eaf5-9e88-4796-9439-bb6187baee9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308559552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2308559552
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2810714617
Short name T573
Test name
Test status
Simulation time 210135540 ps
CPU time 1.36 seconds
Started Jun 25 05:40:34 PM PDT 24
Finished Jun 25 05:40:36 PM PDT 24
Peak memory 198724 kb
Host smart-f6c1448c-1d8a-4bd6-979c-8fe1197ae412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810714617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2810714617
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.503817026
Short name T387
Test name
Test status
Simulation time 24801042 ps
CPU time 0.9 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 197388 kb
Host smart-e8335d9c-7580-480e-8b7e-5ade8e1f726b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503817026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.503817026
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1866395745
Short name T376
Test name
Test status
Simulation time 298189029 ps
CPU time 1.15 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 198620 kb
Host smart-104a44c6-9806-427a-a048-77314c7b1ede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866395745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1866395745
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1788427692
Short name T627
Test name
Test status
Simulation time 68305621 ps
CPU time 1.11 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:48 PM PDT 24
Peak memory 196292 kb
Host smart-cd180a7d-6376-4bc6-9cab-0893855a3abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788427692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1788427692
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1228200438
Short name T118
Test name
Test status
Simulation time 27633535 ps
CPU time 0.93 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:40:39 PM PDT 24
Peak memory 196948 kb
Host smart-9d7bd20f-058d-4223-8762-93189de23343
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228200438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1228200438
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3613582640
Short name T512
Test name
Test status
Simulation time 29807278331 ps
CPU time 193.81 seconds
Started Jun 25 05:40:36 PM PDT 24
Finished Jun 25 05:43:51 PM PDT 24
Peak memory 198760 kb
Host smart-783c3c8c-b7a4-4680-99f5-4c8056b28ddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613582640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3613582640
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.356801304
Short name T59
Test name
Test status
Simulation time 15620573868 ps
CPU time 276.57 seconds
Started Jun 25 05:40:36 PM PDT 24
Finished Jun 25 05:45:14 PM PDT 24
Peak memory 198876 kb
Host smart-f2d01b80-a732-470c-81cb-c8de83c53576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=356801304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.356801304
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2930850162
Short name T484
Test name
Test status
Simulation time 30523717 ps
CPU time 0.57 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 194644 kb
Host smart-88a242e9-b334-4d8a-8f08-0ef0cc815a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930850162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2930850162
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1111570155
Short name T314
Test name
Test status
Simulation time 40880246 ps
CPU time 0.93 seconds
Started Jun 25 05:40:36 PM PDT 24
Finished Jun 25 05:40:38 PM PDT 24
Peak memory 197160 kb
Host smart-1c637844-e1f4-4d37-b1fe-d5858f275d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111570155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1111570155
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.241901775
Short name T668
Test name
Test status
Simulation time 1315439216 ps
CPU time 9.96 seconds
Started Jun 25 05:40:34 PM PDT 24
Finished Jun 25 05:40:45 PM PDT 24
Peak memory 198660 kb
Host smart-f8346a12-fa7a-420c-bd66-193e471fc819
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241901775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.241901775
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1293722307
Short name T284
Test name
Test status
Simulation time 172571067 ps
CPU time 1.11 seconds
Started Jun 25 05:40:35 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 197160 kb
Host smart-ad1eeec0-0a87-407d-8305-b2b2ef710f8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293722307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1293722307
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3474274518
Short name T563
Test name
Test status
Simulation time 24803554 ps
CPU time 0.86 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 196272 kb
Host smart-152b0e85-f664-41f9-a341-40dd4e37be4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474274518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3474274518
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.491474294
Short name T388
Test name
Test status
Simulation time 184159963 ps
CPU time 1.29 seconds
Started Jun 25 05:40:50 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 197528 kb
Host smart-e902c3ff-0afd-42f3-bb66-e0a6e4dfd0bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491474294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.491474294
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3772243607
Short name T477
Test name
Test status
Simulation time 199342392 ps
CPU time 1.66 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 196536 kb
Host smart-9e80f64b-0e3f-44e3-8d0c-70712dbeac66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772243607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3772243607
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2193370455
Short name T687
Test name
Test status
Simulation time 54956633 ps
CPU time 1.11 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:48 PM PDT 24
Peak memory 197280 kb
Host smart-55b15a88-e471-49f4-992d-f9889dc79225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193370455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2193370455
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.816897740
Short name T689
Test name
Test status
Simulation time 106608666 ps
CPU time 0.68 seconds
Started Jun 25 05:40:38 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 195028 kb
Host smart-311c00bb-6b90-496d-8df0-521400798670
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816897740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.816897740
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2006993186
Short name T172
Test name
Test status
Simulation time 101029575 ps
CPU time 4.62 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:40:54 PM PDT 24
Peak memory 198636 kb
Host smart-fb50a125-ad2d-401a-b0f0-549b6c62f237
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006993186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2006993186
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3446853749
Short name T586
Test name
Test status
Simulation time 105015461 ps
CPU time 0.93 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 196260 kb
Host smart-5fff5a3e-ab03-4d16-b502-309dbb3a0189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446853749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3446853749
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3756581567
Short name T507
Test name
Test status
Simulation time 39482236 ps
CPU time 0.77 seconds
Started Jun 25 05:40:35 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 194896 kb
Host smart-d7ee5f1f-2feb-4eca-9d13-7e3d8360c471
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756581567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3756581567
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2746525302
Short name T502
Test name
Test status
Simulation time 5244343563 ps
CPU time 128.17 seconds
Started Jun 25 05:40:50 PM PDT 24
Finished Jun 25 05:43:00 PM PDT 24
Peak memory 198820 kb
Host smart-2b90e4a5-dbe6-4b41-9ffd-1450fa36792c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746525302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2746525302
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2608033404
Short name T299
Test name
Test status
Simulation time 39124701 ps
CPU time 0.58 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 194672 kb
Host smart-520465f1-b118-4fa7-a018-3e52e2e1c6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608033404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2608033404
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4024107106
Short name T712
Test name
Test status
Simulation time 15066830 ps
CPU time 0.65 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 194576 kb
Host smart-4b1cd065-ab94-49d4-958c-9428b3baba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024107106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4024107106
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.216873138
Short name T202
Test name
Test status
Simulation time 664157638 ps
CPU time 9.45 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:40:48 PM PDT 24
Peak memory 197552 kb
Host smart-20bcb503-6b64-4686-b3eb-87587a8a6121
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216873138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.216873138
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.671398999
Short name T156
Test name
Test status
Simulation time 75441436 ps
CPU time 0.64 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 195196 kb
Host smart-fee53ce8-cb97-418b-b904-6e7851157455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671398999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.671398999
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3518983433
Short name T640
Test name
Test status
Simulation time 114255972 ps
CPU time 1.09 seconds
Started Jun 25 05:40:50 PM PDT 24
Finished Jun 25 05:40:52 PM PDT 24
Peak memory 197520 kb
Host smart-cd65c464-930b-46f6-9993-7492ca44858b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518983433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3518983433
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2161011283
Short name T683
Test name
Test status
Simulation time 51802068 ps
CPU time 2.04 seconds
Started Jun 25 05:40:35 PM PDT 24
Finished Jun 25 05:40:38 PM PDT 24
Peak memory 197244 kb
Host smart-84050aa5-b11d-44cf-9bcc-94d46273bb28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161011283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2161011283
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1264091214
Short name T237
Test name
Test status
Simulation time 149155558 ps
CPU time 2.95 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197684 kb
Host smart-4f40a9c5-8b7f-477c-b724-0a5fc70927d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264091214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1264091214
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3908019694
Short name T296
Test name
Test status
Simulation time 52978460 ps
CPU time 1.11 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:46 PM PDT 24
Peak memory 196540 kb
Host smart-c0ba24f2-13fb-4e6c-ae84-e044f9291ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908019694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3908019694
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2848657702
Short name T291
Test name
Test status
Simulation time 30298845 ps
CPU time 0.8 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 196044 kb
Host smart-610e87e7-ad6e-42f3-87d7-338c409abd9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848657702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2848657702
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1502944603
Short name T340
Test name
Test status
Simulation time 913202389 ps
CPU time 3.46 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 198764 kb
Host smart-88d87ec0-5e86-4b3d-85e5-e7b099a447d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502944603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1502944603
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3394498449
Short name T268
Test name
Test status
Simulation time 143324964 ps
CPU time 0.94 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196200 kb
Host smart-59b7b7c4-f6a3-437b-aee9-6fa18c943870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394498449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3394498449
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3003594665
Short name T182
Test name
Test status
Simulation time 85389201 ps
CPU time 1.45 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 196976 kb
Host smart-43c7499c-03b3-4fbf-b72b-6bb1a5e6065a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003594665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3003594665
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2002791593
Short name T211
Test name
Test status
Simulation time 1772666243 ps
CPU time 47.38 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:41:31 PM PDT 24
Peak memory 198672 kb
Host smart-4b30ff47-4157-496b-b78f-4282fd3300d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002791593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2002791593
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3077269390
Short name T577
Test name
Test status
Simulation time 20072753 ps
CPU time 0.59 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 195364 kb
Host smart-bfcf7884-f256-4407-af84-b9703036e524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077269390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3077269390
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1768032285
Short name T378
Test name
Test status
Simulation time 29263222 ps
CPU time 0.67 seconds
Started Jun 25 05:40:38 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 195440 kb
Host smart-7fdd77f8-b9be-4be7-b825-b4180129010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768032285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1768032285
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2393148553
Short name T529
Test name
Test status
Simulation time 833371137 ps
CPU time 7.75 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:40:51 PM PDT 24
Peak memory 197732 kb
Host smart-436a22db-b546-476b-808a-1eb0b57ef0b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393148553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2393148553
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3511261683
Short name T49
Test name
Test status
Simulation time 130192445 ps
CPU time 0.75 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 196144 kb
Host smart-076934e9-9b3f-4137-9bf7-8e14b11e1987
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511261683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3511261683
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2592116290
Short name T119
Test name
Test status
Simulation time 227620789 ps
CPU time 0.95 seconds
Started Jun 25 05:40:35 PM PDT 24
Finished Jun 25 05:40:38 PM PDT 24
Peak memory 197520 kb
Host smart-ecfd8973-3cc2-4864-8983-36fa7d4bc490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592116290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2592116290
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3651848
Short name T363
Test name
Test status
Simulation time 60977553 ps
CPU time 1.38 seconds
Started Jun 25 05:40:36 PM PDT 24
Finished Jun 25 05:40:38 PM PDT 24
Peak memory 198752 kb
Host smart-2630523d-cb7d-476c-ab72-5c5eabbaa2be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_intr_with_filter_rand_intr_event.3651848
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1651824399
Short name T141
Test name
Test status
Simulation time 524909849 ps
CPU time 1.07 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:54 PM PDT 24
Peak memory 195996 kb
Host smart-56f94b25-6b6f-48d4-ad13-969f3f1f26c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651824399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1651824399
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3399422600
Short name T584
Test name
Test status
Simulation time 20596444 ps
CPU time 0.83 seconds
Started Jun 25 05:40:35 PM PDT 24
Finished Jun 25 05:40:38 PM PDT 24
Peak memory 197248 kb
Host smart-f5650d85-63f4-4147-a901-11d63a5d7117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399422600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3399422600
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.770991883
Short name T469
Test name
Test status
Simulation time 44045715 ps
CPU time 1.07 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 196504 kb
Host smart-08b9a05f-bda1-4050-bcd9-444be76cb745
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770991883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.770991883
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1713740870
Short name T628
Test name
Test status
Simulation time 1503152295 ps
CPU time 2.06 seconds
Started Jun 25 05:40:50 PM PDT 24
Finished Jun 25 05:40:54 PM PDT 24
Peak memory 198648 kb
Host smart-06e201d9-2091-4b49-a10d-c31fa483162b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713740870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1713740870
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2209639577
Short name T214
Test name
Test status
Simulation time 534483127 ps
CPU time 1.31 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196116 kb
Host smart-3e7b5008-737a-4c00-8b6b-71f79bb3aa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209639577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2209639577
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.386864786
Short name T508
Test name
Test status
Simulation time 108428174 ps
CPU time 1.52 seconds
Started Jun 25 05:40:39 PM PDT 24
Finished Jun 25 05:40:42 PM PDT 24
Peak memory 197348 kb
Host smart-315ff6d7-45a8-4754-ac46-63c63be5ca8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386864786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.386864786
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.816633375
Short name T490
Test name
Test status
Simulation time 30247841398 ps
CPU time 196.88 seconds
Started Jun 25 05:40:41 PM PDT 24
Finished Jun 25 05:43:59 PM PDT 24
Peak memory 198924 kb
Host smart-6eca7462-38d0-4ea9-a312-6e65256250be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816633375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.816633375
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.751822801
Short name T579
Test name
Test status
Simulation time 97513236619 ps
CPU time 2052.08 seconds
Started Jun 25 05:40:37 PM PDT 24
Finished Jun 25 06:14:51 PM PDT 24
Peak memory 198956 kb
Host smart-2625bc6c-3b54-4378-8097-e81fe894eb73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=751822801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.751822801
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3693216355
Short name T235
Test name
Test status
Simulation time 17682264 ps
CPU time 0.58 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 194652 kb
Host smart-a1c465b8-2002-40f2-8c43-2b7160f6fad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693216355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3693216355
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2876785864
Short name T112
Test name
Test status
Simulation time 50149436 ps
CPU time 1 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:45 PM PDT 24
Peak memory 197304 kb
Host smart-65abb86d-fbea-4d35-a958-4d026a24806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876785864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2876785864
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1078784913
Short name T536
Test name
Test status
Simulation time 2469663280 ps
CPU time 19.95 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:41:14 PM PDT 24
Peak memory 197648 kb
Host smart-3902c84a-cf06-4406-a49a-874cb9953f91
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078784913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1078784913
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2292433716
Short name T716
Test name
Test status
Simulation time 94456870 ps
CPU time 0.85 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197484 kb
Host smart-d7512ecc-ba56-40fc-8a58-0c5ade216619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292433716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2292433716
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.618525302
Short name T647
Test name
Test status
Simulation time 33576570 ps
CPU time 0.89 seconds
Started Jun 25 05:40:50 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196044 kb
Host smart-712296d1-f1ba-41b8-9445-d8df049d3aec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618525302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.618525302
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3462842725
Short name T245
Test name
Test status
Simulation time 61568231 ps
CPU time 1.34 seconds
Started Jun 25 05:41:02 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 197360 kb
Host smart-870d5b24-8c05-4925-99ff-8721ae1eb4cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462842725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3462842725
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1732654202
Short name T203
Test name
Test status
Simulation time 195356422 ps
CPU time 1.38 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197360 kb
Host smart-0e13bd33-64d7-42fd-9f36-83aeb9a8e316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732654202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1732654202
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1166214286
Short name T649
Test name
Test status
Simulation time 30181652 ps
CPU time 1.2 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197488 kb
Host smart-df136f74-f2fa-4fdd-be38-99b3e4e066cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166214286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1166214286
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1663732091
Short name T287
Test name
Test status
Simulation time 180208896 ps
CPU time 1.02 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:48 PM PDT 24
Peak memory 196736 kb
Host smart-b608b45f-f417-4353-8a4e-736dd5d0bdb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663732091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1663732091
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2934601901
Short name T120
Test name
Test status
Simulation time 424358388 ps
CPU time 5.06 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 198712 kb
Host smart-67b65619-8116-4f65-a8a8-d81a454dd841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934601901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2934601901
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2336463034
Short name T215
Test name
Test status
Simulation time 71568819 ps
CPU time 1.16 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:40:44 PM PDT 24
Peak memory 196368 kb
Host smart-d05f8167-a6e7-4bd7-bda2-7880a687e9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336463034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2336463034
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3892170047
Short name T372
Test name
Test status
Simulation time 198268321 ps
CPU time 0.87 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:45 PM PDT 24
Peak memory 196908 kb
Host smart-16876790-8b55-4d84-a499-0a35fd1dda8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892170047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3892170047
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3653518355
Short name T256
Test name
Test status
Simulation time 793125329 ps
CPU time 18.59 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:41:01 PM PDT 24
Peak memory 198528 kb
Host smart-bbb0dffb-6cea-41a7-863d-d12675af3eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653518355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3653518355
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3266743514
Short name T646
Test name
Test status
Simulation time 41833746 ps
CPU time 0.57 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 194684 kb
Host smart-98bb627b-790c-4cf9-b214-aaf9c8391580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266743514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3266743514
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3912947437
Short name T639
Test name
Test status
Simulation time 135412488 ps
CPU time 0.77 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:46 PM PDT 24
Peak memory 196644 kb
Host smart-694dfde9-b172-4ea2-9be5-18aad347d8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912947437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3912947437
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1540213796
Short name T557
Test name
Test status
Simulation time 587759942 ps
CPU time 19.37 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 196244 kb
Host smart-041826fd-6c1c-44e0-9bac-55fc3c9024ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540213796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1540213796
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2479131103
Short name T397
Test name
Test status
Simulation time 261424956 ps
CPU time 0.7 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 195288 kb
Host smart-20257e18-6e52-497b-b1e4-1a2972c94af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479131103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2479131103
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.619524975
Short name T51
Test name
Test status
Simulation time 230438959 ps
CPU time 1.05 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 197288 kb
Host smart-3c4106ef-f2d3-41a5-88b7-febcf34e4001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619524975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.619524975
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1919995379
Short name T635
Test name
Test status
Simulation time 290019026 ps
CPU time 2.89 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:57 PM PDT 24
Peak memory 198736 kb
Host smart-73def44a-269a-43b2-9d2e-21ab6f0e11fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919995379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1919995379
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3801363067
Short name T506
Test name
Test status
Simulation time 136887143 ps
CPU time 2.86 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 197836 kb
Host smart-9836e539-1446-4d01-89a1-5cb2fdc4548b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801363067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3801363067
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2428417798
Short name T393
Test name
Test status
Simulation time 64311089 ps
CPU time 1.24 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 198756 kb
Host smart-751a8a15-ae59-40ae-b8db-34536d54e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428417798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2428417798
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.4106244011
Short name T542
Test name
Test status
Simulation time 1262874358 ps
CPU time 1.3 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:46 PM PDT 24
Peak memory 198760 kb
Host smart-40318770-b89f-4b81-a6be-491768e81eb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106244011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.4106244011
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1470925855
Short name T701
Test name
Test status
Simulation time 183106430 ps
CPU time 4.43 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 198696 kb
Host smart-cb70a96c-68ab-4975-8c57-a03710977d22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470925855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1470925855
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3586891914
Short name T648
Test name
Test status
Simulation time 68867384 ps
CPU time 1.36 seconds
Started Jun 25 05:40:49 PM PDT 24
Finished Jun 25 05:40:51 PM PDT 24
Peak memory 198748 kb
Host smart-e75bccce-ec06-478e-af5d-9397b4d491f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586891914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3586891914
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2423420523
Short name T269
Test name
Test status
Simulation time 47770427 ps
CPU time 1.22 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:57 PM PDT 24
Peak memory 197264 kb
Host smart-26e5c8dd-755a-4cca-a714-3a272f51e60e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423420523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2423420523
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1515242711
Short name T345
Test name
Test status
Simulation time 5420164985 ps
CPU time 29.57 seconds
Started Jun 25 05:40:48 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 198816 kb
Host smart-28926419-f1ef-4f05-8e77-bad20579ed26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515242711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1515242711
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1806413292
Short name T631
Test name
Test status
Simulation time 35986317 ps
CPU time 0.61 seconds
Started Jun 25 05:40:08 PM PDT 24
Finished Jun 25 05:40:10 PM PDT 24
Peak memory 194676 kb
Host smart-058462b2-344a-4a1a-9ba7-e71193e24435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806413292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1806413292
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2154479716
Short name T142
Test name
Test status
Simulation time 202312169 ps
CPU time 0.97 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:13 PM PDT 24
Peak memory 196416 kb
Host smart-bc0ead8c-4c6d-427b-9bc6-e0d306115bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154479716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2154479716
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3603476031
Short name T154
Test name
Test status
Simulation time 505447585 ps
CPU time 3.41 seconds
Started Jun 25 05:40:13 PM PDT 24
Finished Jun 25 05:40:17 PM PDT 24
Peak memory 197124 kb
Host smart-77644d9e-ded1-4ab1-91e9-7f12aa2967ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603476031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3603476031
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2765370288
Short name T611
Test name
Test status
Simulation time 122488645 ps
CPU time 0.75 seconds
Started Jun 25 05:40:09 PM PDT 24
Finished Jun 25 05:40:11 PM PDT 24
Peak memory 195492 kb
Host smart-01bb10ed-7794-4637-851a-764d246e7647
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765370288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2765370288
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2561760179
Short name T632
Test name
Test status
Simulation time 66889817 ps
CPU time 1.36 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 196472 kb
Host smart-bfa7833a-082d-4f3c-917e-47749ad87559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561760179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2561760179
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2206060975
Short name T390
Test name
Test status
Simulation time 35209953 ps
CPU time 1.47 seconds
Started Jun 25 05:40:22 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 198504 kb
Host smart-4485849c-fc76-4674-81e3-ec9bd6ec3678
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206060975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2206060975
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.4081171293
Short name T650
Test name
Test status
Simulation time 128947041 ps
CPU time 2.89 seconds
Started Jun 25 05:40:20 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 197860 kb
Host smart-93212224-dbbc-4140-9cb7-627b23b121d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081171293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
4081171293
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.798120344
Short name T523
Test name
Test status
Simulation time 20509327 ps
CPU time 0.77 seconds
Started Jun 25 05:40:12 PM PDT 24
Finished Jun 25 05:40:14 PM PDT 24
Peak memory 196160 kb
Host smart-1f7cdc75-20a0-4167-935d-975726700d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798120344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.798120344
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.857462463
Short name T292
Test name
Test status
Simulation time 81865526 ps
CPU time 1.15 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:13 PM PDT 24
Peak memory 197240 kb
Host smart-da7b74d0-c19f-4c39-a027-6e8ba7406f61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857462463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.857462463
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.454100175
Short name T623
Test name
Test status
Simulation time 1193794556 ps
CPU time 4.42 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:40:21 PM PDT 24
Peak memory 198668 kb
Host smart-53639089-686f-4d37-a543-5e39612c754c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454100175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.454100175
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.733733037
Short name T28
Test name
Test status
Simulation time 282662871 ps
CPU time 1.12 seconds
Started Jun 25 05:40:20 PM PDT 24
Finished Jun 25 05:40:23 PM PDT 24
Peak memory 214336 kb
Host smart-37279a06-2724-442b-b9f9-83192151eadc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733733037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.733733037
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.3049412575
Short name T193
Test name
Test status
Simulation time 61745128 ps
CPU time 0.9 seconds
Started Jun 25 05:40:05 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 196372 kb
Host smart-4839c36b-608b-4182-9d2d-82eda3b0c5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049412575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.3049412575
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3215112146
Short name T177
Test name
Test status
Simulation time 62384960 ps
CPU time 1.2 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:40:17 PM PDT 24
Peak memory 197560 kb
Host smart-ed33375c-f29d-4ef5-b62a-3cf0c76e7e94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215112146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3215112146
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.413030025
Short name T578
Test name
Test status
Simulation time 17083303362 ps
CPU time 238.61 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:44:10 PM PDT 24
Peak memory 198940 kb
Host smart-f20a950a-e643-4975-b7c0-a6f7ae185351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=413030025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.413030025
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2819563315
Short name T234
Test name
Test status
Simulation time 15957193 ps
CPU time 0.63 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 194896 kb
Host smart-b735f90f-360f-4ed5-b560-2d0ed8a628ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819563315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2819563315
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.98021724
Short name T418
Test name
Test status
Simulation time 43144645 ps
CPU time 0.71 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:40:44 PM PDT 24
Peak memory 195040 kb
Host smart-67322537-eb88-4801-91d5-42d16a807546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98021724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.98021724
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4271277135
Short name T642
Test name
Test status
Simulation time 791079251 ps
CPU time 20.08 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 197672 kb
Host smart-d4d78cdb-3e1c-4ae7-bdb7-305656f34da0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271277135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4271277135
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2008816649
Short name T308
Test name
Test status
Simulation time 246735293 ps
CPU time 0.8 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196548 kb
Host smart-f9e49440-adda-4874-b58f-8bdf216b1305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008816649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2008816649
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4221560826
Short name T466
Test name
Test status
Simulation time 233768654 ps
CPU time 0.9 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197164 kb
Host smart-51863598-f3ef-4f7f-afcf-0c90c45c4321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221560826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4221560826
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2395929092
Short name T493
Test name
Test status
Simulation time 144675682 ps
CPU time 2.89 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 198700 kb
Host smart-f31b1660-fae9-435a-9458-cd9b8ebce604
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395929092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2395929092
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2545528253
Short name T133
Test name
Test status
Simulation time 152185263 ps
CPU time 2.39 seconds
Started Jun 25 05:40:54 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 196544 kb
Host smart-1e4e9416-ff9f-4f07-9668-489aa6d5a1cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545528253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2545528253
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1921270989
Short name T19
Test name
Test status
Simulation time 251730871 ps
CPU time 1.35 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 198692 kb
Host smart-fa95b9ed-0b58-4334-b53f-87bfeae8f761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921270989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1921270989
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3622668708
Short name T173
Test name
Test status
Simulation time 428042241 ps
CPU time 0.89 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196064 kb
Host smart-97ed5bcf-4be5-4911-be79-bf4c783660ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622668708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3622668708
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2660385453
Short name T666
Test name
Test status
Simulation time 371036239 ps
CPU time 6.45 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:54 PM PDT 24
Peak memory 198636 kb
Host smart-38bf8a09-3b39-4219-bdb7-47b355878a49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660385453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2660385453
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2935814104
Short name T17
Test name
Test status
Simulation time 100392722 ps
CPU time 1.51 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197452 kb
Host smart-6022f7b5-eaa0-4eac-a2e7-dc205e1b915a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935814104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2935814104
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1991221298
Short name T674
Test name
Test status
Simulation time 206508846 ps
CPU time 1.14 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 196472 kb
Host smart-3923cd09-f276-4e07-b939-d3379c70baf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991221298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1991221298
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1400470700
Short name T8
Test name
Test status
Simulation time 9895420552 ps
CPU time 108.29 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:42:42 PM PDT 24
Peak memory 198780 kb
Host smart-67fc505f-8c37-4d93-9861-bb6115ffc331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400470700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1400470700
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.155071985
Short name T224
Test name
Test status
Simulation time 51173597 ps
CPU time 0.64 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 195588 kb
Host smart-51188eb1-fec6-4d48-ab75-78db2e612858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155071985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.155071985
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2719292313
Short name T128
Test name
Test status
Simulation time 130035034 ps
CPU time 0.83 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 196072 kb
Host smart-4ca06964-b1e5-4f7a-a8f4-cf66229a4d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719292313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2719292313
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1756557995
Short name T165
Test name
Test status
Simulation time 707973765 ps
CPU time 7.77 seconds
Started Jun 25 05:40:49 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 197520 kb
Host smart-dffcdfb7-eaec-493e-9344-5e5947f37982
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756557995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1756557995
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3338841480
Short name T629
Test name
Test status
Simulation time 47967802 ps
CPU time 0.87 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 197164 kb
Host smart-6bc45dff-ada2-47ea-ae76-1787801e4986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338841480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3338841480
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1169483786
Short name T116
Test name
Test status
Simulation time 362339834 ps
CPU time 0.9 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 196992 kb
Host smart-17e70195-271c-48da-ae41-de4987bd83d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169483786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1169483786
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1989558452
Short name T96
Test name
Test status
Simulation time 85873406 ps
CPU time 3.58 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 198712 kb
Host smart-b89bd328-fc61-4bef-9d16-5dd1b9645a6e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989558452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1989558452
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2731455717
Short name T394
Test name
Test status
Simulation time 112683004 ps
CPU time 2.43 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197736 kb
Host smart-df27484c-376c-482b-8914-2d931624d6a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731455717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2731455717
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1541141789
Short name T500
Test name
Test status
Simulation time 27634028 ps
CPU time 1.09 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 05:40:47 PM PDT 24
Peak memory 197408 kb
Host smart-d4193955-2fe0-4be8-9032-ce491243ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541141789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1541141789
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3603130813
Short name T259
Test name
Test status
Simulation time 33096567 ps
CPU time 1.17 seconds
Started Jun 25 05:40:42 PM PDT 24
Finished Jun 25 05:40:44 PM PDT 24
Peak memory 197312 kb
Host smart-4132f02d-0a29-4ebf-a1e2-f6d2b22b1ce2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603130813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3603130813
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.287428995
Short name T505
Test name
Test status
Simulation time 75729557 ps
CPU time 1.16 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:45 PM PDT 24
Peak memory 196892 kb
Host smart-164c3feb-020c-4a9d-a035-b8499e93063a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287428995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.287428995
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2458771434
Short name T107
Test name
Test status
Simulation time 179516766 ps
CPU time 1.27 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:57 PM PDT 24
Peak memory 197476 kb
Host smart-c9f3dfd8-40ee-4d11-93c1-caccb875a8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458771434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2458771434
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2266287277
Short name T258
Test name
Test status
Simulation time 42703037 ps
CPU time 1.08 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:46 PM PDT 24
Peak memory 197156 kb
Host smart-0e2488f5-8eb9-4427-bc1a-b358cdda41c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266287277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2266287277
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4230664576
Short name T349
Test name
Test status
Simulation time 114754948373 ps
CPU time 191.61 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:43:57 PM PDT 24
Peak memory 198812 kb
Host smart-3a6e1583-5831-4f0a-81ec-e81784f9e774
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230664576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4230664576
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.169369915
Short name T497
Test name
Test status
Simulation time 100466946566 ps
CPU time 407.55 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:47:40 PM PDT 24
Peak memory 198916 kb
Host smart-e8b4ada9-3105-484e-9b2c-742a2dac0dc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=169369915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.169369915
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1705525583
Short name T431
Test name
Test status
Simulation time 53315460 ps
CPU time 0.6 seconds
Started Jun 25 05:40:43 PM PDT 24
Finished Jun 25 05:40:46 PM PDT 24
Peak memory 194876 kb
Host smart-d3211cc3-961a-40fc-8b3c-05c7e3a6badd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705525583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1705525583
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3709911680
Short name T543
Test name
Test status
Simulation time 92497662 ps
CPU time 0.86 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 196780 kb
Host smart-eb8bd8fa-20e9-4e22-82fe-83d51c41adb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709911680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3709911680
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3066386192
Short name T405
Test name
Test status
Simulation time 2488212905 ps
CPU time 22.06 seconds
Started Jun 25 05:40:54 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 197500 kb
Host smart-d0eae602-84bc-459b-b6a0-bf910b37d438
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066386192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3066386192
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3108625577
Short name T257
Test name
Test status
Simulation time 257781637 ps
CPU time 0.97 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:54 PM PDT 24
Peak memory 197848 kb
Host smart-6b33b21e-2a76-4053-b0ee-faae754bc5b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108625577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3108625577
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.151248924
Short name T352
Test name
Test status
Simulation time 180598997 ps
CPU time 1.51 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 198752 kb
Host smart-2e8d92b1-6bbc-4d3c-857f-c2eb225810d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151248924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.151248924
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3799443775
Short name T236
Test name
Test status
Simulation time 99946287 ps
CPU time 2.19 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 197140 kb
Host smart-bd39934d-cdc7-4b97-935d-fc0f7262c42a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799443775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3799443775
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4087249123
Short name T132
Test name
Test status
Simulation time 117892805 ps
CPU time 2.29 seconds
Started Jun 25 05:40:54 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 196528 kb
Host smart-7e42841c-2ac2-466c-830f-9a6429a50edd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087249123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4087249123
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2644726480
Short name T576
Test name
Test status
Simulation time 67434568 ps
CPU time 1.04 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 196632 kb
Host smart-19709211-8e6c-4b46-8ffc-e89a72a63c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644726480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2644726480
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.443999463
Short name T707
Test name
Test status
Simulation time 104679290 ps
CPU time 1.05 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 196496 kb
Host smart-91adea9e-3a7a-4ef9-aa94-14dc63afbb0d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443999463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.443999463
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4111682438
Short name T430
Test name
Test status
Simulation time 568095680 ps
CPU time 4.83 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:40:54 PM PDT 24
Peak memory 198672 kb
Host smart-ef83003e-b8e3-401d-8ae7-08b6dc2f05e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111682438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4111682438
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1342259823
Short name T124
Test name
Test status
Simulation time 45898646 ps
CPU time 1.25 seconds
Started Jun 25 05:40:54 PM PDT 24
Finished Jun 25 05:41:02 PM PDT 24
Peak memory 197084 kb
Host smart-01911647-8bc5-4a1e-91a8-c0a43f03854f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342259823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1342259823
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4245940242
Short name T188
Test name
Test status
Simulation time 83092207 ps
CPU time 1.35 seconds
Started Jun 25 05:40:54 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 196964 kb
Host smart-7f2b459b-0e1a-4c66-94b5-c47508305eb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245940242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4245940242
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4176889053
Short name T122
Test name
Test status
Simulation time 5584513815 ps
CPU time 37.32 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:41:25 PM PDT 24
Peak memory 198808 kb
Host smart-b0be8151-3731-4fb5-bede-29e215117f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176889053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4176889053
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.905347153
Short name T658
Test name
Test status
Simulation time 120209177362 ps
CPU time 2062.48 seconds
Started Jun 25 05:40:44 PM PDT 24
Finished Jun 25 06:15:08 PM PDT 24
Peak memory 198936 kb
Host smart-2fa05ca8-703a-4875-b624-1b35d9c51b73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=905347153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.905347153
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1514550116
Short name T279
Test name
Test status
Simulation time 15836485 ps
CPU time 0.6 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 195496 kb
Host smart-9004d0d3-468f-43c2-8adb-a09a08e56d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514550116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1514550116
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1793435002
Short name T225
Test name
Test status
Simulation time 60608539 ps
CPU time 0.85 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196796 kb
Host smart-0c68f41d-7ded-4914-88c6-8bf9b50b79d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793435002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1793435002
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2905161734
Short name T706
Test name
Test status
Simulation time 3980164406 ps
CPU time 27.79 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:41:23 PM PDT 24
Peak memory 197208 kb
Host smart-7ab770e6-2954-454d-951b-08cbe124cad3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905161734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2905161734
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1857362650
Short name T450
Test name
Test status
Simulation time 94376299 ps
CPU time 0.99 seconds
Started Jun 25 05:41:03 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 197748 kb
Host smart-0bc317e1-1b47-4fee-bf21-0b54f095409b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857362650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1857362650
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3323597598
Short name T593
Test name
Test status
Simulation time 56039580 ps
CPU time 1 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 196832 kb
Host smart-b3b98a36-36ae-4e7f-bf5d-bdceba7ece9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323597598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3323597598
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2944932483
Short name T159
Test name
Test status
Simulation time 41974300 ps
CPU time 0.98 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 197596 kb
Host smart-0340bbe0-0615-4927-bae6-2f36f2015133
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944932483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2944932483
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2621845428
Short name T630
Test name
Test status
Simulation time 132247682 ps
CPU time 2.81 seconds
Started Jun 25 05:40:45 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 197212 kb
Host smart-bf8562e4-b72a-44b5-8503-70954ecb5cad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621845428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2621845428
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2015531893
Short name T247
Test name
Test status
Simulation time 161651537 ps
CPU time 1.08 seconds
Started Jun 25 05:40:46 PM PDT 24
Finished Jun 25 05:40:49 PM PDT 24
Peak memory 196596 kb
Host smart-c397aa23-3412-463a-a08f-9b2c4e79187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015531893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2015531893
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3391911203
Short name T681
Test name
Test status
Simulation time 90601809 ps
CPU time 0.86 seconds
Started Jun 25 05:40:58 PM PDT 24
Finished Jun 25 05:41:00 PM PDT 24
Peak memory 196924 kb
Host smart-0cdc317c-e33b-457a-af13-c756223bb09e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391911203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3391911203
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1996736519
Short name T511
Test name
Test status
Simulation time 374175859 ps
CPU time 3.24 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:41:11 PM PDT 24
Peak memory 198656 kb
Host smart-cb7d97cf-7cff-4fcb-93cb-a0206afa9aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996736519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1996736519
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.791856251
Short name T426
Test name
Test status
Simulation time 95439575 ps
CPU time 1.03 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 196512 kb
Host smart-4d2c2154-fd44-456a-9d1f-edec94679284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791856251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.791856251
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1403352741
Short name T567
Test name
Test status
Simulation time 164851289 ps
CPU time 1.35 seconds
Started Jun 25 05:40:47 PM PDT 24
Finished Jun 25 05:40:50 PM PDT 24
Peak memory 196260 kb
Host smart-2b598097-8f47-417c-bc8f-08f70709a3c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403352741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1403352741
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3779800328
Short name T702
Test name
Test status
Simulation time 23212415027 ps
CPU time 135.82 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:43:14 PM PDT 24
Peak memory 198820 kb
Host smart-833ca282-a6f5-4509-a337-e4a941860e1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779800328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3779800328
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2851885912
Short name T700
Test name
Test status
Simulation time 24315924 ps
CPU time 0.55 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 194664 kb
Host smart-e4c6b658-721b-40ea-9135-b0b099e4aa2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851885912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2851885912
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.85707941
Short name T483
Test name
Test status
Simulation time 48804868 ps
CPU time 0.94 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:40:58 PM PDT 24
Peak memory 197408 kb
Host smart-1b9d7ec5-54c2-4bff-8505-af4ad2632bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85707941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.85707941
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3939390830
Short name T452
Test name
Test status
Simulation time 772053659 ps
CPU time 20.17 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 198736 kb
Host smart-bf3e0f71-4255-4e7d-aab8-25d7ce218074
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939390830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3939390830
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3947164355
Short name T423
Test name
Test status
Simulation time 206222379 ps
CPU time 0.89 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:11 PM PDT 24
Peak memory 197352 kb
Host smart-7d46d03f-2d36-4035-a746-35809b4aad84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947164355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3947164355
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.4093055732
Short name T422
Test name
Test status
Simulation time 328224837 ps
CPU time 1.09 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 197216 kb
Host smart-e954c029-f08d-40ea-9ebe-51140fe65855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093055732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.4093055732
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3745383327
Short name T311
Test name
Test status
Simulation time 31782544 ps
CPU time 1.31 seconds
Started Jun 25 05:41:02 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 197584 kb
Host smart-efb4d8d1-58bd-44a3-9073-83484590afbf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745383327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3745383327
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2868274228
Short name T377
Test name
Test status
Simulation time 214221988 ps
CPU time 1.99 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 197604 kb
Host smart-b15473bb-adea-4e58-b7e2-f4f8f5fa2d3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868274228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2868274228
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1081863286
Short name T580
Test name
Test status
Simulation time 73865487 ps
CPU time 0.81 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 196812 kb
Host smart-c33f0dca-20c3-4824-a30c-1a0cd9b536f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081863286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1081863286
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3655964504
Short name T444
Test name
Test status
Simulation time 39127363 ps
CPU time 0.69 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 05:41:13 PM PDT 24
Peak memory 195028 kb
Host smart-bcc0ab67-7805-4741-aa3f-1065ccac284a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655964504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3655964504
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.892730275
Short name T301
Test name
Test status
Simulation time 2138829518 ps
CPU time 6.55 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 198644 kb
Host smart-852e879f-9351-4c06-928f-72fae8d800d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892730275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.892730275
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2195610072
Short name T499
Test name
Test status
Simulation time 87614558 ps
CPU time 0.86 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:55 PM PDT 24
Peak memory 195876 kb
Host smart-ab9da78b-e93f-4882-9ec9-04be4440c1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195610072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2195610072
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3672460161
Short name T262
Test name
Test status
Simulation time 30467205 ps
CPU time 1.02 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:02 PM PDT 24
Peak memory 196392 kb
Host smart-de9abbaa-1370-465d-a837-b66c39d1838e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672460161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3672460161
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.293449511
Short name T664
Test name
Test status
Simulation time 7666229944 ps
CPU time 107.45 seconds
Started Jun 25 05:40:54 PM PDT 24
Finished Jun 25 05:42:44 PM PDT 24
Peak memory 198804 kb
Host smart-20f401ce-fd95-46b6-871c-9f89fdfcc50e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293449511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.293449511
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1755917044
Short name T56
Test name
Test status
Simulation time 250906939226 ps
CPU time 597.37 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:50:54 PM PDT 24
Peak memory 198944 kb
Host smart-9b45e8a6-1434-4a9f-b40f-4854ccc0f523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1755917044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1755917044
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3141340502
Short name T210
Test name
Test status
Simulation time 11442675 ps
CPU time 0.62 seconds
Started Jun 25 05:41:04 PM PDT 24
Finished Jun 25 05:41:07 PM PDT 24
Peak memory 194888 kb
Host smart-9b2385e8-1d94-42b3-b335-645e1c78a919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141340502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3141340502
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3194326383
Short name T161
Test name
Test status
Simulation time 25804519 ps
CPU time 0.97 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 197736 kb
Host smart-b2db1bcb-54d2-4522-b2c0-8fc2a5ce983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194326383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3194326383
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2490039543
Short name T433
Test name
Test status
Simulation time 537997608 ps
CPU time 27.9 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 198696 kb
Host smart-9935bc29-87d5-4931-9247-c3d20676a6fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490039543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2490039543
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1804659753
Short name T654
Test name
Test status
Simulation time 314598954 ps
CPU time 0.99 seconds
Started Jun 25 05:41:03 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 197812 kb
Host smart-421aa984-a62e-456e-a8d0-934a4016c6c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804659753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1804659753
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1909425772
Short name T175
Test name
Test status
Simulation time 52837146 ps
CPU time 0.83 seconds
Started Jun 25 05:40:51 PM PDT 24
Finished Jun 25 05:40:54 PM PDT 24
Peak memory 196356 kb
Host smart-8a4afa78-9a4b-474a-b38a-3b685418f694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909425772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1909425772
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2113173352
Short name T101
Test name
Test status
Simulation time 35446280 ps
CPU time 0.99 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 196736 kb
Host smart-05631fc7-ca67-4bc4-a5ab-0dab52d5bdf2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113173352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2113173352
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.34057370
Short name T591
Test name
Test status
Simulation time 32760055 ps
CPU time 1.08 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 196912 kb
Host smart-32306d49-5223-4998-bfc5-7a95eb937196
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.34057370
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3153222258
Short name T475
Test name
Test status
Simulation time 553127167 ps
CPU time 1.28 seconds
Started Jun 25 05:40:53 PM PDT 24
Finished Jun 25 05:40:57 PM PDT 24
Peak memory 197288 kb
Host smart-d19dd7c8-5e11-40d3-ba64-0ff6fff4167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153222258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3153222258
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.720232257
Short name T443
Test name
Test status
Simulation time 49693393 ps
CPU time 0.73 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:02 PM PDT 24
Peak memory 195016 kb
Host smart-e4e2d185-b483-4593-9a77-d6152e9b80ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720232257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.720232257
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.4269432873
Short name T3
Test name
Test status
Simulation time 966531396 ps
CPU time 3.27 seconds
Started Jun 25 05:40:59 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 198636 kb
Host smart-0437840f-814a-4f24-89c8-472b88a991c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269432873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.4269432873
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.4178327150
Short name T348
Test name
Test status
Simulation time 135960148 ps
CPU time 1.2 seconds
Started Jun 25 05:40:52 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 196352 kb
Host smart-9a8bda59-a383-43d7-a902-a3e4e1e8dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178327150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.4178327150
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2386134653
Short name T455
Test name
Test status
Simulation time 76764003 ps
CPU time 1.07 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 197188 kb
Host smart-fa31555e-2231-42c0-8ba4-a66114e491d0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386134653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2386134653
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2566454665
Short name T6
Test name
Test status
Simulation time 53676036568 ps
CPU time 155.63 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:43:33 PM PDT 24
Peak memory 198800 kb
Host smart-9de6482a-a5db-482f-8157-f948bbfe3e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566454665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2566454665
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1864032724
Short name T399
Test name
Test status
Simulation time 42179992 ps
CPU time 0.59 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 05:41:14 PM PDT 24
Peak memory 194676 kb
Host smart-5176268a-4dd4-4fc5-84c6-29ced102b64e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864032724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1864032724
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.56195550
Short name T151
Test name
Test status
Simulation time 14468911 ps
CPU time 0.67 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:02 PM PDT 24
Peak memory 195400 kb
Host smart-a0b98ff7-7f2f-4271-a29d-fb72f4e5d426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56195550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.56195550
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.867077304
Short name T690
Test name
Test status
Simulation time 221775879 ps
CPU time 11.08 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:14 PM PDT 24
Peak memory 198684 kb
Host smart-2fdc27b8-6d45-4bdb-804d-db78145e56f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867077304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.867077304
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2983436474
Short name T581
Test name
Test status
Simulation time 251482684 ps
CPU time 1.01 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:26 PM PDT 24
Peak memory 197340 kb
Host smart-a88ecdb6-fc13-4d15-963e-f2d7bfe01963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983436474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2983436474
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2885576490
Short name T254
Test name
Test status
Simulation time 106652542 ps
CPU time 1.09 seconds
Started Jun 25 05:41:03 PM PDT 24
Finished Jun 25 05:41:06 PM PDT 24
Peak memory 196800 kb
Host smart-84cb86cc-8017-4b5a-8d64-13f22110fbda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885576490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2885576490
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.424363258
Short name T362
Test name
Test status
Simulation time 203903454 ps
CPU time 2.54 seconds
Started Jun 25 05:40:59 PM PDT 24
Finished Jun 25 05:41:03 PM PDT 24
Peak memory 197920 kb
Host smart-fd391727-68c3-43b7-aee9-ba809a06de80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424363258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.424363258
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1342803044
Short name T244
Test name
Test status
Simulation time 559953351 ps
CPU time 2.5 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:41:00 PM PDT 24
Peak memory 198784 kb
Host smart-57354329-5fa1-4a63-96d6-7cfacf0ef3f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342803044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1342803044
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1108588687
Short name T320
Test name
Test status
Simulation time 340766904 ps
CPU time 1.19 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:03 PM PDT 24
Peak memory 197296 kb
Host smart-97c78bd4-d8d7-41a2-84da-c163ea367112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108588687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1108588687
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.270447806
Short name T492
Test name
Test status
Simulation time 101794091 ps
CPU time 1.09 seconds
Started Jun 25 05:40:54 PM PDT 24
Finished Jun 25 05:40:57 PM PDT 24
Peak memory 197404 kb
Host smart-febaf75c-90a9-49a6-abb8-5bee09fba474
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270447806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.270447806
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1975502738
Short name T595
Test name
Test status
Simulation time 90364448 ps
CPU time 1.27 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 198624 kb
Host smart-8aed3cb5-f975-467f-8c99-841160dd1592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975502738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1975502738
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1680711909
Short name T633
Test name
Test status
Simulation time 42088249 ps
CPU time 1.27 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 197160 kb
Host smart-ab0c7829-ff90-4fba-b084-49ddfa7e3eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680711909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1680711909
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.462942955
Short name T715
Test name
Test status
Simulation time 60229303 ps
CPU time 1.09 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 196964 kb
Host smart-b435b221-6585-4f34-9552-ad1e24fe491a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462942955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.462942955
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3542994887
Short name T458
Test name
Test status
Simulation time 30575965341 ps
CPU time 190.43 seconds
Started Jun 25 05:41:03 PM PDT 24
Finished Jun 25 05:44:16 PM PDT 24
Peak memory 198844 kb
Host smart-76631bf0-9ae1-4300-b657-06831cd103cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542994887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3542994887
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2451837988
Short name T570
Test name
Test status
Simulation time 68990112883 ps
CPU time 519.25 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:49:41 PM PDT 24
Peak memory 198920 kb
Host smart-e8be64b7-57b8-4569-a739-4d66b2e48ef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2451837988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2451837988
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2174233232
Short name T597
Test name
Test status
Simulation time 18629460 ps
CPU time 0.55 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 194632 kb
Host smart-0492f731-60cf-439d-97eb-2acfa1f1fff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174233232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2174233232
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3119936545
Short name T126
Test name
Test status
Simulation time 33037476 ps
CPU time 0.82 seconds
Started Jun 25 05:41:02 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 196728 kb
Host smart-0f44907d-9af2-4c59-a9ec-b89effe3cc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119936545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3119936545
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.24462395
Short name T327
Test name
Test status
Simulation time 1885543698 ps
CPU time 18.02 seconds
Started Jun 25 05:41:05 PM PDT 24
Finished Jun 25 05:41:24 PM PDT 24
Peak memory 197468 kb
Host smart-1473c77d-68eb-46d3-a93d-7473b3f24af5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24462395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.24462395
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1965117689
Short name T675
Test name
Test status
Simulation time 100334454 ps
CPU time 0.94 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 197688 kb
Host smart-0c9cf39d-700d-4488-a8bc-14b16f240dcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965117689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1965117689
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.683632568
Short name T354
Test name
Test status
Simulation time 377473142 ps
CPU time 0.82 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 196044 kb
Host smart-49eff203-395a-4f45-a64c-ccc1d0d440cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683632568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.683632568
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2163693930
Short name T162
Test name
Test status
Simulation time 742572373 ps
CPU time 2.54 seconds
Started Jun 25 05:40:55 PM PDT 24
Finished Jun 25 05:41:00 PM PDT 24
Peak memory 198740 kb
Host smart-5f32274c-7c9a-4999-b81f-6f5e83673c75
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163693930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2163693930
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.806572282
Short name T655
Test name
Test status
Simulation time 460348904 ps
CPU time 3.06 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:41:01 PM PDT 24
Peak memory 196448 kb
Host smart-3b285720-35b5-429a-b860-5936164e4c15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806572282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
806572282
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3401740115
Short name T366
Test name
Test status
Simulation time 22199282 ps
CPU time 0.8 seconds
Started Jun 25 05:40:56 PM PDT 24
Finished Jun 25 05:40:59 PM PDT 24
Peak memory 196048 kb
Host smart-ffcc4263-c65a-4854-9ae0-4c3a059db05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401740115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3401740115
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3465165337
Short name T164
Test name
Test status
Simulation time 63770364 ps
CPU time 1.18 seconds
Started Jun 25 05:40:50 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 196528 kb
Host smart-b03748ea-8da9-436d-b019-03d93fae43fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465165337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3465165337
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.992223537
Short name T592
Test name
Test status
Simulation time 302494125 ps
CPU time 4.98 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 05:41:17 PM PDT 24
Peak memory 198552 kb
Host smart-0fc8f8af-0c7b-4830-b31e-586dc840fb16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992223537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.992223537
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.843196536
Short name T315
Test name
Test status
Simulation time 32226083 ps
CPU time 1.04 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:03 PM PDT 24
Peak memory 196604 kb
Host smart-7f9e461a-706c-4ff1-a5b2-642b0cf71a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843196536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.843196536
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3546069589
Short name T243
Test name
Test status
Simulation time 178479756 ps
CPU time 1.6 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 198716 kb
Host smart-1cd00411-6461-4475-9479-43c593872cfc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546069589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3546069589
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2567877037
Short name T525
Test name
Test status
Simulation time 42259667438 ps
CPU time 144.01 seconds
Started Jun 25 05:40:59 PM PDT 24
Finished Jun 25 05:43:24 PM PDT 24
Peak memory 198816 kb
Host smart-e5415173-919e-474f-93b2-09b085af1b1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567877037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2567877037
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.67172837
Short name T665
Test name
Test status
Simulation time 41211802 ps
CPU time 0.61 seconds
Started Jun 25 05:41:02 PM PDT 24
Finished Jun 25 05:41:04 PM PDT 24
Peak memory 195236 kb
Host smart-c1225e07-c6c2-4e6c-bd22-3e2c92698103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67172837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.67172837
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3725949579
Short name T131
Test name
Test status
Simulation time 91841431 ps
CPU time 0.93 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:02 PM PDT 24
Peak memory 197896 kb
Host smart-f421f2ba-c7ad-416a-8c62-b2d2df2ae0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725949579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3725949579
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2798412853
Short name T290
Test name
Test status
Simulation time 919786260 ps
CPU time 27.25 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:29 PM PDT 24
Peak memory 197304 kb
Host smart-3525b708-af37-4890-aaa6-b2be01d8986d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798412853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2798412853
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2385977742
Short name T208
Test name
Test status
Simulation time 43211322 ps
CPU time 0.87 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 196124 kb
Host smart-effa4530-72ac-4d00-a690-92e26fd90a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385977742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2385977742
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2977765935
Short name T437
Test name
Test status
Simulation time 299513265 ps
CPU time 3.14 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:13 PM PDT 24
Peak memory 198744 kb
Host smart-86e74ae3-150b-4b14-a686-9275ddb4e017
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977765935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2977765935
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2478530695
Short name T174
Test name
Test status
Simulation time 183654701 ps
CPU time 1.6 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:41:09 PM PDT 24
Peak memory 196828 kb
Host smart-609aa8b5-b936-419d-85d7-6cd209ebed40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478530695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2478530695
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1725508095
Short name T419
Test name
Test status
Simulation time 92951208 ps
CPU time 1.11 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 197396 kb
Host smart-5c226a1f-0bf5-4098-952d-ec6085d0594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725508095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1725508095
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2048579719
Short name T298
Test name
Test status
Simulation time 101038939 ps
CPU time 0.97 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 196612 kb
Host smart-eb32cc78-1238-4b34-a6d3-2114b0d27546
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048579719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2048579719
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2540101817
Short name T533
Test name
Test status
Simulation time 498243926 ps
CPU time 5.55 seconds
Started Jun 25 05:40:59 PM PDT 24
Finished Jun 25 05:41:06 PM PDT 24
Peak memory 198664 kb
Host smart-bdc12e25-4f68-4081-a6fa-93672ddd5e23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540101817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2540101817
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.4140657029
Short name T456
Test name
Test status
Simulation time 72136225 ps
CPU time 1.28 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 196968 kb
Host smart-8f1ddfe5-689a-4318-921d-0c3c63ae22b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140657029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.4140657029
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3973180740
Short name T704
Test name
Test status
Simulation time 87490293 ps
CPU time 0.86 seconds
Started Jun 25 05:41:01 PM PDT 24
Finished Jun 25 05:41:03 PM PDT 24
Peak memory 197108 kb
Host smart-ca9984cf-0b7c-4e70-9e31-8f3108149516
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973180740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3973180740
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.30277047
Short name T685
Test name
Test status
Simulation time 75019764932 ps
CPU time 117.38 seconds
Started Jun 25 05:41:10 PM PDT 24
Finished Jun 25 05:43:10 PM PDT 24
Peak memory 198816 kb
Host smart-befa60b0-418c-44e7-abd1-cf127b044f1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30277047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gp
io_stress_all.30277047
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1067975094
Short name T53
Test name
Test status
Simulation time 20726184140 ps
CPU time 588.31 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:51:06 PM PDT 24
Peak memory 198972 kb
Host smart-518ed34d-d73c-49e3-8f3d-5f415d208344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1067975094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1067975094
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3854623456
Short name T192
Test name
Test status
Simulation time 19234185 ps
CPU time 0.61 seconds
Started Jun 25 05:40:59 PM PDT 24
Finished Jun 25 05:41:01 PM PDT 24
Peak memory 194916 kb
Host smart-d6c23912-e0cf-4c9e-aa4b-0b6306f1499d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854623456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3854623456
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3801853296
Short name T554
Test name
Test status
Simulation time 148591923 ps
CPU time 0.96 seconds
Started Jun 25 05:41:04 PM PDT 24
Finished Jun 25 05:41:07 PM PDT 24
Peak memory 197160 kb
Host smart-76c15933-8a24-48a5-abd5-9601445b4583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801853296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3801853296
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3218597690
Short name T441
Test name
Test status
Simulation time 2557089009 ps
CPU time 20.67 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:38 PM PDT 24
Peak memory 197644 kb
Host smart-9303910b-489c-4f08-91d3-472492e2d6e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218597690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3218597690
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1663965911
Short name T624
Test name
Test status
Simulation time 123207068 ps
CPU time 0.76 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 195384 kb
Host smart-de01c12a-13db-4dc6-a403-170d102da5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663965911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1663965911
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.4052877614
Short name T464
Test name
Test status
Simulation time 84940052 ps
CPU time 0.87 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 196556 kb
Host smart-7176aa29-cf7f-474a-875e-37f5dd2535aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052877614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4052877614
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2056824081
Short name T588
Test name
Test status
Simulation time 93277713 ps
CPU time 4.02 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:41:11 PM PDT 24
Peak memory 198736 kb
Host smart-227c8d7a-b3be-493a-a5cb-92f184881bd7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056824081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2056824081
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1337485569
Short name T113
Test name
Test status
Simulation time 83035791 ps
CPU time 1.04 seconds
Started Jun 25 05:40:58 PM PDT 24
Finished Jun 25 05:41:01 PM PDT 24
Peak memory 196232 kb
Host smart-356254c3-81c6-4f18-8da0-071b7ce6201b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337485569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1337485569
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2001151660
Short name T200
Test name
Test status
Simulation time 42888771 ps
CPU time 1.13 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 05:41:13 PM PDT 24
Peak memory 197744 kb
Host smart-87cb2a62-2e4b-4c26-bd32-5fa5c93c1d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001151660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2001151660
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1179931443
Short name T678
Test name
Test status
Simulation time 76030839 ps
CPU time 0.87 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:11 PM PDT 24
Peak memory 196728 kb
Host smart-bbf68396-12cb-4ec8-9e8a-83445427faab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179931443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1179931443
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3596066461
Short name T204
Test name
Test status
Simulation time 62441147 ps
CPU time 1.58 seconds
Started Jun 25 05:41:02 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 198428 kb
Host smart-afb2517c-d1fa-44d0-8c5e-420db466a6d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596066461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3596066461
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.514630856
Short name T201
Test name
Test status
Simulation time 350123323 ps
CPU time 1.54 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:41:09 PM PDT 24
Peak memory 197436 kb
Host smart-a628bc5c-da27-40fb-8d88-4f7f63fbab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514630856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.514630856
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2581749698
Short name T599
Test name
Test status
Simulation time 220067169 ps
CPU time 1.43 seconds
Started Jun 25 05:41:03 PM PDT 24
Finished Jun 25 05:41:06 PM PDT 24
Peak memory 197220 kb
Host smart-932116c3-cf78-43fa-8965-52e9a31697ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581749698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2581749698
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.622858525
Short name T135
Test name
Test status
Simulation time 5125959367 ps
CPU time 39.73 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 198812 kb
Host smart-453d6277-e144-446a-b1d3-cc6e98af88ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622858525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.622858525
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3071701788
Short name T57
Test name
Test status
Simulation time 79102639062 ps
CPU time 1615.29 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 06:08:10 PM PDT 24
Peak memory 198940 kb
Host smart-e1bba77a-5d1a-4697-aac8-bc3343ac6b6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3071701788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3071701788
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1264942797
Short name T582
Test name
Test status
Simulation time 22956136 ps
CPU time 0.61 seconds
Started Jun 25 05:40:13 PM PDT 24
Finished Jun 25 05:40:15 PM PDT 24
Peak memory 194860 kb
Host smart-38b1be3f-f4c1-4105-a6f4-0f0632383fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264942797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1264942797
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2603308037
Short name T694
Test name
Test status
Simulation time 49634013 ps
CPU time 0.63 seconds
Started Jun 25 05:40:08 PM PDT 24
Finished Jun 25 05:40:10 PM PDT 24
Peak memory 194712 kb
Host smart-ded621bb-193e-4909-8d2f-747c8b884f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603308037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2603308037
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3229144950
Short name T572
Test name
Test status
Simulation time 4518051702 ps
CPU time 22.95 seconds
Started Jun 25 05:40:08 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 197452 kb
Host smart-a099a995-4024-4b6a-ac7f-94ef3d9f686e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229144950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3229144950
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2076779557
Short name T548
Test name
Test status
Simulation time 89698817 ps
CPU time 1.01 seconds
Started Jun 25 05:40:13 PM PDT 24
Finished Jun 25 05:40:15 PM PDT 24
Peak memory 197840 kb
Host smart-f047eaa6-df75-4fce-81ae-f8c94ebc3fdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076779557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2076779557
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2367449949
Short name T146
Test name
Test status
Simulation time 25287053 ps
CPU time 0.71 seconds
Started Jun 25 05:40:11 PM PDT 24
Finished Jun 25 05:40:13 PM PDT 24
Peak memory 195812 kb
Host smart-8a2189e2-b595-4158-8518-128a5cc0fdcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367449949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2367449949
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3847825947
Short name T102
Test name
Test status
Simulation time 22043971 ps
CPU time 0.92 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:12 PM PDT 24
Peak memory 196572 kb
Host smart-bb84ce31-6c7f-46f9-ba3d-05e9a7d64c98
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847825947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3847825947
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3906062107
Short name T385
Test name
Test status
Simulation time 127847825 ps
CPU time 2.22 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 196504 kb
Host smart-b4039602-a10f-4666-88b9-adcd05322ad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906062107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3906062107
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1884268743
Short name T212
Test name
Test status
Simulation time 187837681 ps
CPU time 0.84 seconds
Started Jun 25 05:40:10 PM PDT 24
Finished Jun 25 05:40:12 PM PDT 24
Peak memory 196196 kb
Host smart-a55804e2-53ff-4050-a7f1-c8fb3257817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884268743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1884268743
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4171403267
Short name T538
Test name
Test status
Simulation time 23475913 ps
CPU time 0.86 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:40:17 PM PDT 24
Peak memory 197176 kb
Host smart-c335d77b-54bb-4b4b-9b36-d64ab39eb9a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171403267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4171403267
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1284376652
Short name T7
Test name
Test status
Simulation time 442972663 ps
CPU time 4.5 seconds
Started Jun 25 05:40:19 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 198692 kb
Host smart-6fc1bef0-fe0d-4c02-8dbd-e98b1ef44aca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284376652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1284376652
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.1353956980
Short name T323
Test name
Test status
Simulation time 157493460 ps
CPU time 1.2 seconds
Started Jun 25 05:40:11 PM PDT 24
Finished Jun 25 05:40:13 PM PDT 24
Peak memory 197532 kb
Host smart-e72cf871-7234-4861-a421-200396246f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353956980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1353956980
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3910766944
Short name T562
Test name
Test status
Simulation time 190856140 ps
CPU time 0.84 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:40:17 PM PDT 24
Peak memory 195896 kb
Host smart-32875edd-9815-4e54-b0b2-f8e941db0b96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910766944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3910766944
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2124921470
Short name T9
Test name
Test status
Simulation time 41670318937 ps
CPU time 119.17 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:42:15 PM PDT 24
Peak memory 198784 kb
Host smart-6e4857a8-4807-426b-801b-b45a8049949f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124921470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2124921470
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.4255506640
Short name T58
Test name
Test status
Simulation time 189991685651 ps
CPU time 1081.37 seconds
Started Jun 25 05:40:08 PM PDT 24
Finished Jun 25 05:58:11 PM PDT 24
Peak memory 198988 kb
Host smart-797e54ea-9a3d-4b3d-a4f0-1cdfc5da702a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4255506640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.4255506640
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3529634686
Short name T513
Test name
Test status
Simulation time 62406129 ps
CPU time 0.57 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:23 PM PDT 24
Peak memory 195384 kb
Host smart-36e0b73e-ae78-486a-a862-f5390f745c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529634686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3529634686
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2990162251
Short name T564
Test name
Test status
Simulation time 257118185 ps
CPU time 0.77 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 05:41:14 PM PDT 24
Peak memory 196552 kb
Host smart-5af5c7d9-cbd0-4812-84a2-4956ca7936c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990162251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2990162251
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3082061526
Short name T589
Test name
Test status
Simulation time 137712456 ps
CPU time 4 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:06 PM PDT 24
Peak memory 196660 kb
Host smart-6b6ddacc-91b3-4b1e-83d8-65e402142f9d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082061526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3082061526
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3458850284
Short name T223
Test name
Test status
Simulation time 84985487 ps
CPU time 1.17 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:41:09 PM PDT 24
Peak memory 197080 kb
Host smart-7293be21-c5a1-47a0-9eed-3eef40ec3cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458850284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3458850284
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2756395448
Short name T688
Test name
Test status
Simulation time 216333561 ps
CPU time 1.11 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:17 PM PDT 24
Peak memory 196696 kb
Host smart-bb97b704-3514-4097-ac94-be5157f0c51a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756395448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2756395448
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.730184924
Short name T309
Test name
Test status
Simulation time 393415069 ps
CPU time 3.64 seconds
Started Jun 25 05:40:58 PM PDT 24
Finished Jun 25 05:41:03 PM PDT 24
Peak memory 198776 kb
Host smart-854c544b-f77c-46a1-ba53-cbfa5ae9bcec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730184924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.730184924
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3050857373
Short name T381
Test name
Test status
Simulation time 73781611 ps
CPU time 1.78 seconds
Started Jun 25 05:41:10 PM PDT 24
Finished Jun 25 05:41:14 PM PDT 24
Peak memory 196832 kb
Host smart-fa478956-c070-482a-a1e2-5977e72dc980
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050857373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3050857373
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.4281887543
Short name T537
Test name
Test status
Simulation time 17235148 ps
CPU time 0.63 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 195620 kb
Host smart-28874426-76e8-4018-95a7-1922af08e525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281887543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.4281887543
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3068670563
Short name T198
Test name
Test status
Simulation time 60819078 ps
CPU time 1.31 seconds
Started Jun 25 05:41:00 PM PDT 24
Finished Jun 25 05:41:03 PM PDT 24
Peak memory 197620 kb
Host smart-02f767de-5359-4241-8a9d-338e8981ce72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068670563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3068670563
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3797340349
Short name T600
Test name
Test status
Simulation time 327332853 ps
CPU time 5.36 seconds
Started Jun 25 05:41:02 PM PDT 24
Finished Jun 25 05:41:08 PM PDT 24
Peak memory 198556 kb
Host smart-b2c39517-d3d8-4f6c-8e23-77b53cf3ce45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797340349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3797340349
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2073584101
Short name T220
Test name
Test status
Simulation time 50617069 ps
CPU time 0.98 seconds
Started Jun 25 05:41:10 PM PDT 24
Finished Jun 25 05:41:14 PM PDT 24
Peak memory 197184 kb
Host smart-38ca33ec-8290-4690-8eef-09a2cc793fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073584101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2073584101
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.445949600
Short name T197
Test name
Test status
Simulation time 196297901 ps
CPU time 1.02 seconds
Started Jun 25 05:40:58 PM PDT 24
Finished Jun 25 05:41:01 PM PDT 24
Peak memory 197180 kb
Host smart-0406508f-be6f-4c50-b8d0-c4eeeb41b5cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445949600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.445949600
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2716152385
Short name T380
Test name
Test status
Simulation time 34386406168 ps
CPU time 102.63 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:42:52 PM PDT 24
Peak memory 198828 kb
Host smart-f8f5543e-5567-4fa6-813e-4522206dcebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716152385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2716152385
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.2878592210
Short name T91
Test name
Test status
Simulation time 42099554147 ps
CPU time 608.75 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:51:24 PM PDT 24
Peak memory 198924 kb
Host smart-65206011-04b2-4c85-9971-c4cdc86acd7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2878592210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.2878592210
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1529711505
Short name T355
Test name
Test status
Simulation time 51019967 ps
CPU time 0.57 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:12 PM PDT 24
Peak memory 194896 kb
Host smart-8ef1fc56-6650-43b1-a25b-95d47a02fd84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529711505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1529711505
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.333740172
Short name T304
Test name
Test status
Simulation time 69585629 ps
CPU time 0.84 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:17 PM PDT 24
Peak memory 196048 kb
Host smart-da78e663-b8e8-4484-bd35-50772ba4a6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333740172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.333740172
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3345540988
Short name T504
Test name
Test status
Simulation time 458775197 ps
CPU time 21.84 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:33 PM PDT 24
Peak memory 198692 kb
Host smart-6843d8f9-0786-4aa8-90c8-25ee9d78b03c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345540988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3345540988
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1074276322
Short name T516
Test name
Test status
Simulation time 130338001 ps
CPU time 0.74 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:17 PM PDT 24
Peak memory 196016 kb
Host smart-f41e68f7-5c60-4619-930d-2e4d584212e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074276322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1074276322
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1875583040
Short name T139
Test name
Test status
Simulation time 221451151 ps
CPU time 1.21 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 197400 kb
Host smart-883ebbba-a7c3-45c6-a7ac-581dbca2e082
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875583040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1875583040
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.755792038
Short name T98
Test name
Test status
Simulation time 160284851 ps
CPU time 1.71 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 197876 kb
Host smart-215bd1e8-c275-4ee1-8a1f-ec78e838cf68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755792038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.755792038
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.4085256005
Short name T711
Test name
Test status
Simulation time 114016506 ps
CPU time 2.2 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 197480 kb
Host smart-685e4d60-95fc-4a74-8394-500661fe2577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085256005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.4085256005
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2474061849
Short name T488
Test name
Test status
Simulation time 19129243 ps
CPU time 0.74 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 195016 kb
Host smart-4e9c9060-7e34-4275-a789-a3a025fc2b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474061849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2474061849
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.924362401
Short name T662
Test name
Test status
Simulation time 25875098 ps
CPU time 0.99 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 197496 kb
Host smart-35485ac2-4135-462c-9159-007d0a6833aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924362401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.924362401
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1442212653
Short name T312
Test name
Test status
Simulation time 589757122 ps
CPU time 7.06 seconds
Started Jun 25 05:41:17 PM PDT 24
Finished Jun 25 05:41:27 PM PDT 24
Peak memory 198644 kb
Host smart-3f34fca8-64ab-4400-8514-49ffb8bfea87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442212653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1442212653
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3202851720
Short name T129
Test name
Test status
Simulation time 134659718 ps
CPU time 1.5 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:13 PM PDT 24
Peak memory 197136 kb
Host smart-9277b231-fd7a-4d04-8eca-ae2a7a644138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202851720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3202851720
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.330903516
Short name T324
Test name
Test status
Simulation time 79963121 ps
CPU time 1.28 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 197244 kb
Host smart-8f9097e3-b65f-47d8-9ec1-dbdd23e22a81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330903516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.330903516
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3283113937
Short name T482
Test name
Test status
Simulation time 43982824661 ps
CPU time 167.49 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:43:55 PM PDT 24
Peak memory 198804 kb
Host smart-c77fddbd-e966-41b6-ae61-b32ca382e104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283113937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3283113937
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2561888497
Short name T532
Test name
Test status
Simulation time 431838389659 ps
CPU time 2966.8 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 06:30:43 PM PDT 24
Peak memory 198936 kb
Host smart-3962711b-373e-4436-9b5e-db6ca6ea7d11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2561888497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2561888497
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1410179384
Short name T406
Test name
Test status
Simulation time 15283250 ps
CPU time 0.61 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 194904 kb
Host smart-7c6d538e-2110-4c58-809f-6b456bea4413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410179384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1410179384
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3268006567
Short name T189
Test name
Test status
Simulation time 41975597 ps
CPU time 0.81 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 196056 kb
Host smart-219a5565-c45b-49e2-984b-bd1fa2cd8cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268006567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3268006567
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2887680471
Short name T255
Test name
Test status
Simulation time 449704508 ps
CPU time 12.02 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:23 PM PDT 24
Peak memory 197708 kb
Host smart-3856b405-677d-456c-a691-140eb1d28d8e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887680471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2887680471
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2310870792
Short name T698
Test name
Test status
Simulation time 178227606 ps
CPU time 0.77 seconds
Started Jun 25 05:41:05 PM PDT 24
Finished Jun 25 05:41:07 PM PDT 24
Peak memory 197192 kb
Host smart-c2ce740e-d200-4211-8d33-cb89560e4508
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310870792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2310870792
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1454353385
Short name T347
Test name
Test status
Simulation time 334052301 ps
CPU time 1.06 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 05:41:15 PM PDT 24
Peak memory 197168 kb
Host smart-7b8b2bb1-3999-45e9-9c05-acd2d170c83a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454353385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1454353385
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2218345555
Short name T270
Test name
Test status
Simulation time 774372280 ps
CPU time 3.34 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 05:41:15 PM PDT 24
Peak memory 198776 kb
Host smart-1926b7db-5de8-45a5-a276-83c2097293f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218345555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2218345555
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1941289039
Short name T459
Test name
Test status
Simulation time 389640507 ps
CPU time 2.11 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:13 PM PDT 24
Peak memory 197184 kb
Host smart-f402e6a3-02f8-467a-9366-e79e44209a80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941289039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1941289039
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2136017293
Short name T669
Test name
Test status
Simulation time 514145331 ps
CPU time 1.05 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 196688 kb
Host smart-52e0c27d-6e53-4925-97d5-eee20fe2e94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136017293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2136017293
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.698832868
Short name T92
Test name
Test status
Simulation time 158128684 ps
CPU time 0.94 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 05:41:13 PM PDT 24
Peak memory 196716 kb
Host smart-0508796f-e068-4307-85b8-c579e465a25b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698832868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.698832868
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2475693570
Short name T218
Test name
Test status
Simulation time 219343695 ps
CPU time 2.63 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 05:41:14 PM PDT 24
Peak memory 198668 kb
Host smart-b4359eff-71a8-450c-bc68-baa39ed25e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475693570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2475693570
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3680371472
Short name T470
Test name
Test status
Simulation time 55514140 ps
CPU time 1.06 seconds
Started Jun 25 05:41:06 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 196296 kb
Host smart-e2b8fa47-6285-4eb7-979b-79d43a562f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680371472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3680371472
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.743311093
Short name T468
Test name
Test status
Simulation time 168496386 ps
CPU time 1.37 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 05:41:15 PM PDT 24
Peak memory 197476 kb
Host smart-a88a82fd-e2c5-4b68-a86a-24c2920d7720
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743311093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.743311093
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3430163418
Short name T4
Test name
Test status
Simulation time 11983134767 ps
CPU time 132.06 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 05:43:25 PM PDT 24
Peak memory 198848 kb
Host smart-8e9d6582-a6e7-4805-8023-f8e700b3c0c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430163418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3430163418
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1234932879
Short name T614
Test name
Test status
Simulation time 104111726780 ps
CPU time 2021.14 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 06:14:53 PM PDT 24
Peak memory 198956 kb
Host smart-d21f53d7-d6f4-458f-9493-79811573b98e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1234932879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1234932879
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.4262885475
Short name T30
Test name
Test status
Simulation time 17000671 ps
CPU time 0.62 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 194884 kb
Host smart-1fad3894-34a9-41bc-a3a9-dbc563e97f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262885475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4262885475
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2955821971
Short name T280
Test name
Test status
Simulation time 83046447 ps
CPU time 0.75 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:17 PM PDT 24
Peak memory 196608 kb
Host smart-bd6e2fce-3f3a-4aea-af86-595c0f0f8084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955821971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2955821971
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.507087340
Short name T474
Test name
Test status
Simulation time 445784583 ps
CPU time 14.18 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:32 PM PDT 24
Peak memory 197484 kb
Host smart-45940fa8-3328-4469-a0c1-0ff3b3ee9a8a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507087340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.507087340
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.395691641
Short name T411
Test name
Test status
Simulation time 58577134 ps
CPU time 0.91 seconds
Started Jun 25 05:41:08 PM PDT 24
Finished Jun 25 05:41:11 PM PDT 24
Peak memory 196820 kb
Host smart-b268ac2a-51a0-4191-9598-d401f177a186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395691641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.395691641
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3617517342
Short name T413
Test name
Test status
Simulation time 43631455 ps
CPU time 1.3 seconds
Started Jun 25 05:41:09 PM PDT 24
Finished Jun 25 05:41:13 PM PDT 24
Peak memory 197488 kb
Host smart-e58a482d-7444-4aae-a987-e2554c930ef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617517342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3617517342
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3910480873
Short name T645
Test name
Test status
Simulation time 81817512 ps
CPU time 0.99 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:17 PM PDT 24
Peak memory 197384 kb
Host smart-5e549a71-b675-45fa-bcb6-69c74fba57d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910480873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3910480873
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3351243064
Short name T653
Test name
Test status
Simulation time 105567349 ps
CPU time 2.41 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:11 PM PDT 24
Peak memory 197652 kb
Host smart-2930181d-d469-47d1-8fc1-dfe94962b0a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351243064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3351243064
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.4095673680
Short name T60
Test name
Test status
Simulation time 134853309 ps
CPU time 0.69 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 195980 kb
Host smart-cd0d0f71-e2b2-4c8b-85d4-e97dae46963c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095673680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.4095673680
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4094114049
Short name T398
Test name
Test status
Simulation time 102415956 ps
CPU time 1.2 seconds
Started Jun 25 05:41:11 PM PDT 24
Finished Jun 25 05:41:15 PM PDT 24
Peak memory 197732 kb
Host smart-ebd92c90-c0ae-4780-9ab2-9bddf3616107
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094114049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4094114049
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2363522964
Short name T265
Test name
Test status
Simulation time 129040362 ps
CPU time 1.85 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 198648 kb
Host smart-e9814db2-7579-470f-b7b3-e18445812ffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363522964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2363522964
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2825622574
Short name T286
Test name
Test status
Simulation time 59658504 ps
CPU time 1.29 seconds
Started Jun 25 05:41:05 PM PDT 24
Finished Jun 25 05:41:08 PM PDT 24
Peak memory 196436 kb
Host smart-d692419d-c116-4a9b-b9db-e09e6ca2f824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825622574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2825622574
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3858537498
Short name T145
Test name
Test status
Simulation time 51419053 ps
CPU time 1.01 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 197156 kb
Host smart-19d84876-1537-44f9-8552-29023874e1c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858537498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3858537498
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1398470400
Short name T392
Test name
Test status
Simulation time 18413594079 ps
CPU time 49.22 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 198824 kb
Host smart-853e093e-405d-47ef-aec1-acdd3d2a2a61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398470400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1398470400
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2783973724
Short name T432
Test name
Test status
Simulation time 12495009 ps
CPU time 0.59 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 194696 kb
Host smart-373bbd14-d133-48fb-ba8a-40459105ce89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783973724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2783973724
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1720843744
Short name T565
Test name
Test status
Simulation time 68009141 ps
CPU time 0.66 seconds
Started Jun 25 05:41:17 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 194760 kb
Host smart-1e66874a-1ed2-438f-97c3-d553c92c474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720843744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1720843744
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4061610180
Short name T351
Test name
Test status
Simulation time 337361892 ps
CPU time 11.33 seconds
Started Jun 25 05:41:20 PM PDT 24
Finished Jun 25 05:41:33 PM PDT 24
Peak memory 196972 kb
Host smart-e4f67518-3a4a-42ca-bb95-036bbeb649b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061610180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4061610180
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3009012637
Short name T281
Test name
Test status
Simulation time 35191042 ps
CPU time 0.7 seconds
Started Jun 25 05:41:19 PM PDT 24
Finished Jun 25 05:41:22 PM PDT 24
Peak memory 195936 kb
Host smart-fccf0f24-811f-4018-b1c7-5ff6f1eda457
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009012637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3009012637
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2981817486
Short name T618
Test name
Test status
Simulation time 179414143 ps
CPU time 0.87 seconds
Started Jun 25 05:41:42 PM PDT 24
Finished Jun 25 05:41:44 PM PDT 24
Peak memory 197400 kb
Host smart-4ca9299e-037c-4cbe-9886-dbdb88204c8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981817486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2981817486
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.505712975
Short name T603
Test name
Test status
Simulation time 1229336398 ps
CPU time 3.76 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 198804 kb
Host smart-15954faa-ab53-4e79-bc8b-8a686e692a7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505712975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.505712975
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.87548009
Short name T545
Test name
Test status
Simulation time 1900397291 ps
CPU time 3.19 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 197488 kb
Host smart-085834c1-867a-4e95-861d-6aa2ee2434b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87548009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.87548009
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.649479598
Short name T12
Test name
Test status
Simulation time 28757918 ps
CPU time 0.68 seconds
Started Jun 25 05:41:07 PM PDT 24
Finished Jun 25 05:41:10 PM PDT 24
Peak memory 195104 kb
Host smart-e3c7fcf8-0547-41ea-b856-522dc9d60e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649479598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.649479598
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4021161330
Short name T183
Test name
Test status
Simulation time 159345508 ps
CPU time 1.01 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:16 PM PDT 24
Peak memory 197356 kb
Host smart-a2633f8e-6488-4f15-b21b-9385b814cee5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021161330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4021161330
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1256559828
Short name T205
Test name
Test status
Simulation time 48649150 ps
CPU time 2.31 seconds
Started Jun 25 05:41:20 PM PDT 24
Finished Jun 25 05:41:24 PM PDT 24
Peak memory 198656 kb
Host smart-0009f9c9-6a8a-44f6-805e-34bafb9efd8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256559828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1256559828
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.159701512
Short name T556
Test name
Test status
Simulation time 131941050 ps
CPU time 1.02 seconds
Started Jun 25 05:41:12 PM PDT 24
Finished Jun 25 05:41:15 PM PDT 24
Peak memory 197972 kb
Host smart-b1e1dbe9-994f-4954-98e6-cba1ff13771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159701512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.159701512
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.312750978
Short name T157
Test name
Test status
Simulation time 55587722 ps
CPU time 1.37 seconds
Started Jun 25 05:41:13 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 197524 kb
Host smart-3bf866c5-7dcd-4aef-ba03-690ace26312e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312750978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.312750978
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2362188569
Short name T409
Test name
Test status
Simulation time 110227285179 ps
CPU time 145.72 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:43:44 PM PDT 24
Peak memory 198824 kb
Host smart-6a6e34b5-e6bd-483d-8941-180543829af5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362188569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2362188569
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3353755375
Short name T568
Test name
Test status
Simulation time 36567432 ps
CPU time 0.58 seconds
Started Jun 25 05:41:27 PM PDT 24
Finished Jun 25 05:41:29 PM PDT 24
Peak memory 195368 kb
Host smart-b124334f-a4d6-4a5f-a175-4e5b087d7518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353755375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3353755375
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1808095154
Short name T708
Test name
Test status
Simulation time 129672590 ps
CPU time 0.81 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 196792 kb
Host smart-966987f5-8684-4f45-8f32-1b1e8010efdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808095154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1808095154
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2508979897
Short name T18
Test name
Test status
Simulation time 1010333440 ps
CPU time 30.12 seconds
Started Jun 25 05:41:25 PM PDT 24
Finished Jun 25 05:41:56 PM PDT 24
Peak memory 196484 kb
Host smart-ae709363-b328-4e74-ab70-72d8af5df1ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508979897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2508979897
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1457021180
Short name T467
Test name
Test status
Simulation time 39518450 ps
CPU time 0.74 seconds
Started Jun 25 05:41:17 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 195500 kb
Host smart-04141738-68de-4a8e-a49f-b8b4133c1d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457021180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1457021180
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2158729700
Short name T216
Test name
Test status
Simulation time 375080128 ps
CPU time 1.23 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 196496 kb
Host smart-c27727e9-28b8-4d97-9221-ceb79154fe8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158729700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2158729700
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3833231419
Short name T465
Test name
Test status
Simulation time 26110765 ps
CPU time 1.12 seconds
Started Jun 25 05:41:35 PM PDT 24
Finished Jun 25 05:41:37 PM PDT 24
Peak memory 197952 kb
Host smart-d7ed221b-b881-4506-b328-ba254206487a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833231419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3833231419
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2947438289
Short name T344
Test name
Test status
Simulation time 349920039 ps
CPU time 2.14 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 196748 kb
Host smart-ebbc146b-1b2e-425e-9256-3eeed281b7a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947438289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2947438289
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1088385542
Short name T253
Test name
Test status
Simulation time 39054015 ps
CPU time 0.84 seconds
Started Jun 25 05:41:20 PM PDT 24
Finished Jun 25 05:41:22 PM PDT 24
Peak memory 197348 kb
Host smart-51f63d68-8b04-4563-9888-23fd4af0c5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088385542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1088385542
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3035232298
Short name T121
Test name
Test status
Simulation time 63173838 ps
CPU time 0.7 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 195708 kb
Host smart-43882913-8527-4cbe-b68c-b02abd4274fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035232298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3035232298
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2280205947
Short name T601
Test name
Test status
Simulation time 1578283606 ps
CPU time 6.2 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:25 PM PDT 24
Peak memory 198692 kb
Host smart-a156b3d8-7468-407c-9109-90023d906db9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280205947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2280205947
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3972455636
Short name T334
Test name
Test status
Simulation time 129240869 ps
CPU time 1.35 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 196252 kb
Host smart-6d51ef9d-38d5-415c-a11c-b808d1f86fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972455636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3972455636
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2701701226
Short name T94
Test name
Test status
Simulation time 108810367 ps
CPU time 1.31 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:27 PM PDT 24
Peak memory 197488 kb
Host smart-38c4901b-29ef-4a9e-9745-cb169a467553
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701701226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2701701226
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.896091300
Short name T169
Test name
Test status
Simulation time 2589077840 ps
CPU time 33.01 seconds
Started Jun 25 05:41:17 PM PDT 24
Finished Jun 25 05:41:53 PM PDT 24
Peak memory 198808 kb
Host smart-84e0a332-84d6-4368-88fc-298d1f845820
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896091300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.896091300
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.124070078
Short name T445
Test name
Test status
Simulation time 16500355 ps
CPU time 0.58 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 194844 kb
Host smart-2c6ef1e4-4477-486e-9a00-8ef413d41b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124070078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.124070078
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3034494889
Short name T641
Test name
Test status
Simulation time 16000564 ps
CPU time 0.68 seconds
Started Jun 25 05:41:20 PM PDT 24
Finished Jun 25 05:41:22 PM PDT 24
Peak memory 194548 kb
Host smart-51220bc6-d8fc-4650-8a34-1b8f43e3de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034494889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3034494889
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3238025152
Short name T274
Test name
Test status
Simulation time 1743894406 ps
CPU time 14.62 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:34 PM PDT 24
Peak memory 198712 kb
Host smart-29e6f7af-3870-4522-9894-379042fcbbd7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238025152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3238025152
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4246476652
Short name T448
Test name
Test status
Simulation time 53071505 ps
CPU time 0.88 seconds
Started Jun 25 05:41:19 PM PDT 24
Finished Jun 25 05:41:22 PM PDT 24
Peak memory 196556 kb
Host smart-5de98f78-1e31-4fc1-aa8d-56645b66fe99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246476652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4246476652
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.991931658
Short name T501
Test name
Test status
Simulation time 102478026 ps
CPU time 0.9 seconds
Started Jun 25 05:41:19 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 197400 kb
Host smart-ddddc43c-ffe2-4bb5-bb21-a60a289e94b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991931658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.991931658
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.4188800737
Short name T305
Test name
Test status
Simulation time 182755455 ps
CPU time 1.84 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 198672 kb
Host smart-698afb15-d199-4a75-ac7e-479807b02ac2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188800737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.4188800737
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3617283376
Short name T282
Test name
Test status
Simulation time 86821721 ps
CPU time 2.61 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:22 PM PDT 24
Peak memory 197940 kb
Host smart-c444653f-dba6-448d-81f5-e75e68bc67c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617283376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3617283376
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1463857432
Short name T196
Test name
Test status
Simulation time 179872535 ps
CPU time 1.14 seconds
Started Jun 25 05:41:35 PM PDT 24
Finished Jun 25 05:41:38 PM PDT 24
Peak memory 197368 kb
Host smart-b2a604e1-46d5-4ce9-8e1b-fbbc287f7857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463857432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1463857432
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1926569135
Short name T575
Test name
Test status
Simulation time 24547466 ps
CPU time 0.84 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 196140 kb
Host smart-2456c589-1ad7-468d-bc79-5e8ddbd0423e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926569135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1926569135
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.82964767
Short name T693
Test name
Test status
Simulation time 249667035 ps
CPU time 1.26 seconds
Started Jun 25 05:41:17 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 198508 kb
Host smart-25c67502-38ec-41d7-98b8-84de0309a7f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82964767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand
om_long_reg_writes_reg_reads.82964767
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3863011741
Short name T417
Test name
Test status
Simulation time 112592946 ps
CPU time 1.24 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 197176 kb
Host smart-1254f999-79ae-4187-86c9-354bdde9d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863011741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3863011741
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3275441964
Short name T598
Test name
Test status
Simulation time 58621722 ps
CPU time 0.95 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 197088 kb
Host smart-4711f583-7f64-4280-8792-7f6bc4f53a68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275441964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3275441964
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2994890854
Short name T410
Test name
Test status
Simulation time 6328032356 ps
CPU time 40.82 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 198800 kb
Host smart-898ea0bd-39ba-42ed-be18-98838037d210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994890854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2994890854
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3846749676
Short name T322
Test name
Test status
Simulation time 95123311 ps
CPU time 0.57 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 195368 kb
Host smart-94a0044e-38ff-496f-bf84-6044b955b7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846749676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3846749676
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3299505610
Short name T93
Test name
Test status
Simulation time 194322238 ps
CPU time 0.76 seconds
Started Jun 25 05:41:19 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 196088 kb
Host smart-fa9a8b05-cb91-4713-9eee-e7a76d8b2777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299505610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3299505610
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2609273105
Short name T428
Test name
Test status
Simulation time 227583820 ps
CPU time 7.31 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:25 PM PDT 24
Peak memory 196932 kb
Host smart-09de8dc0-698e-4e88-bade-73cbbb705a10
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609273105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2609273105
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.50836940
Short name T275
Test name
Test status
Simulation time 40423423 ps
CPU time 0.72 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:18 PM PDT 24
Peak memory 195480 kb
Host smart-da5d3fa5-8cab-49a7-aa32-85d4610a2b89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50836940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.50836940
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.789258541
Short name T590
Test name
Test status
Simulation time 50056008 ps
CPU time 1.33 seconds
Started Jun 25 05:41:17 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 198724 kb
Host smart-fc8a78c1-8e42-4534-a8cc-10225730f7fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789258541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.789258541
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1739654199
Short name T673
Test name
Test status
Simulation time 24694732 ps
CPU time 1.09 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 196772 kb
Host smart-8e26030b-7047-4df0-9bf3-abcbfd320a0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739654199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1739654199
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.4073713924
Short name T384
Test name
Test status
Simulation time 59938783 ps
CPU time 1.25 seconds
Started Jun 25 05:41:14 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 197888 kb
Host smart-eb0a685d-f4cb-4b8f-a0b2-3d18d191fc78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073713924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.4073713924
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2546654875
Short name T496
Test name
Test status
Simulation time 592561705 ps
CPU time 1.2 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:26 PM PDT 24
Peak memory 197660 kb
Host smart-6575f7f3-2650-47ed-be05-229dce0efead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546654875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2546654875
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2359865729
Short name T530
Test name
Test status
Simulation time 21046539 ps
CPU time 0.66 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:26 PM PDT 24
Peak memory 194964 kb
Host smart-3463887c-49d4-498c-b726-cc98f90ac189
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359865729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2359865729
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.672763157
Short name T375
Test name
Test status
Simulation time 701421644 ps
CPU time 2.37 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:21 PM PDT 24
Peak memory 198616 kb
Host smart-59d6dbba-7052-471c-9c26-2f38be6de792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672763157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.672763157
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3465340991
Short name T195
Test name
Test status
Simulation time 102683818 ps
CPU time 1.18 seconds
Started Jun 25 05:41:15 PM PDT 24
Finished Jun 25 05:41:19 PM PDT 24
Peak memory 197212 kb
Host smart-2ce2f186-ddde-4a90-a0ab-ea23783ca49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465340991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3465340991
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3264726096
Short name T440
Test name
Test status
Simulation time 66592526 ps
CPU time 1.28 seconds
Started Jun 25 05:41:16 PM PDT 24
Finished Jun 25 05:41:20 PM PDT 24
Peak memory 197156 kb
Host smart-f8091266-5ac5-4c4d-87b5-82ef3b8df53f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264726096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3264726096
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.300225620
Short name T321
Test name
Test status
Simulation time 57016517519 ps
CPU time 164.99 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:44:10 PM PDT 24
Peak memory 198752 kb
Host smart-7d5abee2-1954-4606-86d4-dd3498f82bb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300225620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.300225620
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1834791095
Short name T32
Test name
Test status
Simulation time 40078825 ps
CPU time 0.57 seconds
Started Jun 25 05:41:22 PM PDT 24
Finished Jun 25 05:41:23 PM PDT 24
Peak memory 193492 kb
Host smart-293dd82e-128d-4a31-83c5-a7b705577b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834791095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1834791095
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2918421077
Short name T438
Test name
Test status
Simulation time 16840094 ps
CPU time 0.63 seconds
Started Jun 25 05:41:30 PM PDT 24
Finished Jun 25 05:41:31 PM PDT 24
Peak memory 195300 kb
Host smart-3a83838a-b4c9-4f2e-a314-616bfd8a3589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918421077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2918421077
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2752843777
Short name T656
Test name
Test status
Simulation time 344359527 ps
CPU time 3.88 seconds
Started Jun 25 05:41:26 PM PDT 24
Finished Jun 25 05:41:31 PM PDT 24
Peak memory 197340 kb
Host smart-55ede9ca-c65c-4ccd-8827-28f92ec2e610
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752843777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2752843777
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.355512859
Short name T594
Test name
Test status
Simulation time 333249119 ps
CPU time 1.08 seconds
Started Jun 25 05:41:26 PM PDT 24
Finished Jun 25 05:41:28 PM PDT 24
Peak memory 197344 kb
Host smart-01022bc9-850b-45b2-8170-40b32276f055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355512859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.355512859
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2560108749
Short name T553
Test name
Test status
Simulation time 255657441 ps
CPU time 1.11 seconds
Started Jun 25 05:41:23 PM PDT 24
Finished Jun 25 05:41:25 PM PDT 24
Peak memory 196736 kb
Host smart-229533ec-345b-49ed-938c-11f6be382bbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560108749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2560108749
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1646822179
Short name T566
Test name
Test status
Simulation time 140381559 ps
CPU time 1.65 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:26 PM PDT 24
Peak memory 197516 kb
Host smart-cb5b334e-34e9-4cae-a3cc-6ccd79f06cd9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646822179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1646822179
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2880770888
Short name T679
Test name
Test status
Simulation time 539544506 ps
CPU time 3.27 seconds
Started Jun 25 05:41:26 PM PDT 24
Finished Jun 25 05:41:30 PM PDT 24
Peak memory 198660 kb
Host smart-5b50838e-9ea5-49f8-8067-62a06e863835
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880770888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2880770888
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3572740479
Short name T373
Test name
Test status
Simulation time 99025023 ps
CPU time 1.08 seconds
Started Jun 25 05:41:35 PM PDT 24
Finished Jun 25 05:41:37 PM PDT 24
Peak memory 196528 kb
Host smart-af56d8b5-4138-4d93-af58-dc03c8be7cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572740479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3572740479
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.530331767
Short name T526
Test name
Test status
Simulation time 60974839 ps
CPU time 1.3 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:45 PM PDT 24
Peak memory 197792 kb
Host smart-5becba54-cd38-48bf-953f-1c2019046823
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530331767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.530331767
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4121543145
Short name T365
Test name
Test status
Simulation time 102705285 ps
CPU time 4.73 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:30 PM PDT 24
Peak memory 198716 kb
Host smart-338e9030-ce8a-4362-acee-f154dd81f78b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121543145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4121543145
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.1301014800
Short name T276
Test name
Test status
Simulation time 175297574 ps
CPU time 0.97 seconds
Started Jun 25 05:41:25 PM PDT 24
Finished Jun 25 05:41:28 PM PDT 24
Peak memory 197120 kb
Host smart-9c4bfea8-6514-4613-bdc8-17891623a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301014800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1301014800
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3474852598
Short name T574
Test name
Test status
Simulation time 45639183 ps
CPU time 0.96 seconds
Started Jun 25 05:41:26 PM PDT 24
Finished Jun 25 05:41:29 PM PDT 24
Peak memory 196924 kb
Host smart-6a47f0c0-88b9-4a57-bc08-449e8b2376e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474852598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3474852598
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2280619944
Short name T659
Test name
Test status
Simulation time 35814600245 ps
CPU time 127.52 seconds
Started Jun 25 05:41:38 PM PDT 24
Finished Jun 25 05:43:46 PM PDT 24
Peak memory 198748 kb
Host smart-526f4862-af69-4809-b2c8-4e6406ce5907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280619944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2280619944
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1532993123
Short name T44
Test name
Test status
Simulation time 39434453 ps
CPU time 0.59 seconds
Started Jun 25 05:41:26 PM PDT 24
Finished Jun 25 05:41:28 PM PDT 24
Peak memory 195356 kb
Host smart-7fe2d495-f853-4427-83e6-976547c13fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532993123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1532993123
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.4129238203
Short name T705
Test name
Test status
Simulation time 240926803 ps
CPU time 0.84 seconds
Started Jun 25 05:41:25 PM PDT 24
Finished Jun 25 05:41:27 PM PDT 24
Peak memory 196764 kb
Host smart-40fe1393-1b98-4800-b9fe-3d3b52c62de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129238203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.4129238203
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.542021815
Short name T240
Test name
Test status
Simulation time 3470931290 ps
CPU time 25.73 seconds
Started Jun 25 05:41:23 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 197640 kb
Host smart-91640cad-d894-4bac-8bb8-6be807a0d50f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542021815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.542021815
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1678647885
Short name T609
Test name
Test status
Simulation time 30879813 ps
CPU time 0.73 seconds
Started Jun 25 05:41:25 PM PDT 24
Finished Jun 25 05:41:27 PM PDT 24
Peak memory 195316 kb
Host smart-40ab106c-df8b-497c-b8e9-3e1add42a0c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678647885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1678647885
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.247770323
Short name T517
Test name
Test status
Simulation time 441029196 ps
CPU time 0.97 seconds
Started Jun 25 05:41:30 PM PDT 24
Finished Jun 25 05:41:32 PM PDT 24
Peak memory 197384 kb
Host smart-b69a6be1-803a-4d26-aff4-7cca493f1eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247770323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.247770323
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.338123433
Short name T179
Test name
Test status
Simulation time 161526279 ps
CPU time 1.74 seconds
Started Jun 25 05:41:31 PM PDT 24
Finished Jun 25 05:41:34 PM PDT 24
Peak memory 198788 kb
Host smart-5e1bdf36-6a12-45e2-a577-b482945ab32b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338123433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.338123433
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.472654804
Short name T636
Test name
Test status
Simulation time 111936808 ps
CPU time 0.95 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:26 PM PDT 24
Peak memory 195156 kb
Host smart-b8eb6cf4-b7d4-4cb4-8312-8869c36f75eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472654804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
472654804
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3292297330
Short name T583
Test name
Test status
Simulation time 81318007 ps
CPU time 1.41 seconds
Started Jun 25 05:41:23 PM PDT 24
Finished Jun 25 05:41:25 PM PDT 24
Peak memory 196544 kb
Host smart-d0a848a3-188f-441d-b529-3cc6811b7345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292297330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3292297330
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.850084299
Short name T451
Test name
Test status
Simulation time 134045840 ps
CPU time 1.11 seconds
Started Jun 25 05:41:38 PM PDT 24
Finished Jun 25 05:41:40 PM PDT 24
Peak memory 197436 kb
Host smart-c98b4665-2744-4987-be13-9e281ff08952
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850084299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup
_pulldown.850084299
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2702776877
Short name T357
Test name
Test status
Simulation time 84666585 ps
CPU time 1.11 seconds
Started Jun 25 05:41:23 PM PDT 24
Finished Jun 25 05:41:25 PM PDT 24
Peak memory 198592 kb
Host smart-af150abb-bb69-4e2e-a26e-923ac16a7406
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702776877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2702776877
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2175482170
Short name T369
Test name
Test status
Simulation time 159948058 ps
CPU time 1.08 seconds
Started Jun 25 05:41:25 PM PDT 24
Finished Jun 25 05:41:27 PM PDT 24
Peak memory 196400 kb
Host smart-77321b8d-5112-4fa4-987a-939a9ba466d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175482170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2175482170
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.743094268
Short name T153
Test name
Test status
Simulation time 149461907 ps
CPU time 1.22 seconds
Started Jun 25 05:41:25 PM PDT 24
Finished Jun 25 05:41:28 PM PDT 24
Peak memory 196456 kb
Host smart-3b521f13-be56-4d3c-90a3-0c6a36bb7d2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743094268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.743094268
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.934176375
Short name T127
Test name
Test status
Simulation time 42573535928 ps
CPU time 102.57 seconds
Started Jun 25 05:41:23 PM PDT 24
Finished Jun 25 05:43:06 PM PDT 24
Peak memory 198772 kb
Host smart-fd1977bc-f659-4b0a-af2e-e11f309df665
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934176375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.934176375
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3399739532
Short name T228
Test name
Test status
Simulation time 19522870 ps
CPU time 0.59 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:19 PM PDT 24
Peak memory 194680 kb
Host smart-4c1ad240-dca1-4c22-8886-f4d18f2ae979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399739532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3399739532
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3028997228
Short name T626
Test name
Test status
Simulation time 38782966 ps
CPU time 0.82 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:19 PM PDT 24
Peak memory 196056 kb
Host smart-e9c22fa2-8c36-4ea5-b881-a21b1f414526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028997228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3028997228
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3390348309
Short name T343
Test name
Test status
Simulation time 10417821354 ps
CPU time 23.53 seconds
Started Jun 25 05:40:18 PM PDT 24
Finished Jun 25 05:40:43 PM PDT 24
Peak memory 198332 kb
Host smart-d9b5569d-07be-44f9-954a-b6ef82afe8ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390348309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3390348309
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1907562982
Short name T442
Test name
Test status
Simulation time 71959404 ps
CPU time 0.94 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:23 PM PDT 24
Peak memory 197904 kb
Host smart-4e95dd7a-c412-41ba-8a30-5144a1eac145
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907562982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1907562982
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1532077859
Short name T331
Test name
Test status
Simulation time 170872417 ps
CPU time 1.4 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 197540 kb
Host smart-d781ee74-bab2-49a1-9b92-62781f23d60f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532077859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1532077859
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3659171896
Short name T699
Test name
Test status
Simulation time 122921609 ps
CPU time 2.38 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 196984 kb
Host smart-c970e846-70a7-4497-b208-38a669455931
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659171896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3659171896
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.147560516
Short name T677
Test name
Test status
Simulation time 78573034 ps
CPU time 1.76 seconds
Started Jun 25 05:40:23 PM PDT 24
Finished Jun 25 05:40:26 PM PDT 24
Peak memory 196888 kb
Host smart-201eff3e-7443-4b87-82c7-6aa179a393d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147560516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.147560516
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1764752789
Short name T560
Test name
Test status
Simulation time 64508596 ps
CPU time 1.34 seconds
Started Jun 25 05:40:23 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 198616 kb
Host smart-cee9b743-aff4-4861-be03-21b119c8b055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764752789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1764752789
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3196070515
Short name T289
Test name
Test status
Simulation time 50451238 ps
CPU time 1.24 seconds
Started Jun 25 05:40:19 PM PDT 24
Finished Jun 25 05:40:22 PM PDT 24
Peak memory 197476 kb
Host smart-3b7fa034-e01d-43b3-b5d3-8703205afae9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196070515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3196070515
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2049199939
Short name T158
Test name
Test status
Simulation time 244213635 ps
CPU time 3.13 seconds
Started Jun 25 05:40:16 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 198684 kb
Host smart-40e17f97-d913-4636-b6f0-6fc6048ff58c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049199939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2049199939
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3410737561
Short name T43
Test name
Test status
Simulation time 771653897 ps
CPU time 0.9 seconds
Started Jun 25 05:40:18 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 215328 kb
Host smart-4ca2c7a9-6c70-42bb-a082-fe2ebb2b2c69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410737561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3410737561
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.921711707
Short name T539
Test name
Test status
Simulation time 75873035 ps
CPU time 1.23 seconds
Started Jun 25 05:40:08 PM PDT 24
Finished Jun 25 05:40:11 PM PDT 24
Peak memory 197452 kb
Host smart-8cb25c2a-1679-40fe-9216-595436f90a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921711707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.921711707
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2440584383
Short name T382
Test name
Test status
Simulation time 192590937 ps
CPU time 1.08 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:19 PM PDT 24
Peak memory 196228 kb
Host smart-9861db3f-09c3-4768-8657-b7b9fe52d259
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440584383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2440584383
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2788927907
Short name T644
Test name
Test status
Simulation time 24373933384 ps
CPU time 158.35 seconds
Started Jun 25 05:40:18 PM PDT 24
Finished Jun 25 05:42:58 PM PDT 24
Peak memory 198784 kb
Host smart-e3349a2f-5c5c-43c6-a430-b19b60b8a33c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788927907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2788927907
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3074236834
Short name T472
Test name
Test status
Simulation time 41106737 ps
CPU time 0.56 seconds
Started Jun 25 05:41:31 PM PDT 24
Finished Jun 25 05:41:33 PM PDT 24
Peak memory 194688 kb
Host smart-fea687e1-37cd-4b03-9714-cc45c41d6751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074236834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3074236834
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2725462737
Short name T178
Test name
Test status
Simulation time 141120854 ps
CPU time 0.95 seconds
Started Jun 25 05:41:40 PM PDT 24
Finished Jun 25 05:41:42 PM PDT 24
Peak memory 197112 kb
Host smart-e56c1253-8577-43c6-bd92-ef8c8008a50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725462737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2725462737
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1498326954
Short name T283
Test name
Test status
Simulation time 2510021640 ps
CPU time 22.18 seconds
Started Jun 25 05:41:27 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 197276 kb
Host smart-4ad7e1b3-36ea-49f5-a35a-014bd26726a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498326954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1498326954
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.549544466
Short name T11
Test name
Test status
Simulation time 74689730 ps
CPU time 1.13 seconds
Started Jun 25 05:41:35 PM PDT 24
Finished Jun 25 05:41:37 PM PDT 24
Peak memory 196964 kb
Host smart-471f0f2c-b874-4ead-b3d6-73c2b98373c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549544466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.549544466
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1005651197
Short name T498
Test name
Test status
Simulation time 65635813 ps
CPU time 1.25 seconds
Started Jun 25 05:41:25 PM PDT 24
Finished Jun 25 05:41:27 PM PDT 24
Peak memory 196856 kb
Host smart-e7f38d3d-6319-43d4-ae86-0a401c0913a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005651197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1005651197
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.4228885174
Short name T551
Test name
Test status
Simulation time 96223092 ps
CPU time 4 seconds
Started Jun 25 05:41:26 PM PDT 24
Finished Jun 25 05:41:32 PM PDT 24
Peak memory 198692 kb
Host smart-1a9992db-60a8-460e-80f6-8513c346d5ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228885174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.4228885174
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2578229828
Short name T300
Test name
Test status
Simulation time 168782551 ps
CPU time 1.98 seconds
Started Jun 25 05:41:26 PM PDT 24
Finished Jun 25 05:41:29 PM PDT 24
Peak memory 197188 kb
Host smart-e7d4a436-70fe-4e71-af8c-ff8856215560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578229828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2578229828
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1068377474
Short name T105
Test name
Test status
Simulation time 26596666 ps
CPU time 1.02 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:26 PM PDT 24
Peak memory 196564 kb
Host smart-9cc02a2a-83b4-4864-8349-aaa9dc026eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068377474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1068377474
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2007474663
Short name T682
Test name
Test status
Simulation time 137775455 ps
CPU time 0.83 seconds
Started Jun 25 05:41:22 PM PDT 24
Finished Jun 25 05:41:24 PM PDT 24
Peak memory 196176 kb
Host smart-751b89b3-b633-43e3-b35a-dcd75f7117f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007474663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2007474663
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1633536040
Short name T651
Test name
Test status
Simulation time 85658276 ps
CPU time 1.22 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 198672 kb
Host smart-7372bd1b-b478-48e6-9311-df44d58aaf5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633536040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1633536040
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2190885879
Short name T20
Test name
Test status
Simulation time 81364938 ps
CPU time 1.4 seconds
Started Jun 25 05:41:39 PM PDT 24
Finished Jun 25 05:41:41 PM PDT 24
Peak memory 196264 kb
Host smart-3f7180a9-9bfe-46df-8d20-985bf00bbaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190885879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2190885879
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3362408584
Short name T316
Test name
Test status
Simulation time 34769080 ps
CPU time 1.05 seconds
Started Jun 25 05:41:24 PM PDT 24
Finished Jun 25 05:41:27 PM PDT 24
Peak memory 197816 kb
Host smart-6a0af1ea-24b5-4334-a551-299cdb2c246f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362408584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3362408584
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.436821728
Short name T596
Test name
Test status
Simulation time 1630037630 ps
CPU time 21.79 seconds
Started Jun 25 05:41:40 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 198692 kb
Host smart-a15c6f7b-4579-4e46-a90d-fa7240d20d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436821728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.436821728
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.45267091
Short name T510
Test name
Test status
Simulation time 49240092474 ps
CPU time 1400.83 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 06:04:55 PM PDT 24
Peak memory 198952 kb
Host smart-aef8770c-6450-450f-9096-61dcb8450a17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=45267091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.45267091
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1611443693
Short name T41
Test name
Test status
Simulation time 16922107 ps
CPU time 0.58 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 195388 kb
Host smart-e752fdea-4ae0-45f9-aa4c-64b56edbc22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611443693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1611443693
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2843339040
Short name T462
Test name
Test status
Simulation time 40628387 ps
CPU time 0.89 seconds
Started Jun 25 05:41:31 PM PDT 24
Finished Jun 25 05:41:33 PM PDT 24
Peak memory 197236 kb
Host smart-5e6139dc-d641-45bb-a17d-a1398a589f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843339040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2843339040
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1712520742
Short name T233
Test name
Test status
Simulation time 600870200 ps
CPU time 17.72 seconds
Started Jun 25 05:41:36 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 198624 kb
Host smart-530bb9cc-59b2-4721-b3cb-3e373245c960
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712520742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1712520742
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1604831483
Short name T692
Test name
Test status
Simulation time 96399308 ps
CPU time 1.11 seconds
Started Jun 25 05:41:40 PM PDT 24
Finished Jun 25 05:41:42 PM PDT 24
Peak memory 198464 kb
Host smart-094a3e3e-61de-43cf-a7a1-fde4cf59ded1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604831483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1604831483
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.893097996
Short name T610
Test name
Test status
Simulation time 27550171 ps
CPU time 0.77 seconds
Started Jun 25 05:41:40 PM PDT 24
Finished Jun 25 05:41:41 PM PDT 24
Peak memory 196804 kb
Host smart-df467ec5-5fd4-426a-8591-264a7b09b49e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893097996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.893097996
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.4203527729
Short name T166
Test name
Test status
Simulation time 879922884 ps
CPU time 2.79 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:37 PM PDT 24
Peak memory 197036 kb
Host smart-813290cd-e40d-451c-aa7e-b5b95a8e7ef1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203527729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.4203527729
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2418475593
Short name T713
Test name
Test status
Simulation time 70189094 ps
CPU time 1.54 seconds
Started Jun 25 05:41:32 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 197472 kb
Host smart-2ec1481b-1acf-4f32-b795-5804007a3982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418475593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2418475593
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2993495561
Short name T306
Test name
Test status
Simulation time 54863153 ps
CPU time 1.06 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 196536 kb
Host smart-02bd9130-a3ad-4379-894b-4fa9ee5f77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993495561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2993495561
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.874083374
Short name T473
Test name
Test status
Simulation time 66274823 ps
CPU time 0.99 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 197464 kb
Host smart-5f5aca94-2b03-4f5b-8263-b91e2c71804c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874083374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.874083374
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.652531740
Short name T111
Test name
Test status
Simulation time 173001408 ps
CPU time 2.36 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 198900 kb
Host smart-e2372856-b2ab-44e2-808b-437ce4407dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652531740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.652531740
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2640259458
Short name T288
Test name
Test status
Simulation time 40970428 ps
CPU time 1.09 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 196232 kb
Host smart-65b654c4-6841-49e8-b913-f4bb55be636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640259458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2640259458
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.630871293
Short name T317
Test name
Test status
Simulation time 131883421 ps
CPU time 1.21 seconds
Started Jun 25 05:41:30 PM PDT 24
Finished Jun 25 05:41:32 PM PDT 24
Peak memory 197156 kb
Host smart-15464ced-c01e-4f0b-beee-7bd61941558e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630871293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.630871293
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1487571465
Short name T294
Test name
Test status
Simulation time 21495103629 ps
CPU time 147.52 seconds
Started Jun 25 05:41:34 PM PDT 24
Finished Jun 25 05:44:03 PM PDT 24
Peak memory 198820 kb
Host smart-39158118-9134-41e4-839e-ccef14eeb1c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487571465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1487571465
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.346959235
Short name T339
Test name
Test status
Simulation time 53445680 ps
CPU time 0.61 seconds
Started Jun 25 05:41:39 PM PDT 24
Finished Jun 25 05:41:40 PM PDT 24
Peak memory 194676 kb
Host smart-142fabc0-af26-4cd7-960e-7761d1072c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346959235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.346959235
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1811482097
Short name T130
Test name
Test status
Simulation time 51338580 ps
CPU time 0.8 seconds
Started Jun 25 05:41:32 PM PDT 24
Finished Jun 25 05:41:33 PM PDT 24
Peak memory 195880 kb
Host smart-7927da7e-241e-4f7a-bacf-f9171caeb3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811482097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1811482097
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1123356373
Short name T171
Test name
Test status
Simulation time 483803933 ps
CPU time 14.68 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 197680 kb
Host smart-418e0270-a0d7-4f4e-96db-6032fcabf58f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123356373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1123356373
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3285977444
Short name T335
Test name
Test status
Simulation time 80174485 ps
CPU time 1.06 seconds
Started Jun 25 05:41:35 PM PDT 24
Finished Jun 25 05:41:37 PM PDT 24
Peak memory 198716 kb
Host smart-a0e71bc1-16a3-448f-9bc6-8ab47bb78b5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285977444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3285977444
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2651932494
Short name T515
Test name
Test status
Simulation time 39945655 ps
CPU time 0.72 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 195772 kb
Host smart-df7a44e4-250a-440b-b275-945290cb739e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651932494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2651932494
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.655704788
Short name T491
Test name
Test status
Simulation time 83938820 ps
CPU time 3.29 seconds
Started Jun 25 05:41:31 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 198772 kb
Host smart-34907940-043a-4bf0-8890-398328f9cb8e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655704788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.655704788
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1058478982
Short name T389
Test name
Test status
Simulation time 136539883 ps
CPU time 2.07 seconds
Started Jun 25 05:41:41 PM PDT 24
Finished Jun 25 05:41:44 PM PDT 24
Peak memory 196532 kb
Host smart-99b58ac7-44f5-4a82-a189-5cb50bffe442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058478982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1058478982
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3928334462
Short name T149
Test name
Test status
Simulation time 24816022 ps
CPU time 0.98 seconds
Started Jun 25 05:41:34 PM PDT 24
Finished Jun 25 05:41:36 PM PDT 24
Peak memory 197400 kb
Host smart-f06657ae-db62-4f36-83e2-48649311e1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928334462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3928334462
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.4201375272
Short name T176
Test name
Test status
Simulation time 32107190 ps
CPU time 1.27 seconds
Started Jun 25 05:41:31 PM PDT 24
Finished Jun 25 05:41:33 PM PDT 24
Peak memory 198728 kb
Host smart-4f65239e-4766-4299-88bf-37216e744632
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201375272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.4201375272
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3261865131
Short name T487
Test name
Test status
Simulation time 845665326 ps
CPU time 3.11 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 198640 kb
Host smart-cd0164bf-ebb0-4194-8eae-703a837b0120
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261865131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3261865131
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.831170165
Short name T476
Test name
Test status
Simulation time 110650426 ps
CPU time 1.18 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 196284 kb
Host smart-6047571c-1757-4107-9b43-5c66d2d31f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831170165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.831170165
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2222903368
Short name T571
Test name
Test status
Simulation time 362598203 ps
CPU time 1.08 seconds
Started Jun 25 05:41:34 PM PDT 24
Finished Jun 25 05:41:36 PM PDT 24
Peak memory 197104 kb
Host smart-78d2280d-cccf-4a9e-9674-a3b68fc47ef1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222903368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2222903368
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3169342492
Short name T612
Test name
Test status
Simulation time 18576204340 ps
CPU time 130.37 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:44:01 PM PDT 24
Peak memory 198748 kb
Host smart-105ceb8b-231e-4536-990f-2058e971e78c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169342492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3169342492
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1891855537
Short name T439
Test name
Test status
Simulation time 14255794 ps
CPU time 0.64 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 194620 kb
Host smart-df080de1-2b6a-4887-b4e4-b8ec9ae35b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891855537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1891855537
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1012880798
Short name T607
Test name
Test status
Simulation time 100060697 ps
CPU time 0.74 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:41:48 PM PDT 24
Peak memory 195728 kb
Host smart-2b601ba2-c120-4f1b-b6e0-ee22d9fa052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012880798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1012880798
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1558108779
Short name T295
Test name
Test status
Simulation time 409562428 ps
CPU time 21.1 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 197696 kb
Host smart-ab86a741-2b49-49ed-8639-ae1eb5c7053f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558108779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1558108779
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.4062577398
Short name T652
Test name
Test status
Simulation time 78633442 ps
CPU time 1.09 seconds
Started Jun 25 05:41:35 PM PDT 24
Finished Jun 25 05:41:37 PM PDT 24
Peak memory 197080 kb
Host smart-52505e84-eea7-4da6-bcb7-1c3e1c22ae8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062577398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.4062577398
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1348694839
Short name T396
Test name
Test status
Simulation time 44534150 ps
CPU time 1.22 seconds
Started Jun 25 05:41:32 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 196496 kb
Host smart-11f31cf3-70ec-4d0c-bd27-48f3ffe5ff29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348694839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1348694839
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4145962073
Short name T424
Test name
Test status
Simulation time 39825876 ps
CPU time 1 seconds
Started Jun 25 05:41:32 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 196852 kb
Host smart-b42381f2-5d3c-4fb3-9733-a485a2965c8a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145962073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4145962073
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3090436240
Short name T454
Test name
Test status
Simulation time 73834050 ps
CPU time 2.46 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:36 PM PDT 24
Peak memory 198760 kb
Host smart-79d4dbe3-3e09-4eaf-bf93-56a54625e868
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090436240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3090436240
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3809815461
Short name T416
Test name
Test status
Simulation time 79611906 ps
CPU time 0.85 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 196728 kb
Host smart-f120529b-6b3b-4bb1-8ec1-268728a9e675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809815461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3809815461
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3071619294
Short name T686
Test name
Test status
Simulation time 244192544 ps
CPU time 1.05 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 196676 kb
Host smart-9890e949-15a2-4cc3-b6c4-a72bc070f5c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071619294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3071619294
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3900252879
Short name T318
Test name
Test status
Simulation time 126560721 ps
CPU time 6.21 seconds
Started Jun 25 05:41:32 PM PDT 24
Finished Jun 25 05:41:39 PM PDT 24
Peak memory 198688 kb
Host smart-25da5a85-a310-4e8d-bbe1-9f648ad6c3f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900252879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3900252879
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.86153624
Short name T190
Test name
Test status
Simulation time 62009099 ps
CPU time 1.23 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 197172 kb
Host smart-a56b9bce-2d76-410c-8d09-a7f09080b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86153624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.86153624
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.674510619
Short name T61
Test name
Test status
Simulation time 34171088 ps
CPU time 0.94 seconds
Started Jun 25 05:41:37 PM PDT 24
Finished Jun 25 05:41:38 PM PDT 24
Peak memory 196936 kb
Host smart-53d1f676-605f-4bde-befd-e253cc2d7708
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674510619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.674510619
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3200729750
Short name T519
Test name
Test status
Simulation time 7542116832 ps
CPU time 192.88 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:45:00 PM PDT 24
Peak memory 198760 kb
Host smart-463a3782-b92e-4644-b9a0-9e9e1b5647d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200729750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3200729750
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.283829266
Short name T249
Test name
Test status
Simulation time 23622723 ps
CPU time 0.64 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:34 PM PDT 24
Peak memory 194864 kb
Host smart-ba371b1c-fb20-491e-a858-ba3bed6d10d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283829266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.283829266
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1398564216
Short name T514
Test name
Test status
Simulation time 25908249 ps
CPU time 0.83 seconds
Started Jun 25 05:41:40 PM PDT 24
Finished Jun 25 05:41:42 PM PDT 24
Peak memory 196724 kb
Host smart-494a7819-f396-4a5a-b3dc-08420a1ab4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398564216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1398564216
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2972101408
Short name T613
Test name
Test status
Simulation time 2774091041 ps
CPU time 23.04 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:42:07 PM PDT 24
Peak memory 197684 kb
Host smart-4d9f679c-60c1-45b8-8cf9-f9857f1dcac1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972101408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2972101408
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2710130752
Short name T185
Test name
Test status
Simulation time 445243945 ps
CPU time 0.82 seconds
Started Jun 25 05:41:34 PM PDT 24
Finished Jun 25 05:41:36 PM PDT 24
Peak memory 197256 kb
Host smart-d5faa37e-1825-4826-84d9-edc4e65f2625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710130752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2710130752
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1071144477
Short name T206
Test name
Test status
Simulation time 35684877 ps
CPU time 1.12 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:35 PM PDT 24
Peak memory 196816 kb
Host smart-33b4709a-2ac1-42fe-8871-8a83115b15e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071144477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1071144477
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1044897942
Short name T404
Test name
Test status
Simulation time 292336642 ps
CPU time 2.98 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 198796 kb
Host smart-c53f9c08-7b81-4584-b5b8-3ecd92e8f54f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044897942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1044897942
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3733023060
Short name T559
Test name
Test status
Simulation time 459542713 ps
CPU time 1.62 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 196544 kb
Host smart-ba62a22e-033b-43cd-97ee-958d23eb724c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733023060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3733023060
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.812211760
Short name T356
Test name
Test status
Simulation time 41758104 ps
CPU time 1.01 seconds
Started Jun 25 05:41:41 PM PDT 24
Finished Jun 25 05:41:43 PM PDT 24
Peak memory 197196 kb
Host smart-59e5398c-ebe9-4bc6-9dca-c23c3b907fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812211760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.812211760
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3881028491
Short name T242
Test name
Test status
Simulation time 21795638 ps
CPU time 0.87 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 197284 kb
Host smart-90f506d2-c573-488b-a634-83cb6500602a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881028491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3881028491
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1229350294
Short name T5
Test name
Test status
Simulation time 1101413733 ps
CPU time 3.45 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:52 PM PDT 24
Peak memory 198652 kb
Host smart-c0c3f000-b819-4d0f-ac7c-b7ef807bcf94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229350294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1229350294
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1387255978
Short name T114
Test name
Test status
Simulation time 484217819 ps
CPU time 1.15 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:45 PM PDT 24
Peak memory 196468 kb
Host smart-1a43d401-9bcb-45cf-a319-09a2109457ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387255978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1387255978
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1352873545
Short name T401
Test name
Test status
Simulation time 51349657 ps
CPU time 1.47 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:41:36 PM PDT 24
Peak memory 196952 kb
Host smart-5e85f87a-8c57-4919-8aa6-9632abc4e769
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352873545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1352873545
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1743316097
Short name T350
Test name
Test status
Simulation time 58665612225 ps
CPU time 201.85 seconds
Started Jun 25 05:41:32 PM PDT 24
Finished Jun 25 05:44:55 PM PDT 24
Peak memory 198856 kb
Host smart-2a78750e-51dd-441d-9083-05f84e034c3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743316097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1743316097
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1310738636
Short name T31
Test name
Test status
Simulation time 12951020 ps
CPU time 0.59 seconds
Started Jun 25 05:41:42 PM PDT 24
Finished Jun 25 05:41:43 PM PDT 24
Peak memory 194704 kb
Host smart-4b3331f4-4661-4024-ab7f-8a497ddf0492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310738636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1310738636
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3113723495
Short name T168
Test name
Test status
Simulation time 93420005 ps
CPU time 0.72 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 194820 kb
Host smart-f1ede9a3-8933-4d85-a445-25f6d58d9b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113723495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3113723495
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2170627809
Short name T680
Test name
Test status
Simulation time 801218084 ps
CPU time 26.04 seconds
Started Jun 25 05:41:33 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 196956 kb
Host smart-012b6beb-c420-4a1e-a78c-9ed9d7f20ea2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170627809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2170627809
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.4050784993
Short name T672
Test name
Test status
Simulation time 26632616 ps
CPU time 0.61 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 194804 kb
Host smart-244957e3-8559-4c76-bbab-182613bbce55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050784993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.4050784993
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.891957560
Short name T395
Test name
Test status
Simulation time 57270421 ps
CPU time 1.04 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 197428 kb
Host smart-f2b8c1ae-62ba-4601-9cd6-2de19a800780
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891957560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.891957560
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2614200575
Short name T412
Test name
Test status
Simulation time 83457551 ps
CPU time 3.34 seconds
Started Jun 25 05:41:36 PM PDT 24
Finished Jun 25 05:41:40 PM PDT 24
Peak memory 196996 kb
Host smart-d3012a05-dc54-4bca-9dc8-2860b27fdb1c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614200575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2614200575
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3692982593
Short name T400
Test name
Test status
Simulation time 399840586 ps
CPU time 2.32 seconds
Started Jun 25 05:41:36 PM PDT 24
Finished Jun 25 05:41:39 PM PDT 24
Peak memory 196572 kb
Host smart-2f9a785c-4e76-4e5b-8e33-134a47184766
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692982593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3692982593
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3418591134
Short name T550
Test name
Test status
Simulation time 431995884 ps
CPU time 1.33 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 198964 kb
Host smart-4d73f1cb-95a7-4cb9-b0d0-4f2d85408567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418591134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3418591134
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3725008815
Short name T230
Test name
Test status
Simulation time 212829742 ps
CPU time 1.21 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 197824 kb
Host smart-85db1c18-223b-4cff-b230-d66237c2aa42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725008815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3725008815
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2015910142
Short name T546
Test name
Test status
Simulation time 93888387 ps
CPU time 4.42 seconds
Started Jun 25 05:41:37 PM PDT 24
Finished Jun 25 05:41:42 PM PDT 24
Peak memory 198688 kb
Host smart-0685feb0-6eba-402f-8c2a-7e3d21d03866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015910142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2015910142
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.4116001076
Short name T260
Test name
Test status
Simulation time 231820665 ps
CPU time 1.23 seconds
Started Jun 25 05:41:49 PM PDT 24
Finished Jun 25 05:41:53 PM PDT 24
Peak memory 196232 kb
Host smart-292fa152-2616-44ac-86fb-8f330bc85862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116001076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.4116001076
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3408098219
Short name T427
Test name
Test status
Simulation time 930865754 ps
CPU time 1.39 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:41:48 PM PDT 24
Peak memory 197352 kb
Host smart-38cb6596-14a8-45cb-99a4-67c6648f13fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408098219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3408098219
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1767457368
Short name T676
Test name
Test status
Simulation time 18508785034 ps
CPU time 49.34 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:42:41 PM PDT 24
Peak memory 198820 kb
Host smart-5a7eedb2-ecaf-4ad4-9a86-78551d6c5d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767457368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1767457368
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1137407123
Short name T346
Test name
Test status
Simulation time 45838982 ps
CPU time 0.6 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 194852 kb
Host smart-5f281e19-3d34-463f-b544-49cc47d052c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137407123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1137407123
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4013271986
Short name T48
Test name
Test status
Simulation time 32589615 ps
CPU time 0.78 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 196484 kb
Host smart-a6e2fdc5-c756-4777-94ed-4c2704cc3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013271986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4013271986
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3747624329
Short name T696
Test name
Test status
Simulation time 515499189 ps
CPU time 9.4 seconds
Started Jun 25 05:41:42 PM PDT 24
Finished Jun 25 05:41:52 PM PDT 24
Peak memory 196220 kb
Host smart-a33f7701-a2ea-4263-a5da-e1cad3b0d2ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747624329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3747624329
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1395957418
Short name T213
Test name
Test status
Simulation time 88897072 ps
CPU time 0.77 seconds
Started Jun 25 05:41:50 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 196572 kb
Host smart-71611cbb-3518-4f96-8755-716c9c7473df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395957418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1395957418
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2246343304
Short name T307
Test name
Test status
Simulation time 93767593 ps
CPU time 1.49 seconds
Started Jun 25 05:41:41 PM PDT 24
Finished Jun 25 05:41:43 PM PDT 24
Peak memory 198752 kb
Host smart-f98da48c-63a4-4fa1-9ca5-bdca28c8b4cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246343304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2246343304
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.935308921
Short name T160
Test name
Test status
Simulation time 101195972 ps
CPU time 3.76 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 198760 kb
Host smart-ceb91b7c-d965-4cf9-b21a-9b8167524ede
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935308921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.935308921
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3930447727
Short name T606
Test name
Test status
Simulation time 65319537 ps
CPU time 1.71 seconds
Started Jun 25 05:41:49 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 196548 kb
Host smart-2667d51e-47ec-496e-b9ec-06e91d8b7330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930447727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3930447727
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3546836302
Short name T248
Test name
Test status
Simulation time 67800748 ps
CPU time 1.45 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 197716 kb
Host smart-bf459d2d-8f97-4de1-a885-af8813c8ee98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546836302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3546836302
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1519614808
Short name T709
Test name
Test status
Simulation time 70102259 ps
CPU time 1.18 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 196704 kb
Host smart-9f3cfe11-37c1-4d66-ac37-4bcad49a31a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519614808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1519614808
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4149424840
Short name T45
Test name
Test status
Simulation time 369834057 ps
CPU time 1.95 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 198668 kb
Host smart-403dba1c-ce7b-4ec9-a48b-e500b3023879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149424840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4149424840
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2471294739
Short name T277
Test name
Test status
Simulation time 251098201 ps
CPU time 1.38 seconds
Started Jun 25 05:41:50 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 197532 kb
Host smart-fd76a4dd-7bfe-4f50-815c-fe1815d43904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471294739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2471294739
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2018798085
Short name T436
Test name
Test status
Simulation time 178570307 ps
CPU time 0.93 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 196036 kb
Host smart-04139395-0e14-40e1-bd3e-5cb5054cbaca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018798085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2018798085
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1459900499
Short name T509
Test name
Test status
Simulation time 22440827844 ps
CPU time 64.31 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:42:53 PM PDT 24
Peak memory 198916 kb
Host smart-e9d5323f-5a49-416c-b6c0-3b41a3f2fdaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459900499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1459900499
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3294126942
Short name T457
Test name
Test status
Simulation time 13234403 ps
CPU time 0.59 seconds
Started Jun 25 05:41:52 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 195380 kb
Host smart-2fe866ef-356d-434e-82d6-94c4fcc9160d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294126942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3294126942
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1635168991
Short name T46
Test name
Test status
Simulation time 25654438 ps
CPU time 0.69 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 194784 kb
Host smart-41a4768b-6c95-448f-abe0-2402636de232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635168991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1635168991
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1083747673
Short name T489
Test name
Test status
Simulation time 734322868 ps
CPU time 6.6 seconds
Started Jun 25 05:41:42 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 197568 kb
Host smart-91b2a8c5-0c0f-4e75-b9bf-52b05371c909
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083747673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1083747673
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.983540855
Short name T695
Test name
Test status
Simulation time 387275313 ps
CPU time 0.94 seconds
Started Jun 25 05:41:42 PM PDT 24
Finished Jun 25 05:41:44 PM PDT 24
Peak memory 197308 kb
Host smart-9cdd5d55-1790-4c5a-b9d6-11a6a1dce5fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983540855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.983540855
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3607554564
Short name T138
Test name
Test status
Simulation time 87560020 ps
CPU time 0.83 seconds
Started Jun 25 05:41:49 PM PDT 24
Finished Jun 25 05:41:53 PM PDT 24
Peak memory 196212 kb
Host smart-c78018f4-0600-420b-afac-136a76ad978e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607554564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3607554564
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3172094369
Short name T278
Test name
Test status
Simulation time 46841306 ps
CPU time 2.16 seconds
Started Jun 25 05:41:53 PM PDT 24
Finished Jun 25 05:41:57 PM PDT 24
Peak memory 198736 kb
Host smart-fec084c1-5b56-4dc6-b831-2b058c8c31f8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172094369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3172094369
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3939107559
Short name T587
Test name
Test status
Simulation time 578843442 ps
CPU time 3.47 seconds
Started Jun 25 05:41:53 PM PDT 24
Finished Jun 25 05:41:58 PM PDT 24
Peak memory 198732 kb
Host smart-9d2a2c0e-3c40-4c97-bab1-433660f74c10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939107559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3939107559
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.522882778
Short name T250
Test name
Test status
Simulation time 126330896 ps
CPU time 1.25 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 197716 kb
Host smart-d5c97267-dae9-4bc5-a411-477c03cb8c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522882778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.522882778
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1508578928
Short name T370
Test name
Test status
Simulation time 54892208 ps
CPU time 1.22 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 196556 kb
Host smart-d727cd33-1c12-4dc2-ac04-3a10681c5428
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508578928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1508578928
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1343633448
Short name T386
Test name
Test status
Simulation time 95435120 ps
CPU time 2.22 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 198584 kb
Host smart-7dd92b63-8bce-4de8-93fa-fdaaf16e1d30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343633448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1343633448
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1663872674
Short name T106
Test name
Test status
Simulation time 108409203 ps
CPU time 1.38 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 198628 kb
Host smart-6c5e5052-1cb1-4e6d-a820-84f784c7c715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663872674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1663872674
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.4139586241
Short name T421
Test name
Test status
Simulation time 115818084 ps
CPU time 1.17 seconds
Started Jun 25 05:41:41 PM PDT 24
Finished Jun 25 05:41:43 PM PDT 24
Peak memory 196024 kb
Host smart-ca4f35de-7a98-4542-b971-58191e5a1bda
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139586241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.4139586241
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2676844903
Short name T313
Test name
Test status
Simulation time 5681997328 ps
CPU time 74.93 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:43:03 PM PDT 24
Peak memory 198736 kb
Host smart-3a4dcabe-4bb3-4c34-bc8a-3639b1840ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676844903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2676844903
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.572834646
Short name T222
Test name
Test status
Simulation time 45431283 ps
CPU time 0.62 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 194864 kb
Host smart-833af479-1d78-45f0-88d8-54b313348513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572834646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.572834646
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2093914434
Short name T115
Test name
Test status
Simulation time 29154427 ps
CPU time 0.91 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 196692 kb
Host smart-9c923259-4d4c-40db-b4cc-dd90099ed0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093914434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2093914434
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3614162264
Short name T714
Test name
Test status
Simulation time 9496928324 ps
CPU time 17.38 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 197164 kb
Host smart-809da6dd-b1ed-4cf3-b274-b737eb2d79d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614162264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3614162264
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.403410753
Short name T229
Test name
Test status
Simulation time 143638954 ps
CPU time 0.78 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 196524 kb
Host smart-6cc9f018-8fc6-4c17-885e-29a66adb68dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403410753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.403410753
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3231533463
Short name T371
Test name
Test status
Simulation time 101889875 ps
CPU time 1.5 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:41:48 PM PDT 24
Peak memory 198724 kb
Host smart-6aed754f-9570-45ef-9947-6025ed73b679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231533463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3231533463
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.302468585
Short name T383
Test name
Test status
Simulation time 386894383 ps
CPU time 3.17 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:52 PM PDT 24
Peak memory 198752 kb
Host smart-e3a18804-e2ad-4253-9dec-ef1e0e903215
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302468585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.302468585
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3429698582
Short name T503
Test name
Test status
Simulation time 482897027 ps
CPU time 2.21 seconds
Started Jun 25 05:41:52 PM PDT 24
Finished Jun 25 05:41:56 PM PDT 24
Peak memory 197240 kb
Host smart-763822ca-e512-474a-a4c9-ac6d219f32e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429698582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3429698582
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.534590816
Short name T544
Test name
Test status
Simulation time 59614047 ps
CPU time 1.18 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 198788 kb
Host smart-ae83a2dd-24f3-4423-b464-d7a721c32153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534590816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.534590816
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2486091377
Short name T52
Test name
Test status
Simulation time 317362041 ps
CPU time 1.16 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 196756 kb
Host smart-d6d04399-f405-4507-98b0-1031faafde19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486091377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2486091377
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1039150519
Short name T555
Test name
Test status
Simulation time 690931332 ps
CPU time 6.47 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 197044 kb
Host smart-f7ae0728-f999-463b-bb81-05e87db79e3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039150519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1039150519
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1683789321
Short name T273
Test name
Test status
Simulation time 66069092 ps
CPU time 1.13 seconds
Started Jun 25 05:41:54 PM PDT 24
Finished Jun 25 05:41:57 PM PDT 24
Peak memory 196712 kb
Host smart-f34fee01-808e-4795-a1c7-0811a59149ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683789321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1683789321
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1620489262
Short name T657
Test name
Test status
Simulation time 164528306 ps
CPU time 1.04 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 196228 kb
Host smart-b3f5ba54-0cd6-4865-b1a6-20d16234c520
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620489262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1620489262
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.317991494
Short name T479
Test name
Test status
Simulation time 4347589238 ps
CPU time 28.18 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:42:16 PM PDT 24
Peak memory 198820 kb
Host smart-b0c0cd39-a8a3-42c1-b8cc-95447d32c24a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317991494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.317991494
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3584970099
Short name T495
Test name
Test status
Simulation time 15076386 ps
CPU time 0.59 seconds
Started Jun 25 05:41:56 PM PDT 24
Finished Jun 25 05:41:58 PM PDT 24
Peak memory 195496 kb
Host smart-1315246a-b06a-441e-a835-1efb1d87d88e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584970099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3584970099
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.491591929
Short name T337
Test name
Test status
Simulation time 30511024 ps
CPU time 0.74 seconds
Started Jun 25 05:41:51 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 195924 kb
Host smart-5335f6ff-9f41-4699-bd1d-a1c7a220be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491591929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.491591929
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1016748185
Short name T150
Test name
Test status
Simulation time 2773793575 ps
CPU time 11.53 seconds
Started Jun 25 05:41:51 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 197312 kb
Host smart-ef0da2a5-7d74-4b63-9e48-3074ffc37c95
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016748185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1016748185
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1874808175
Short name T358
Test name
Test status
Simulation time 142385737 ps
CPU time 1.21 seconds
Started Jun 25 05:41:54 PM PDT 24
Finished Jun 25 05:41:57 PM PDT 24
Peak memory 198856 kb
Host smart-a51effe4-067c-4172-8c3a-3804096120aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874808175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1874808175
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.867181496
Short name T191
Test name
Test status
Simulation time 109678580 ps
CPU time 1 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:49 PM PDT 24
Peak memory 196744 kb
Host smart-5ab4376f-3894-4aaf-8ad1-886db39b05d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867181496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.867181496
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1610662271
Short name T429
Test name
Test status
Simulation time 95224282 ps
CPU time 3.91 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 198756 kb
Host smart-31ab7e09-db96-49f7-8aad-130437850d83
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610662271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1610662271
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1936122733
Short name T263
Test name
Test status
Simulation time 354829858 ps
CPU time 2.76 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:52 PM PDT 24
Peak memory 198768 kb
Host smart-9ed1c63d-1100-4c55-af07-f10742f05963
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936122733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1936122733
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3790741337
Short name T534
Test name
Test status
Simulation time 17721561 ps
CPU time 0.79 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:47 PM PDT 24
Peak memory 196160 kb
Host smart-f14fb2c0-e037-4d1d-8386-6a3ff93307ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790741337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3790741337
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.114018415
Short name T617
Test name
Test status
Simulation time 177106416 ps
CPU time 1.39 seconds
Started Jun 25 05:41:46 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 197600 kb
Host smart-7d2c3396-4bb3-4367-a0da-bad7d82e0c99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114018415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.114018415
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.172510547
Short name T231
Test name
Test status
Simulation time 664422207 ps
CPU time 2.93 seconds
Started Jun 25 05:41:44 PM PDT 24
Finished Jun 25 05:41:48 PM PDT 24
Peak memory 198716 kb
Host smart-c19d3dda-f34c-43d4-8db8-4d53af121c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172510547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.172510547
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.4274253779
Short name T531
Test name
Test status
Simulation time 1291333625 ps
CPU time 1.28 seconds
Started Jun 25 05:41:45 PM PDT 24
Finished Jun 25 05:41:48 PM PDT 24
Peak memory 196252 kb
Host smart-8e8b1043-a992-4e4b-abb5-f1aa2123ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274253779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.4274253779
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1860042204
Short name T402
Test name
Test status
Simulation time 100810227 ps
CPU time 1.34 seconds
Started Jun 25 05:41:43 PM PDT 24
Finished Jun 25 05:41:46 PM PDT 24
Peak memory 197168 kb
Host smart-653def65-787f-4352-97c6-0227dfab4bcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860042204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1860042204
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.720299467
Short name T643
Test name
Test status
Simulation time 71274409029 ps
CPU time 171.63 seconds
Started Jun 25 05:41:52 PM PDT 24
Finished Jun 25 05:44:45 PM PDT 24
Peak memory 198792 kb
Host smart-f1666d83-73b8-4b7e-9d10-1a62e1f69c46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720299467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.720299467
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3322236744
Short name T637
Test name
Test status
Simulation time 37466700 ps
CPU time 0.61 seconds
Started Jun 25 05:40:23 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 194724 kb
Host smart-9e2bb18b-9ee3-4153-8ab5-cdc4cdf08ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322236744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3322236744
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2522625440
Short name T328
Test name
Test status
Simulation time 111318012 ps
CPU time 0.87 seconds
Started Jun 25 05:40:22 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 196644 kb
Host smart-91bfc624-0a1c-4ba2-adf7-834159716f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522625440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2522625440
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1913846156
Short name T147
Test name
Test status
Simulation time 2997210459 ps
CPU time 27.47 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:46 PM PDT 24
Peak memory 198756 kb
Host smart-bb1a29d7-6f2f-4afb-8004-3aff2623b060
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913846156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1913846156
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3904443860
Short name T246
Test name
Test status
Simulation time 710558887 ps
CPU time 0.83 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:40:17 PM PDT 24
Peak memory 196692 kb
Host smart-3caedb7b-b68c-44e8-944f-bd5121f44f87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904443860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3904443860
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.569758057
Short name T136
Test name
Test status
Simulation time 257398061 ps
CPU time 1.11 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:23 PM PDT 24
Peak memory 196476 kb
Host smart-fc6cc708-312d-4da2-82a2-0c0a839d76f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569758057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.569758057
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2180804145
Short name T104
Test name
Test status
Simulation time 92122165 ps
CPU time 1.88 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:21 PM PDT 24
Peak memory 198692 kb
Host smart-89ab988b-5485-43ef-9530-f0c58a7784f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180804145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2180804145
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3941298337
Short name T435
Test name
Test status
Simulation time 44141109 ps
CPU time 1.4 seconds
Started Jun 25 05:40:19 PM PDT 24
Finished Jun 25 05:40:22 PM PDT 24
Peak memory 196856 kb
Host smart-35217d44-f375-4d23-bca5-dc8e8e5e0cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941298337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3941298337
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3857720943
Short name T374
Test name
Test status
Simulation time 89403080 ps
CPU time 1.07 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 196512 kb
Host smart-a0d11e2e-a865-40b0-9ebe-ab6576c5703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857720943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3857720943
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3497633872
Short name T379
Test name
Test status
Simulation time 75023473 ps
CPU time 1.21 seconds
Started Jun 25 05:40:23 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 197308 kb
Host smart-ccda2551-7e0b-4fdc-9f13-2a1149afeb1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497633872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3497633872
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2010413512
Short name T361
Test name
Test status
Simulation time 899216047 ps
CPU time 5.24 seconds
Started Jun 25 05:40:22 PM PDT 24
Finished Jun 25 05:40:29 PM PDT 24
Peak memory 198604 kb
Host smart-4e148609-7598-49c8-8f98-241e3accce89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010413512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2010413512
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.4213306494
Short name T604
Test name
Test status
Simulation time 113503047 ps
CPU time 0.78 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 195956 kb
Host smart-03b178cb-eb60-49a8-bf85-558d544e78dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213306494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.4213306494
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.2311434250
Short name T251
Test name
Test status
Simulation time 357429927 ps
CPU time 1.36 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 197520 kb
Host smart-df845947-248d-4f4a-8c02-45972ed6c6cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311434250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.2311434250
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3672286270
Short name T90
Test name
Test status
Simulation time 39428746090 ps
CPU time 108.18 seconds
Started Jun 25 05:40:15 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 198804 kb
Host smart-cc944fbd-982b-4090-a580-2cc162f69c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672286270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3672286270
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3195030450
Short name T89
Test name
Test status
Simulation time 195672921364 ps
CPU time 1523.2 seconds
Started Jun 25 05:40:23 PM PDT 24
Finished Jun 25 06:05:47 PM PDT 24
Peak memory 198956 kb
Host smart-3d33678c-6726-44af-a7df-7fd38968d041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3195030450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3195030450
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2329928059
Short name T461
Test name
Test status
Simulation time 16137633 ps
CPU time 0.6 seconds
Started Jun 25 05:40:16 PM PDT 24
Finished Jun 25 05:40:18 PM PDT 24
Peak memory 195368 kb
Host smart-9db67219-121f-499b-aff0-e196bc24fc2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329928059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2329928059
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1346643865
Short name T670
Test name
Test status
Simulation time 99269076 ps
CPU time 0.96 seconds
Started Jun 25 05:40:18 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 197240 kb
Host smart-a7bcd9fc-ccc0-4845-8424-c2c18c01464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346643865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1346643865
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.153355966
Short name T117
Test name
Test status
Simulation time 4685109149 ps
CPU time 23.28 seconds
Started Jun 25 05:40:20 PM PDT 24
Finished Jun 25 05:40:45 PM PDT 24
Peak memory 197324 kb
Host smart-63edabe0-77b5-4825-a227-90e023f136b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153355966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.153355966
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.326117992
Short name T170
Test name
Test status
Simulation time 206605183 ps
CPU time 0.88 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:19 PM PDT 24
Peak memory 196740 kb
Host smart-f37ee326-3747-42bc-9e74-c529a605b69c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326117992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.326117992
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2150373913
Short name T271
Test name
Test status
Simulation time 36218363 ps
CPU time 1.09 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:19 PM PDT 24
Peak memory 196796 kb
Host smart-f58bce07-28ae-49b0-8c95-3194352031bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150373913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2150373913
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3298532370
Short name T103
Test name
Test status
Simulation time 298452642 ps
CPU time 2.59 seconds
Started Jun 25 05:40:23 PM PDT 24
Finished Jun 25 05:40:27 PM PDT 24
Peak memory 198708 kb
Host smart-ac03ba3b-5d24-4859-ba0e-e3da27c443a1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298532370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3298532370
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1859976361
Short name T463
Test name
Test status
Simulation time 200318002 ps
CPU time 3.08 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:22 PM PDT 24
Peak memory 197856 kb
Host smart-2882c209-5069-4fac-ba07-1d80e3c879e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859976361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1859976361
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2958174283
Short name T152
Test name
Test status
Simulation time 21716475 ps
CPU time 0.89 seconds
Started Jun 25 05:40:19 PM PDT 24
Finished Jun 25 05:40:21 PM PDT 24
Peak memory 197156 kb
Host smart-38f114ce-2813-4655-8b57-e30c9aa3eb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958174283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2958174283
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.339544578
Short name T367
Test name
Test status
Simulation time 444477113 ps
CPU time 0.79 seconds
Started Jun 25 05:40:22 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 196164 kb
Host smart-22b87d6b-e8aa-4f04-a6ac-ad9ee43473eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339544578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.339544578
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1973286593
Short name T50
Test name
Test status
Simulation time 352808881 ps
CPU time 5.43 seconds
Started Jun 25 05:40:20 PM PDT 24
Finished Jun 25 05:40:27 PM PDT 24
Peak memory 198612 kb
Host smart-554a2696-2e8c-4bac-92bb-30ce479f2f92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973286593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1973286593
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.716568724
Short name T552
Test name
Test status
Simulation time 80708984 ps
CPU time 0.88 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:24 PM PDT 24
Peak memory 197640 kb
Host smart-1d9694e5-eca0-4105-b4cf-128575330919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716568724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.716568724
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.951570410
Short name T485
Test name
Test status
Simulation time 217412824 ps
CPU time 1.14 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:19 PM PDT 24
Peak memory 197032 kb
Host smart-2541de86-c087-454b-af68-ce457727d01e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951570410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.951570410
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1876508394
Short name T1
Test name
Test status
Simulation time 24694921248 ps
CPU time 159.99 seconds
Started Jun 25 05:40:16 PM PDT 24
Finished Jun 25 05:42:57 PM PDT 24
Peak memory 198824 kb
Host smart-bd7e3d29-f6e9-44ff-bb5c-7627a85aaccf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876508394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1876508394
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.19678837
Short name T660
Test name
Test status
Simulation time 109090395276 ps
CPU time 693.91 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:51:56 PM PDT 24
Peak memory 198940 kb
Host smart-9bc2e5d9-35c3-417e-b44f-75aae3569ed8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=19678837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.19678837
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3364526283
Short name T310
Test name
Test status
Simulation time 11304483 ps
CPU time 0.6 seconds
Started Jun 25 05:40:40 PM PDT 24
Finished Jun 25 05:40:41 PM PDT 24
Peak memory 195364 kb
Host smart-1d072417-9943-4da7-ae29-5f70d9fafc08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364526283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3364526283
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2765184083
Short name T332
Test name
Test status
Simulation time 25764187 ps
CPU time 0.71 seconds
Started Jun 25 05:40:24 PM PDT 24
Finished Jun 25 05:40:26 PM PDT 24
Peak memory 195532 kb
Host smart-3249b13d-63dc-467d-93cf-592bad163161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765184083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2765184083
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1475180111
Short name T302
Test name
Test status
Simulation time 2053021706 ps
CPU time 16.17 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:40:43 PM PDT 24
Peak memory 198684 kb
Host smart-d178939a-f927-4cc6-b0a0-dfa580c5d217
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475180111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1475180111
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.371878199
Short name T293
Test name
Test status
Simulation time 147663109 ps
CPU time 0.82 seconds
Started Jun 25 05:40:32 PM PDT 24
Finished Jun 25 05:40:34 PM PDT 24
Peak memory 196588 kb
Host smart-65767d5c-dd32-489e-b29f-dfb94e69b332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371878199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.371878199
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.268402977
Short name T303
Test name
Test status
Simulation time 83676445 ps
CPU time 1.44 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:29 PM PDT 24
Peak memory 197504 kb
Host smart-66cccc74-5d82-4b2b-a403-a362a5e8066c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268402977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.268402977
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1698004080
Short name T226
Test name
Test status
Simulation time 71842989 ps
CPU time 2.38 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 198736 kb
Host smart-544ec62b-d8d0-49f7-9ce0-3145d2e97ed9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698004080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1698004080
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.441326026
Short name T478
Test name
Test status
Simulation time 60334317 ps
CPU time 1.52 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:29 PM PDT 24
Peak memory 197172 kb
Host smart-6c42c785-0801-4ffb-8485-ee267520a730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441326026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.441326026
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.986266058
Short name T558
Test name
Test status
Simulation time 46672112 ps
CPU time 0.72 seconds
Started Jun 25 05:40:18 PM PDT 24
Finished Jun 25 05:40:20 PM PDT 24
Peak memory 194948 kb
Host smart-030338eb-48fd-4d68-9c9e-edbc8da86746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986266058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.986266058
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4249619876
Short name T364
Test name
Test status
Simulation time 113313090 ps
CPU time 1.24 seconds
Started Jun 25 05:40:21 PM PDT 24
Finished Jun 25 05:40:23 PM PDT 24
Peak memory 197708 kb
Host smart-0a2609a0-9369-4690-a933-ba1fe05ceac9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249619876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4249619876
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2268758870
Short name T710
Test name
Test status
Simulation time 140657991 ps
CPU time 1.87 seconds
Started Jun 25 05:40:32 PM PDT 24
Finished Jun 25 05:40:35 PM PDT 24
Peak memory 198684 kb
Host smart-d1fd293a-cbc2-470f-919d-7588c9ef3622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268758870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2268758870
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1260465480
Short name T486
Test name
Test status
Simulation time 89580806 ps
CPU time 0.81 seconds
Started Jun 25 05:40:17 PM PDT 24
Finished Jun 25 05:40:19 PM PDT 24
Peak memory 196028 kb
Host smart-ceb02c48-eda1-4b6b-921d-9aeeb1eebdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260465480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1260465480
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2787836601
Short name T186
Test name
Test status
Simulation time 62731069 ps
CPU time 1.26 seconds
Started Jun 25 05:40:23 PM PDT 24
Finished Jun 25 05:40:25 PM PDT 24
Peak memory 197564 kb
Host smart-6aa7c654-6fc8-4680-ae53-a124a8c67b26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787836601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2787836601
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1839453755
Short name T615
Test name
Test status
Simulation time 14358980650 ps
CPU time 39.95 seconds
Started Jun 25 05:40:24 PM PDT 24
Finished Jun 25 05:41:05 PM PDT 24
Peak memory 198832 kb
Host smart-c574d8a8-2681-48e3-8368-2d7a84ae5818
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839453755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1839453755
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1133471197
Short name T55
Test name
Test status
Simulation time 57518744446 ps
CPU time 938.57 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:56:04 PM PDT 24
Peak memory 198928 kb
Host smart-82e24a3c-c630-41d0-b5e7-cd00d84f2586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1133471197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1133471197
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1931552991
Short name T446
Test name
Test status
Simulation time 14683446 ps
CPU time 0.59 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:40:28 PM PDT 24
Peak memory 195156 kb
Host smart-98cac3b2-f4e9-47fb-b23b-0c1588a76dd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931552991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1931552991
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3268641563
Short name T449
Test name
Test status
Simulation time 60973472 ps
CPU time 1 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:40:27 PM PDT 24
Peak memory 196720 kb
Host smart-0be46e46-de64-4291-bd7b-fa0379e9aade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268641563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3268641563
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.585160245
Short name T520
Test name
Test status
Simulation time 5642485635 ps
CPU time 24.28 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:53 PM PDT 24
Peak memory 197740 kb
Host smart-da7cac29-bbe4-45b6-928b-d14f3b24dc6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585160245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.585160245
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.537115257
Short name T420
Test name
Test status
Simulation time 30450391 ps
CPU time 0.65 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:30 PM PDT 24
Peak memory 195308 kb
Host smart-4eab4c20-28a0-4e17-914c-e1e063d7ca28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537115257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.537115257
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1048030356
Short name T541
Test name
Test status
Simulation time 56292066 ps
CPU time 1.09 seconds
Started Jun 25 05:40:30 PM PDT 24
Finished Jun 25 05:40:33 PM PDT 24
Peak memory 196720 kb
Host smart-edd433d6-f502-4dd6-ac78-5ae761a374a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048030356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1048030356
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.524049348
Short name T181
Test name
Test status
Simulation time 59557910 ps
CPU time 2.59 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 198732 kb
Host smart-6850d644-d496-4048-8678-14bf841594c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524049348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.524049348
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2549580845
Short name T414
Test name
Test status
Simulation time 120664099 ps
CPU time 1.25 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 196828 kb
Host smart-3a4cc3a7-24b0-418a-b007-e26c13af73dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549580845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2549580845
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3160588848
Short name T494
Test name
Test status
Simulation time 274067878 ps
CPU time 1.37 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 197624 kb
Host smart-3562675b-9dfc-4bc1-a2b8-879a4dcdaa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160588848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3160588848
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1993017709
Short name T691
Test name
Test status
Simulation time 65008609 ps
CPU time 1.05 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:40:28 PM PDT 24
Peak memory 196516 kb
Host smart-aa079209-5a21-43ae-a900-e694bd811858
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993017709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1993017709
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.1846686600
Short name T391
Test name
Test status
Simulation time 70487768 ps
CPU time 3.4 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:33 PM PDT 24
Peak memory 198692 kb
Host smart-cd0fbaf7-ad94-4f84-a46c-c2a094fc1584
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846686600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.1846686600
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.25975503
Short name T524
Test name
Test status
Simulation time 80345450 ps
CPU time 0.9 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 196188 kb
Host smart-10ca7d5d-2bb3-495c-a1df-6a0802d34478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25975503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.25975503
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1152660366
Short name T95
Test name
Test status
Simulation time 320534085 ps
CPU time 1.14 seconds
Started Jun 25 05:40:29 PM PDT 24
Finished Jun 25 05:40:32 PM PDT 24
Peak memory 196936 kb
Host smart-f40780c4-1631-45f3-951c-127496e8a3a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152660366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1152660366
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2207400070
Short name T187
Test name
Test status
Simulation time 55036849907 ps
CPU time 194.88 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:43:47 PM PDT 24
Peak memory 198864 kb
Host smart-b2ee9e89-2e46-4d28-94ce-31c4cf6395a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207400070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2207400070
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2528228448
Short name T22
Test name
Test status
Simulation time 38929911402 ps
CPU time 140.86 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:42:47 PM PDT 24
Peak memory 198984 kb
Host smart-8c8ce346-2dba-400f-874c-26c985480d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2528228448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2528228448
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2778011678
Short name T605
Test name
Test status
Simulation time 60680826 ps
CPU time 0.58 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:40:27 PM PDT 24
Peak memory 194680 kb
Host smart-4928f47e-118d-487a-bcb9-90e0bcfc0d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778011678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2778011678
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.4265726703
Short name T144
Test name
Test status
Simulation time 36255336 ps
CPU time 0.65 seconds
Started Jun 25 05:40:31 PM PDT 24
Finished Jun 25 05:40:33 PM PDT 24
Peak memory 194756 kb
Host smart-ad03a793-d61a-4a02-8696-7c5cf92f3ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265726703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.4265726703
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.682782498
Short name T238
Test name
Test status
Simulation time 1737971080 ps
CPU time 26.23 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:56 PM PDT 24
Peak memory 197548 kb
Host smart-46735001-5af0-4b58-9efa-306e0e12847d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682782498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.682782498
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2855989785
Short name T481
Test name
Test status
Simulation time 173061750 ps
CPU time 0.91 seconds
Started Jun 25 05:40:25 PM PDT 24
Finished Jun 25 05:40:27 PM PDT 24
Peak memory 197764 kb
Host smart-6492ff3e-dc2d-48b7-9019-52c02af64cd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855989785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2855989785
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.2930996729
Short name T333
Test name
Test status
Simulation time 200170535 ps
CPU time 1.41 seconds
Started Jun 25 05:40:38 PM PDT 24
Finished Jun 25 05:40:40 PM PDT 24
Peak memory 197612 kb
Host smart-185cda6d-8b62-421a-93f5-5b7e19d94146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930996729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.2930996729
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2993950022
Short name T329
Test name
Test status
Simulation time 179259122 ps
CPU time 3.52 seconds
Started Jun 25 05:40:24 PM PDT 24
Finished Jun 25 05:40:29 PM PDT 24
Peak memory 198728 kb
Host smart-996be343-29d4-4308-8415-acf6d9add17f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993950022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2993950022
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3682024852
Short name T325
Test name
Test status
Simulation time 175334959 ps
CPU time 3.45 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 198796 kb
Host smart-709a096e-151d-486f-a63d-a69bd2f325e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682024852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3682024852
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3484060871
Short name T148
Test name
Test status
Simulation time 27722538 ps
CPU time 0.79 seconds
Started Jun 25 05:40:28 PM PDT 24
Finished Jun 25 05:40:31 PM PDT 24
Peak memory 196144 kb
Host smart-550f8242-d3fa-4676-9477-60f736d32e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484060871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3484060871
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3592318075
Short name T264
Test name
Test status
Simulation time 777757824 ps
CPU time 1.28 seconds
Started Jun 25 05:40:34 PM PDT 24
Finished Jun 25 05:40:37 PM PDT 24
Peak memory 196496 kb
Host smart-2fef3f1c-5bfb-4d60-bc8c-11a229916188
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592318075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3592318075
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1913614117
Short name T403
Test name
Test status
Simulation time 26877910 ps
CPU time 1.26 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:40:29 PM PDT 24
Peak memory 198668 kb
Host smart-1538ae99-5300-4234-a3c6-d0c6f6879cd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913614117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1913614117
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4254153642
Short name T326
Test name
Test status
Simulation time 64508084 ps
CPU time 1.42 seconds
Started Jun 25 05:40:40 PM PDT 24
Finished Jun 25 05:40:43 PM PDT 24
Peak memory 198680 kb
Host smart-78224b0b-2d35-458d-b430-03546e88cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254153642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4254153642
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1202937480
Short name T528
Test name
Test status
Simulation time 46470263 ps
CPU time 1.35 seconds
Started Jun 25 05:40:27 PM PDT 24
Finished Jun 25 05:40:30 PM PDT 24
Peak memory 197444 kb
Host smart-2e262912-e2a3-497a-b57f-5f3a39144981
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202937480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1202937480
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.719600102
Short name T471
Test name
Test status
Simulation time 14215660416 ps
CPU time 168.65 seconds
Started Jun 25 05:40:26 PM PDT 24
Finished Jun 25 05:43:16 PM PDT 24
Peak memory 198604 kb
Host smart-2c97805f-57a2-432a-84bd-71fb7f8e18da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719600102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.719600102
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3145301351
Short name T867
Test name
Test status
Simulation time 39497055 ps
CPU time 1.04 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:55 PM PDT 24
Peak memory 197172 kb
Host smart-83ea0b8e-7257-4fd6-913b-b43f505de415
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3145301351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3145301351
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2576813782
Short name T871
Test name
Test status
Simulation time 46882290 ps
CPU time 0.99 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 197120 kb
Host smart-27e29eda-99f3-4a53-9520-217cecfa2beb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576813782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2576813782
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2060204667
Short name T912
Test name
Test status
Simulation time 68143802 ps
CPU time 0.88 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 195860 kb
Host smart-38b3067a-146d-4df7-a3fc-0dc18be86661
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2060204667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2060204667
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.316765682
Short name T861
Test name
Test status
Simulation time 223698509 ps
CPU time 1.65 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 197280 kb
Host smart-365d572f-9bd0-4850-a94b-569bdb4175e1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316765682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.316765682
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1099085867
Short name T915
Test name
Test status
Simulation time 122178309 ps
CPU time 1 seconds
Started Jun 25 05:39:56 PM PDT 24
Finished Jun 25 05:39:59 PM PDT 24
Peak memory 197100 kb
Host smart-47bcfd1d-cfc5-459d-9fa2-784bca0e514a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1099085867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1099085867
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1466106946
Short name T922
Test name
Test status
Simulation time 199503807 ps
CPU time 1.36 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196992 kb
Host smart-1a2b5b99-50a9-403d-9563-0d7b652e08cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466106946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1466106946
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.112610543
Short name T869
Test name
Test status
Simulation time 233180074 ps
CPU time 1.03 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 196428 kb
Host smart-02726154-52a9-4ecb-b674-63220c39f7ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=112610543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.112610543
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3754682168
Short name T899
Test name
Test status
Simulation time 178935238 ps
CPU time 1.43 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 197032 kb
Host smart-a0005025-6c1c-4a05-8763-b6bf50321a8b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754682168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3754682168
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.658459110
Short name T905
Test name
Test status
Simulation time 69597193 ps
CPU time 1.17 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:02 PM PDT 24
Peak memory 197004 kb
Host smart-37f0deab-c3fd-431f-82d8-07875b304631
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=658459110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.658459110
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3067033901
Short name T926
Test name
Test status
Simulation time 124895490 ps
CPU time 0.97 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 196400 kb
Host smart-d87343c5-3ba0-4269-8bf7-fd14b92ae286
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067033901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3067033901
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1535051215
Short name T939
Test name
Test status
Simulation time 141287899 ps
CPU time 0.86 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:54 PM PDT 24
Peak memory 195916 kb
Host smart-4f3e473d-eafd-4b0d-9f0d-82ebd73147bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1535051215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1535051215
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.159865037
Short name T913
Test name
Test status
Simulation time 145324844 ps
CPU time 1.38 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:54 PM PDT 24
Peak memory 197696 kb
Host smart-662fdf6e-3322-40a4-82fc-b72af8e8b4da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159865037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.159865037
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2313464450
Short name T887
Test name
Test status
Simulation time 88363694 ps
CPU time 0.95 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 197000 kb
Host smart-76143b71-a51f-45e0-8400-13c012b1861e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2313464450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2313464450
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.85403385
Short name T851
Test name
Test status
Simulation time 146046293 ps
CPU time 1.41 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 196316 kb
Host smart-5d6414af-9c64-4bdf-a702-d6043342a2cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85403385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.85403385
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2376666647
Short name T870
Test name
Test status
Simulation time 56079798 ps
CPU time 1.35 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:58 PM PDT 24
Peak memory 197396 kb
Host smart-d4ed6992-ee19-4460-ae59-8fe103c894ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2376666647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2376666647
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2895344535
Short name T858
Test name
Test status
Simulation time 54779187 ps
CPU time 1.17 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 196884 kb
Host smart-0d33b446-86f4-451d-9297-e2457be5f728
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895344535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2895344535
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2900603261
Short name T917
Test name
Test status
Simulation time 55928539 ps
CPU time 1.38 seconds
Started Jun 25 05:39:56 PM PDT 24
Finished Jun 25 05:40:00 PM PDT 24
Peak memory 197192 kb
Host smart-1ad7ed22-aec6-4ceb-b6b6-631eb1d7a643
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2900603261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2900603261
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1124218871
Short name T929
Test name
Test status
Simulation time 48114718 ps
CPU time 1.17 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 197316 kb
Host smart-7991002f-8093-4924-b65d-823ec032fa82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124218871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1124218871
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1554964375
Short name T877
Test name
Test status
Simulation time 24910019 ps
CPU time 0.74 seconds
Started Jun 25 05:39:56 PM PDT 24
Finished Jun 25 05:39:59 PM PDT 24
Peak memory 194640 kb
Host smart-49a6e699-e45a-4294-89d5-42856df903c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1554964375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1554964375
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4038549337
Short name T925
Test name
Test status
Simulation time 38636964 ps
CPU time 1.13 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:54 PM PDT 24
Peak memory 197080 kb
Host smart-95a9094a-343b-4ec1-bc09-7560d474744e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038549337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4038549337
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2737056343
Short name T874
Test name
Test status
Simulation time 29132840 ps
CPU time 0.8 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196652 kb
Host smart-9a969e64-0dc7-4034-9a6a-cec8d9ef1586
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2737056343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2737056343
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2919075174
Short name T919
Test name
Test status
Simulation time 88792563 ps
CPU time 1.61 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 198488 kb
Host smart-b61d70bf-704b-440a-ab69-087340b431f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919075174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2919075174
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.645361026
Short name T843
Test name
Test status
Simulation time 77215360 ps
CPU time 1.04 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196992 kb
Host smart-5b33f531-9230-4a7c-bb2e-c84d5b5e3697
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=645361026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.645361026
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.477643673
Short name T931
Test name
Test status
Simulation time 131718166 ps
CPU time 0.8 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 195884 kb
Host smart-9b77431b-f916-4aa4-adff-669c439ec0cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477643673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.477643673
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.4010498866
Short name T848
Test name
Test status
Simulation time 121819708 ps
CPU time 0.91 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 197168 kb
Host smart-93d360b6-b408-4787-829f-8dca100d0f47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4010498866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.4010498866
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.877859494
Short name T846
Test name
Test status
Simulation time 44109638 ps
CPU time 1.14 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 197220 kb
Host smart-b9699cef-0db8-4774-a624-f2e605342f5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877859494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.877859494
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.585018952
Short name T856
Test name
Test status
Simulation time 81066419 ps
CPU time 1.04 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 196136 kb
Host smart-ad2bec8a-ed5a-4fbe-8105-b6738c07f836
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=585018952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.585018952
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1130525757
Short name T850
Test name
Test status
Simulation time 39495280 ps
CPU time 1.1 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:58 PM PDT 24
Peak memory 197024 kb
Host smart-66b2dc33-cf31-4388-8a21-317aa0561b5c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130525757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1130525757
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.392734953
Short name T900
Test name
Test status
Simulation time 264909721 ps
CPU time 1.23 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196988 kb
Host smart-dc139917-5830-42ce-9b57-beedcbadfe16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=392734953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.392734953
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2436127094
Short name T863
Test name
Test status
Simulation time 52785317 ps
CPU time 1.44 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:58 PM PDT 24
Peak memory 197160 kb
Host smart-8c12ea54-ff6d-452c-9fd7-d9375459a18e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436127094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2436127094
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.263632842
Short name T845
Test name
Test status
Simulation time 80336793 ps
CPU time 0.76 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:54 PM PDT 24
Peak memory 196520 kb
Host smart-6737a63c-ac06-469f-b476-3a94687ee694
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=263632842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.263632842
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2673091379
Short name T934
Test name
Test status
Simulation time 189847143 ps
CPU time 1.45 seconds
Started Jun 25 05:39:55 PM PDT 24
Finished Jun 25 05:39:59 PM PDT 24
Peak memory 197048 kb
Host smart-62e2dc23-d976-4647-b848-0253f46e21ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673091379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2673091379
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3684386079
Short name T923
Test name
Test status
Simulation time 154251894 ps
CPU time 0.96 seconds
Started Jun 25 05:39:58 PM PDT 24
Finished Jun 25 05:40:00 PM PDT 24
Peak memory 196804 kb
Host smart-94f8a756-5304-4ae1-94b5-064627b58a11
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3684386079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3684386079
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3107775937
Short name T940
Test name
Test status
Simulation time 188216856 ps
CPU time 1.33 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196992 kb
Host smart-9817f86c-d901-42df-a605-af010e81cda5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107775937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3107775937
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4205174915
Short name T866
Test name
Test status
Simulation time 259331072 ps
CPU time 1.19 seconds
Started Jun 25 05:40:05 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 197184 kb
Host smart-a1ac872e-76b0-4ce7-89dd-3e6836eaec0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4205174915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4205174915
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1222625371
Short name T902
Test name
Test status
Simulation time 117316687 ps
CPU time 0.88 seconds
Started Jun 25 05:40:03 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 197880 kb
Host smart-f40b8bf4-cdde-46b1-bd3b-7a57369f417d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222625371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1222625371
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1420260535
Short name T888
Test name
Test status
Simulation time 41676058 ps
CPU time 0.97 seconds
Started Jun 25 05:40:05 PM PDT 24
Finished Jun 25 05:40:07 PM PDT 24
Peak memory 196076 kb
Host smart-1f667d94-c94f-4238-8637-328b9e1068ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1420260535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1420260535
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1640066990
Short name T928
Test name
Test status
Simulation time 61754624 ps
CPU time 1.03 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 197020 kb
Host smart-fcaedc47-855f-4a12-84f6-70da44a4d46c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640066990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1640066990
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2516317319
Short name T907
Test name
Test status
Simulation time 382064712 ps
CPU time 1.51 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:09 PM PDT 24
Peak memory 197232 kb
Host smart-3fa72989-b564-4d77-b1b8-50392de7e8e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2516317319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2516317319
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1858878277
Short name T864
Test name
Test status
Simulation time 122936336 ps
CPU time 1.07 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 198488 kb
Host smart-e69fc0ad-8111-497b-8a4f-93e66d326e02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858878277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1858878277
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2633171811
Short name T847
Test name
Test status
Simulation time 263694446 ps
CPU time 1.26 seconds
Started Jun 25 05:40:04 PM PDT 24
Finished Jun 25 05:40:07 PM PDT 24
Peak memory 198456 kb
Host smart-a8f766c2-29b9-4de4-af15-831f6f5785fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2633171811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2633171811
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.195170002
Short name T906
Test name
Test status
Simulation time 38205993 ps
CPU time 0.88 seconds
Started Jun 25 05:40:02 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 195728 kb
Host smart-c5ce6db0-5596-4c4f-802f-baffba32a58b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195170002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.195170002
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1402339313
Short name T891
Test name
Test status
Simulation time 47447000 ps
CPU time 1.02 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:01 PM PDT 24
Peak memory 196972 kb
Host smart-ccd6c79e-ce00-45ef-a1a7-b672ee6053e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1402339313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1402339313
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.151216523
Short name T914
Test name
Test status
Simulation time 339705000 ps
CPU time 0.97 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:02 PM PDT 24
Peak memory 196852 kb
Host smart-4e0f5628-c825-4566-81f8-6599f9684865
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151216523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.151216523
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.158407180
Short name T875
Test name
Test status
Simulation time 231211619 ps
CPU time 0.81 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:04 PM PDT 24
Peak memory 195732 kb
Host smart-2e3657c4-6e53-4c21-ad94-86e7248d522b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=158407180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.158407180
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3417381109
Short name T924
Test name
Test status
Simulation time 46059847 ps
CPU time 1.26 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:09 PM PDT 24
Peak memory 197044 kb
Host smart-993192a1-0bc6-4956-b439-28b85ceaf089
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417381109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3417381109
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.664440346
Short name T857
Test name
Test status
Simulation time 109706240 ps
CPU time 1.09 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:58 PM PDT 24
Peak memory 198316 kb
Host smart-f39ff878-b2d9-490a-893c-ef13ca471e8b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=664440346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.664440346
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.117663768
Short name T909
Test name
Test status
Simulation time 51897689 ps
CPU time 1.09 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196948 kb
Host smart-9d703e54-2a38-47dd-b70e-31d425725acc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117663768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.117663768
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2666443260
Short name T938
Test name
Test status
Simulation time 60944452 ps
CPU time 1.2 seconds
Started Jun 25 05:40:03 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 196168 kb
Host smart-1babeeb6-1a7b-4973-872e-61edd9189fcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2666443260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2666443260
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2478669870
Short name T879
Test name
Test status
Simulation time 194549279 ps
CPU time 1.54 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 197068 kb
Host smart-12a1c5b4-b50c-4539-b59f-3ee95242b436
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478669870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2478669870
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1496620424
Short name T894
Test name
Test status
Simulation time 86485786 ps
CPU time 0.98 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:04 PM PDT 24
Peak memory 195768 kb
Host smart-08ba7c8b-b718-433b-938e-b74a74c1c1ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1496620424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1496620424
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2908316766
Short name T921
Test name
Test status
Simulation time 62593856 ps
CPU time 1.12 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 197180 kb
Host smart-03d3663c-b05c-4c80-8863-89384a03b35a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908316766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2908316766
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1124987916
Short name T852
Test name
Test status
Simulation time 145384807 ps
CPU time 1.38 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 198468 kb
Host smart-1ce76037-40df-487f-8c81-0904b1846026
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1124987916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1124987916
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1907497601
Short name T884
Test name
Test status
Simulation time 380185303 ps
CPU time 1.01 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 196956 kb
Host smart-b9943c43-8c8d-42dc-9804-2108ae870ee8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907497601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1907497601
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2426629771
Short name T930
Test name
Test status
Simulation time 273069450 ps
CPU time 1.34 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:09 PM PDT 24
Peak memory 197252 kb
Host smart-152adb13-db9a-48b7-b003-0542233885cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2426629771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2426629771
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2921667501
Short name T927
Test name
Test status
Simulation time 51017891 ps
CPU time 0.92 seconds
Started Jun 25 05:40:04 PM PDT 24
Finished Jun 25 05:40:07 PM PDT 24
Peak memory 195956 kb
Host smart-bbdc00ec-e17c-43e8-96df-6eda00515abf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921667501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2921667501
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3201183102
Short name T932
Test name
Test status
Simulation time 36814114 ps
CPU time 1.06 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 198420 kb
Host smart-cdf9e813-c93f-475c-97b5-e32ebab4512e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3201183102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3201183102
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3901957335
Short name T886
Test name
Test status
Simulation time 96823229 ps
CPU time 1 seconds
Started Jun 25 05:40:03 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 198544 kb
Host smart-eb167f3e-5ee4-40b4-9a0e-2347cede24ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901957335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3901957335
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2952348180
Short name T935
Test name
Test status
Simulation time 306714108 ps
CPU time 1.43 seconds
Started Jun 25 05:40:05 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 197396 kb
Host smart-47374bde-29d2-4251-bd9a-f746e04ffd43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2952348180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2952348180
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3531728009
Short name T876
Test name
Test status
Simulation time 45865713 ps
CPU time 0.98 seconds
Started Jun 25 05:40:06 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 196956 kb
Host smart-2af2fe4f-374e-43fb-94fb-3bdc1801fd95
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531728009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3531728009
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3183754141
Short name T933
Test name
Test status
Simulation time 121441970 ps
CPU time 0.78 seconds
Started Jun 25 05:40:04 PM PDT 24
Finished Jun 25 05:40:07 PM PDT 24
Peak memory 195748 kb
Host smart-db309dcc-46ae-4020-8666-4f124979a0c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3183754141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3183754141
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2684001581
Short name T893
Test name
Test status
Simulation time 49746269 ps
CPU time 1.39 seconds
Started Jun 25 05:40:02 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 197072 kb
Host smart-788119c9-9013-42ca-aac8-c68c9d27e528
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684001581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2684001581
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3301287090
Short name T903
Test name
Test status
Simulation time 232569205 ps
CPU time 1.21 seconds
Started Jun 25 05:40:04 PM PDT 24
Finished Jun 25 05:40:07 PM PDT 24
Peak memory 197076 kb
Host smart-d3fcb4ff-b654-44c1-995a-6676b88c6180
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3301287090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3301287090
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3679528118
Short name T883
Test name
Test status
Simulation time 838459990 ps
CPU time 1.56 seconds
Started Jun 25 05:40:02 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 198460 kb
Host smart-6013b2b1-e0b9-4170-9a5b-7736c32aeb76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679528118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3679528118
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.915757676
Short name T897
Test name
Test status
Simulation time 66103575 ps
CPU time 1.29 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:04 PM PDT 24
Peak memory 196176 kb
Host smart-cad97ca7-8485-4077-a70b-7c9fa94ac052
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=915757676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.915757676
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3847378883
Short name T908
Test name
Test status
Simulation time 179885821 ps
CPU time 1.27 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:02 PM PDT 24
Peak memory 197160 kb
Host smart-68beed58-2adc-4386-ac20-637b21284d37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847378883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3847378883
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2113741486
Short name T860
Test name
Test status
Simulation time 68026334 ps
CPU time 1.25 seconds
Started Jun 25 05:39:58 PM PDT 24
Finished Jun 25 05:40:01 PM PDT 24
Peak memory 196996 kb
Host smart-28f22e22-b62f-4758-878c-86135808c435
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2113741486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2113741486
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1669660746
Short name T849
Test name
Test status
Simulation time 77314736 ps
CPU time 1.18 seconds
Started Jun 25 05:40:13 PM PDT 24
Finished Jun 25 05:40:16 PM PDT 24
Peak memory 197008 kb
Host smart-a184600d-02ac-4341-9dbe-5f116bed478e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669660746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1669660746
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1487315040
Short name T904
Test name
Test status
Simulation time 75567224 ps
CPU time 1.39 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 196160 kb
Host smart-75b8c10d-0ff7-4bf0-b84c-db13010d485e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1487315040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1487315040
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.127164412
Short name T872
Test name
Test status
Simulation time 72947722 ps
CPU time 1.23 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:55 PM PDT 24
Peak memory 198012 kb
Host smart-826db8d8-cf6f-4f34-80fd-3f9d684d6249
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127164412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.127164412
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3988975819
Short name T918
Test name
Test status
Simulation time 80816424 ps
CPU time 1.55 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:04 PM PDT 24
Peak memory 198508 kb
Host smart-03a90204-35b3-4b21-8823-aa4ceeb83a9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3988975819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3988975819
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2098751472
Short name T885
Test name
Test status
Simulation time 96993453 ps
CPU time 1.1 seconds
Started Jun 25 05:39:58 PM PDT 24
Finished Jun 25 05:40:01 PM PDT 24
Peak memory 197076 kb
Host smart-f5b57167-791c-4e10-bb7c-8b384b6cdde3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098751472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2098751472
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.563940833
Short name T910
Test name
Test status
Simulation time 469598313 ps
CPU time 1.14 seconds
Started Jun 25 05:40:08 PM PDT 24
Finished Jun 25 05:40:10 PM PDT 24
Peak memory 197052 kb
Host smart-bac7e777-1ea8-4619-a468-9b45d722756d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=563940833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.563940833
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.479193108
Short name T892
Test name
Test status
Simulation time 85968242 ps
CPU time 0.76 seconds
Started Jun 25 05:40:03 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 195780 kb
Host smart-120b09bd-1752-4806-9d0d-64bb33e323ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479193108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.479193108
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2560487447
Short name T878
Test name
Test status
Simulation time 41377460 ps
CPU time 1.13 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:02 PM PDT 24
Peak memory 197212 kb
Host smart-7f5e094b-955d-4680-b4ba-0008cc3409c4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2560487447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2560487447
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3770564766
Short name T941
Test name
Test status
Simulation time 132456799 ps
CPU time 1.16 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:02 PM PDT 24
Peak memory 197268 kb
Host smart-feb17363-fc2b-4502-badc-9cae52113708
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770564766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3770564766
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1337595803
Short name T881
Test name
Test status
Simulation time 26632182 ps
CPU time 0.95 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 196856 kb
Host smart-07d7032a-113c-42b9-a836-1d7137d6aff6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1337595803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1337595803
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4203903601
Short name T896
Test name
Test status
Simulation time 267661485 ps
CPU time 1.44 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:04 PM PDT 24
Peak memory 196964 kb
Host smart-88f9f772-8cf3-4755-b132-1b4ba2814ca4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203903601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4203903601
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.952362907
Short name T942
Test name
Test status
Simulation time 48505765 ps
CPU time 1.03 seconds
Started Jun 25 05:40:11 PM PDT 24
Finished Jun 25 05:40:13 PM PDT 24
Peak memory 196868 kb
Host smart-11217a4c-122a-4f28-aba1-75aebc0e2355
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=952362907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.952362907
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3113065774
Short name T854
Test name
Test status
Simulation time 150619609 ps
CPU time 1.5 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 196984 kb
Host smart-6b7f472e-9fcb-4587-ba74-9575c798efe7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113065774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3113065774
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1463499483
Short name T859
Test name
Test status
Simulation time 65186149 ps
CPU time 1.42 seconds
Started Jun 25 05:40:00 PM PDT 24
Finished Jun 25 05:40:04 PM PDT 24
Peak memory 197036 kb
Host smart-4d459d57-22d8-41f5-b2f1-23658efe1b3e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1463499483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1463499483
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.891763682
Short name T911
Test name
Test status
Simulation time 105714899 ps
CPU time 1.33 seconds
Started Jun 25 05:39:59 PM PDT 24
Finished Jun 25 05:40:03 PM PDT 24
Peak memory 198480 kb
Host smart-e68ead33-575e-48e7-9fc3-ce69913ea3e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891763682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.891763682
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1327884353
Short name T865
Test name
Test status
Simulation time 129825184 ps
CPU time 1.3 seconds
Started Jun 25 05:40:05 PM PDT 24
Finished Jun 25 05:40:08 PM PDT 24
Peak memory 197456 kb
Host smart-8687d005-e7f6-4b0f-a66c-881d49c82a94
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1327884353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1327884353
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3858157572
Short name T880
Test name
Test status
Simulation time 40550115 ps
CPU time 0.83 seconds
Started Jun 25 05:40:05 PM PDT 24
Finished Jun 25 05:40:07 PM PDT 24
Peak memory 195876 kb
Host smart-694c51c6-7ec2-4b9a-95e6-51fbf0efa09b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858157572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3858157572
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2900655741
Short name T868
Test name
Test status
Simulation time 65614299 ps
CPU time 1.33 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 197056 kb
Host smart-5c3f83e0-bd93-437e-bea2-8c26030167bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2900655741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2900655741
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.913010305
Short name T920
Test name
Test status
Simulation time 41477222 ps
CPU time 1.26 seconds
Started Jun 25 05:40:01 PM PDT 24
Finished Jun 25 05:40:05 PM PDT 24
Peak memory 196436 kb
Host smart-37229c18-8f95-43ce-8a8a-368fe1603ff0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913010305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.913010305
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3843290792
Short name T936
Test name
Test status
Simulation time 58623168 ps
CPU time 1.01 seconds
Started Jun 25 05:40:04 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 197108 kb
Host smart-56d43921-0f4c-4554-a6d8-c4a5cf18b8c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3843290792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3843290792
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3145163340
Short name T862
Test name
Test status
Simulation time 134757078 ps
CPU time 1.31 seconds
Started Jun 25 05:40:09 PM PDT 24
Finished Jun 25 05:40:12 PM PDT 24
Peak memory 197252 kb
Host smart-7845699b-a226-4ece-b5e4-3507ca23e8ae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145163340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3145163340
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4019433145
Short name T901
Test name
Test status
Simulation time 339325127 ps
CPU time 1.3 seconds
Started Jun 25 05:40:02 PM PDT 24
Finished Jun 25 05:40:06 PM PDT 24
Peak memory 197088 kb
Host smart-7baa9c4a-28a7-43c2-8163-1c7049dd00be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4019433145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4019433145
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983363892
Short name T889
Test name
Test status
Simulation time 116870514 ps
CPU time 0.99 seconds
Started Jun 25 05:40:16 PM PDT 24
Finished Jun 25 05:40:18 PM PDT 24
Peak memory 196908 kb
Host smart-0ef32a21-c4ab-4150-87be-ef176f7f628c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983363892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.983363892
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1524097379
Short name T937
Test name
Test status
Simulation time 116451541 ps
CPU time 0.8 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:54 PM PDT 24
Peak memory 195876 kb
Host smart-d103d121-2b14-4604-8054-05d13a66a7f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1524097379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1524097379
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1470476543
Short name T844
Test name
Test status
Simulation time 99308546 ps
CPU time 0.86 seconds
Started Jun 25 05:39:55 PM PDT 24
Finished Jun 25 05:39:58 PM PDT 24
Peak memory 195884 kb
Host smart-7e77b7b2-fd37-4659-9978-6f3efa91af59
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470476543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1470476543
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2446337542
Short name T916
Test name
Test status
Simulation time 296104745 ps
CPU time 1.24 seconds
Started Jun 25 05:39:54 PM PDT 24
Finished Jun 25 05:39:58 PM PDT 24
Peak memory 197016 kb
Host smart-015f3c1c-324a-4943-bee9-49c8a7ca1d5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2446337542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2446337542
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.847883116
Short name T882
Test name
Test status
Simulation time 38867822 ps
CPU time 0.85 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 196080 kb
Host smart-f63a4bb3-387d-4576-9c3c-f9fcf86aad92
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847883116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.847883116
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.845872902
Short name T855
Test name
Test status
Simulation time 75736590 ps
CPU time 1.24 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 197032 kb
Host smart-45e38b45-b3d5-4a68-836f-6ce2efb48ed8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=845872902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.845872902
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.938075779
Short name T895
Test name
Test status
Simulation time 18008241 ps
CPU time 0.74 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 194816 kb
Host smart-f3fd2c9d-668b-47bb-8d6d-081ca11ef492
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938075779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.938075779
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.755061247
Short name T898
Test name
Test status
Simulation time 63633007 ps
CPU time 1 seconds
Started Jun 25 05:39:51 PM PDT 24
Finished Jun 25 05:39:53 PM PDT 24
Peak memory 196128 kb
Host smart-d257c45e-d939-4f3a-bb85-b95a85943f51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=755061247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.755061247
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4134228540
Short name T853
Test name
Test status
Simulation time 46250096 ps
CPU time 1.11 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:57 PM PDT 24
Peak memory 198484 kb
Host smart-8ca5bd5b-881c-4457-b4a1-0e466ceec545
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134228540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4134228540
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3651175504
Short name T873
Test name
Test status
Simulation time 98673849 ps
CPU time 0.82 seconds
Started Jun 25 05:39:53 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196432 kb
Host smart-ad250a1c-be3e-4921-9362-d514d09fb88d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3651175504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3651175504
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731822922
Short name T890
Test name
Test status
Simulation time 34326213 ps
CPU time 1.15 seconds
Started Jun 25 05:39:52 PM PDT 24
Finished Jun 25 05:39:56 PM PDT 24
Peak memory 196932 kb
Host smart-6653fb03-d9a4-4c44-a756-b6c95428d93e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731822922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2731822922
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%