Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3041965	1			T21	40		T22	1		T23	1
all_pins[1]	3041965	1			T21	40		T22	1		T23	1
all_pins[2]	3041965	1			T21	40		T22	1		T23	1
all_pins[3]	3041965	1			T21	40		T22	1		T23	1
all_pins[4]	3041965	1			T21	40		T22	1		T23	1
all_pins[5]	3041965	1			T21	40		T22	1		T23	1
all_pins[6]	3041965	1			T21	40		T22	1		T23	1
all_pins[7]	3041965	1			T21	40		T22	1		T23	1
all_pins[8]	3041965	1			T21	40		T22	1		T23	1
all_pins[9]	3041965	1			T21	40		T22	1		T23	1
all_pins[10]	3041965	1			T21	40		T22	1		T23	1
all_pins[11]	3041965	1			T21	40		T22	1		T23	1
all_pins[12]	3041965	1			T21	40		T22	1		T23	1
all_pins[13]	3041965	1			T21	40		T22	1		T23	1
all_pins[14]	3041965	1			T21	40		T22	1		T23	1
all_pins[15]	3041965	1			T21	40		T22	1		T23	1
all_pins[16]	3041965	1			T21	40		T22	1		T23	1
all_pins[17]	3041965	1			T21	40		T22	1		T23	1
all_pins[18]	3041965	1			T21	40		T22	1		T23	1
all_pins[19]	3041965	1			T21	40		T22	1		T23	1
all_pins[20]	3041965	1			T21	40		T22	1		T23	1
all_pins[21]	3041965	1			T21	40		T22	1		T23	1
all_pins[22]	3041965	1			T21	40		T22	1		T23	1
all_pins[23]	3041965	1			T21	40		T22	1		T23	1
all_pins[24]	3041965	1			T21	40		T22	1		T23	1
all_pins[25]	3041965	1			T21	40		T22	1		T23	1
all_pins[26]	3041965	1			T21	40		T22	1		T23	1
all_pins[27]	3041965	1			T21	40		T22	1		T23	1
all_pins[28]	3041965	1			T21	40		T22	1		T23	1
all_pins[29]	3041965	1			T21	40		T22	1		T23	1
all_pins[30]	3041965	1			T21	40		T22	1		T23	1
all_pins[31]	3041965	1			T21	40		T22	1		T23	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	60481188	1			T21	681		T22	32		T23	32
values[0x1]	36861692	1			T21	599		T26	5261		T27	337237
transitions[0x0=>0x1]	22078563	1			T21	324		T26	3155		T27	202249
transitions[0x1=>0x0]	22078389	1			T21	323		T26	3155		T27	202249

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1894584	1			T21	21		T22	1		T23	1
all_pins[0]	values[0x1]	1147381	1			T21	19		T26	196		T27	10217
all_pins[0]	transitions[0x0=>0x1]	706529	1			T21	8		T26	130		T27	6328
all_pins[0]	transitions[0x1=>0x0]	715217	1			T21	7		T26	60		T27	6905
all_pins[1]	values[0x0]	1884872	1			T21	22		T22	1		T23	1
all_pins[1]	values[0x1]	1157093	1			T21	18		T26	155		T27	10740
all_pins[1]	transitions[0x0=>0x1]	694620	1			T21	7		T26	61		T27	6587
all_pins[1]	transitions[0x1=>0x0]	684908	1			T21	8		T26	102		T27	6064
all_pins[2]	values[0x0]	1892433	1			T21	16		T22	1		T23	1
all_pins[2]	values[0x1]	1149532	1			T21	24		T26	181		T27	10648
all_pins[2]	transitions[0x0=>0x1]	686858	1			T21	12		T26	115		T27	6383
all_pins[2]	transitions[0x1=>0x0]	694419	1			T21	6		T26	89		T27	6475
all_pins[3]	values[0x0]	1892126	1			T21	28		T22	1		T23	1
all_pins[3]	values[0x1]	1149839	1			T21	12		T26	111		T27	10511
all_pins[3]	transitions[0x0=>0x1]	689586	1			T21	7		T26	62		T27	6273
all_pins[3]	transitions[0x1=>0x0]	689279	1			T21	19		T26	132		T27	6410
all_pins[4]	values[0x0]	1888966	1			T21	22		T22	1		T23	1
all_pins[4]	values[0x1]	1152999	1			T21	18		T26	199		T27	10664
all_pins[4]	transitions[0x0=>0x1]	688999	1			T21	13		T26	154		T27	6346
all_pins[4]	transitions[0x1=>0x0]	685839	1			T21	7		T26	66		T27	6193
all_pins[5]	values[0x0]	1891159	1			T21	24		T22	1		T23	1
all_pins[5]	values[0x1]	1150806	1			T21	16		T26	156		T27	10778
all_pins[5]	transitions[0x0=>0x1]	690279	1			T21	11		T26	116		T27	6223
all_pins[5]	transitions[0x1=>0x0]	692472	1			T21	13		T26	159		T27	6109
all_pins[6]	values[0x0]	1887926	1			T21	18		T22	1		T23	1
all_pins[6]	values[0x1]	1154039	1			T21	22		T26	103		T27	10825
all_pins[6]	transitions[0x0=>0x1]	692262	1			T21	15		T26	63		T27	6497
all_pins[6]	transitions[0x1=>0x0]	689029	1			T21	9		T26	116		T27	6450
all_pins[7]	values[0x0]	1892600	1			T21	18		T22	1		T23	1
all_pins[7]	values[0x1]	1149365	1			T21	22		T26	149		T27	10193
all_pins[7]	transitions[0x0=>0x1]	686418	1			T21	11		T26	110		T27	5869
all_pins[7]	transitions[0x1=>0x0]	691092	1			T21	11		T26	64		T27	6501
all_pins[8]	values[0x0]	1892678	1			T21	23		T22	1		T23	1
all_pins[8]	values[0x1]	1149287	1			T21	17		T26	186		T27	10746
all_pins[8]	transitions[0x0=>0x1]	687883	1			T21	9		T26	116		T27	6494
all_pins[8]	transitions[0x1=>0x0]	687961	1			T21	14		T26	79		T27	5941
all_pins[9]	values[0x0]	1888488	1			T21	21		T22	1		T23	1
all_pins[9]	values[0x1]	1153477	1			T21	19		T26	141		T27	10798
all_pins[9]	transitions[0x0=>0x1]	693681	1			T21	10		T26	82		T27	6371
all_pins[9]	transitions[0x1=>0x0]	689491	1			T21	8		T26	127		T27	6319
all_pins[10]	values[0x0]	1888779	1			T21	15		T22	1		T23	1
all_pins[10]	values[0x1]	1153186	1			T21	25		T26	228		T27	10319
all_pins[10]	transitions[0x0=>0x1]	689266	1			T21	11		T26	155		T27	6032
all_pins[10]	transitions[0x1=>0x0]	689557	1			T21	5		T26	68		T27	6511
all_pins[11]	values[0x0]	1887747	1			T21	18		T22	1		T23	1
all_pins[11]	values[0x1]	1154218	1			T21	22		T26	169		T27	10402
all_pins[11]	transitions[0x0=>0x1]	693511	1			T21	10		T26	65		T27	6393
all_pins[11]	transitions[0x1=>0x0]	692479	1			T21	13		T26	124		T27	6310
all_pins[12]	values[0x0]	1894398	1			T21	23		T22	1		T23	1
all_pins[12]	values[0x1]	1147567	1			T21	17		T26	173		T27	10629
all_pins[12]	transitions[0x0=>0x1]	687025	1			T21	6		T26	118		T27	6613
all_pins[12]	transitions[0x1=>0x0]	693676	1			T21	11		T26	114		T27	6386
all_pins[13]	values[0x0]	1890252	1			T21	24		T22	1		T23	1
all_pins[13]	values[0x1]	1151713	1			T21	16		T26	208		T27	10412
all_pins[13]	transitions[0x0=>0x1]	690620	1			T21	11		T26	126		T27	6277
all_pins[13]	transitions[0x1=>0x0]	686474	1			T21	12		T26	91		T27	6494
all_pins[14]	values[0x0]	1890939	1			T21	23		T22	1		T23	1
all_pins[14]	values[0x1]	1151026	1			T21	17		T26	176		T27	10829
all_pins[14]	transitions[0x0=>0x1]	689730	1			T21	12		T26	98		T27	6319
all_pins[14]	transitions[0x1=>0x0]	690417	1			T21	11		T26	130		T27	5902
all_pins[15]	values[0x0]	1883774	1			T21	24		T22	1		T23	1
all_pins[15]	values[0x1]	1158191	1			T21	16		T26	167		T27	10134
all_pins[15]	transitions[0x0=>0x1]	693652	1			T21	10		T26	103		T27	5899
all_pins[15]	transitions[0x1=>0x0]	686487	1			T21	11		T26	112		T27	6594
all_pins[16]	values[0x0]	1888403	1			T21	20		T22	1		T23	1
all_pins[16]	values[0x1]	1153562	1			T21	20		T26	185		T27	10562
all_pins[16]	transitions[0x0=>0x1]	685233	1			T21	13		T26	95		T27	6452
all_pins[16]	transitions[0x1=>0x0]	689862	1			T21	9		T26	77		T27	6024
all_pins[17]	values[0x0]	1889839	1			T21	17		T22	1		T23	1
all_pins[17]	values[0x1]	1152126	1			T21	23		T26	189		T27	10589
all_pins[17]	transitions[0x0=>0x1]	689650	1			T21	11		T26	111		T27	6257
all_pins[17]	transitions[0x1=>0x0]	691086	1			T21	8		T26	107		T27	6230
all_pins[18]	values[0x0]	1886469	1			T21	23		T22	1		T23	1
all_pins[18]	values[0x1]	1155496	1			T21	17		T26	120		T27	10608
all_pins[18]	transitions[0x0=>0x1]	690639	1			T21	9		T26	73		T27	6212
all_pins[18]	transitions[0x1=>0x0]	687269	1			T21	15		T26	142		T27	6193
all_pins[19]	values[0x0]	1892672	1			T21	30		T22	1		T23	1
all_pins[19]	values[0x1]	1149293	1			T21	10		T26	159		T27	10159
all_pins[19]	transitions[0x0=>0x1]	685801	1			T21	7		T26	101		T27	6074
all_pins[19]	transitions[0x1=>0x0]	692004	1			T21	14		T26	62		T27	6523
all_pins[20]	values[0x0]	1890484	1			T21	17		T22	1		T23	1
all_pins[20]	values[0x1]	1151481	1			T21	23		T26	166		T27	10718
all_pins[20]	transitions[0x0=>0x1]	688363	1			T21	17		T26	111		T27	6632
all_pins[20]	transitions[0x1=>0x0]	686175	1			T21	4		T26	104		T27	6073
all_pins[21]	values[0x0]	1890970	1			T21	20		T22	1		T23	1
all_pins[21]	values[0x1]	1150995	1			T21	20		T26	177		T27	10667
all_pins[21]	transitions[0x0=>0x1]	685551	1			T21	6		T26	87		T27	6436
all_pins[21]	transitions[0x1=>0x0]	686037	1			T21	9		T26	76		T27	6487
all_pins[22]	values[0x0]	1892172	1			T21	15		T22	1		T23	1
all_pins[22]	values[0x1]	1149793	1			T21	25		T26	130		T27	10246
all_pins[22]	transitions[0x0=>0x1]	688902	1			T21	11		T26	88		T27	6121
all_pins[22]	transitions[0x1=>0x0]	690104	1			T21	6		T26	135		T27	6542
all_pins[23]	values[0x0]	1889625	1			T21	20		T22	1		T23	1
all_pins[23]	values[0x1]	1152340	1			T21	20		T26	148		T27	10560
all_pins[23]	transitions[0x0=>0x1]	689417	1			T21	5		T26	109		T27	6403
all_pins[23]	transitions[0x1=>0x0]	686870	1			T21	10		T26	91		T27	6089
all_pins[24]	values[0x0]	1892321	1			T21	23		T22	1		T23	1
all_pins[24]	values[0x1]	1149644	1			T21	17		T26	150		T27	10615
all_pins[24]	transitions[0x0=>0x1]	687670	1			T21	6		T26	78		T27	6299
all_pins[24]	transitions[0x1=>0x0]	690366	1			T21	9		T26	76		T27	6244
all_pins[25]	values[0x0]	1888964	1			T21	22		T22	1		T23	1
all_pins[25]	values[0x1]	1153001	1			T21	18		T26	217		T27	10544
all_pins[25]	transitions[0x0=>0x1]	690185	1			T21	13		T26	121		T27	6121
all_pins[25]	transitions[0x1=>0x0]	686828	1			T21	12		T26	54		T27	6192
all_pins[26]	values[0x0]	1890977	1			T21	23		T22	1		T23	1
all_pins[26]	values[0x1]	1150988	1			T21	17		T26	164		T27	10259
all_pins[26]	transitions[0x0=>0x1]	687455	1			T21	12		T26	79		T27	6396
all_pins[26]	transitions[0x1=>0x0]	689468	1			T21	13		T26	132		T27	6681
all_pins[27]	values[0x0]	1888755	1			T21	25		T22	1		T23	1
all_pins[27]	values[0x1]	1153210	1			T21	15		T26	119		T27	10517
all_pins[27]	transitions[0x0=>0x1]	690275	1			T21	9		T26	56		T27	6690
all_pins[27]	transitions[0x1=>0x0]	688053	1			T21	11		T26	101		T27	6432
all_pins[28]	values[0x0]	1886833	1			T21	29		T22	1		T23	1
all_pins[28]	values[0x1]	1155132	1			T21	11		T26	152		T27	10461
all_pins[28]	transitions[0x0=>0x1]	689665	1			T21	7		T26	86		T27	6195
all_pins[28]	transitions[0x1=>0x0]	687743	1			T21	11		T26	53		T27	6251
all_pins[29]	values[0x0]	1892523	1			T21	14		T22	1		T23	1
all_pins[29]	values[0x1]	1149442	1			T21	26		T26	228		T27	10681
all_pins[29]	transitions[0x0=>0x1]	685901	1			T21	21		T26	129		T27	6519
all_pins[29]	transitions[0x1=>0x0]	691591	1			T21	6		T26	53		T27	6299
all_pins[30]	values[0x0]	1892738	1			T21	22		T22	1		T23	1
all_pins[30]	values[0x1]	1149227	1			T21	18		T26	133		T27	10412
all_pins[30]	transitions[0x0=>0x1]	688095	1			T21	8		T26	83		T27	6132
all_pins[30]	transitions[0x1=>0x0]	688310	1			T21	16		T26	178		T27	6401
all_pins[31]	values[0x0]	1885722	1			T21	21		T22	1		T23	1
all_pins[31]	values[0x1]	1156243	1			T21	19		T26	126		T27	10794
all_pins[31]	transitions[0x0=>0x1]	694842	1			T21	6		T26	74		T27	6406
all_pins[31]	transitions[0x1=>0x0]	687826	1			T21	5		T26	81		T27	6024