Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[1]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[2]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[3]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[4]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[5]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[6]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[7]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[8]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[9]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[10]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[11]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[12]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[13]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[14]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[15]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[16]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[17]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[18]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[19]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[20]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[21]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[22]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[23]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[24]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[25]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[26]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[27]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[28]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[29]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[30]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[31]	10512852	1			T21	448		T22	563		T23	229

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193270728

1

T21

7312

T22

12505

T23

5797

auto[1]

143140536

1

T21

7024

T22

5511

T23

1531

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

271021788

1

T21

14336

T22

11592

T23

6808

auto[1]

65389476

1

T22

6424

T23

520

T24

4532

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

251909367

1

T21

14336

T22

11559

T23

4460

auto[1]

84501897

1

T22

6457

T23

2868

T24

4619

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	3799042	1			T21	258		T22	174		T23	51
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3039950	1			T21	190		T22	76		T23	18
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1031414	1			T22	85		T23	3		T24	90
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1195773	1			T22	100		T23	118		T24	64
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	429449	1			T23	26		T27	1370		T30	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1017224	1			T22	128		T23	13		T24	59
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	3814260	1			T21	232		T22	205		T23	40
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3033896	1			T21	216		T22	71		T23	13
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1028160	1			T22	100		T23	2		T24	70
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1193496	1			T22	94		T23	133		T24	101
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	428188	1			T23	24		T27	1222		T30	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1014852	1			T22	93		T23	17		T24	58
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	3824038	1			T21	241		T22	171		T23	56
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3021429	1			T21	207		T22	83		T23	7
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1024346	1			T22	102		T23	8		T24	66
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1195280	1			T22	81		T23	123		T24	74
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	430120	1			T23	23		T27	1209		T30	15
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1017639	1			T22	126		T23	12		T24	58
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	3822826	1			T21	190		T22	210		T23	139
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3022308	1			T21	258		T22	55		T23	36
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1032950	1			T22	106		T23	17		T24	63
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1194301	1			T22	114		T23	29		T24	74
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	428660	1			T23	8		T27	1180		T30	21
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1011807	1			T22	78		T24	90		T25	118
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	3814180	1			T21	236		T22	175		T23	137
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3027166	1			T21	212		T22	75		T23	50
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1027510	1			T22	105		T23	12		T24	64
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1195802	1			T22	112		T23	28		T24	82
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	428051	1			T23	2		T27	1163		T30	21
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1020143	1			T22	96		T24	89		T25	110
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	3814050	1			T21	219		T22	203		T23	40
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3027698	1			T21	229		T22	71		T23	7
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1029011	1			T22	129		T24	52		T25	106
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1190714	1			T22	88		T23	126		T24	67
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	430316	1			T23	37		T27	1208		T30	27
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1021063	1			T22	72		T23	19		T24	60
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	3813683	1			T21	227		T22	176		T23	136
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3024185	1			T21	221		T22	78		T23	28
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1030495	1			T22	90		T23	15		T24	78
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1195184	1			T22	112		T23	44		T24	61
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	429572	1			T23	5		T27	1285		T30	19
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1019733	1			T22	107		T23	1		T24	90
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	3822476	1			T21	221		T22	199		T23	79
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3022393	1			T21	227		T22	71		T23	20
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1034749	1			T22	94		T23	4		T24	74
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1185317	1			T22	96		T23	96		T24	33
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	427011	1			T23	18		T27	1154		T30	17
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1020906	1			T22	103		T23	12		T24	74
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	3822398	1			T21	213		T22	179		T23	119
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3019247	1			T21	235		T22	71		T23	30
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1024865	1			T22	122		T23	16		T24	72
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1196424	1			T22	109		T23	48		T24	71
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	431589	1			T23	14		T27	1113		T30	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1018329	1			T22	82		T23	2		T24	96
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	3812074	1			T21	199		T22	167		T23	141
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3039000	1			T21	249		T22	83		T23	23
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1028959	1			T22	129		T23	13		T24	56
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1190861	1			T22	76		T23	44		T24	70
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	425665	1			T23	8		T27	1238		T30	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1016293	1			T22	108		T24	109		T25	127
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	3824021	1			T21	271		T22	174		T23	139
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3016954	1			T21	177		T22	75		T23	21
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1027196	1			T22	86		T23	2		T24	97
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1196151	1			T22	138		T23	49		T24	60
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	429904	1			T23	12		T27	1307		T30	20
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1018626	1			T22	90		T23	6		T24	56
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	3814149	1			T21	253		T22	209		T23	61
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3023056	1			T21	195		T22	75		T23	24
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1027064	1			T22	68		T23	5		T24	66
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1197793	1			T22	119		T23	105		T24	66
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	427716	1			T23	26		T27	1276		T30	10
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1023074	1			T22	92		T23	8		T24	82
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	3823627	1			T21	263		T22	177		T23	62
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3023061	1			T21	185		T22	71		T23	17
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1026566	1			T22	92		T23	3		T24	66
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1194209	1			T22	123		T23	110		T24	41
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	428258	1			T23	27		T27	1321		T30	8
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1017131	1			T22	100		T23	10		T24	86
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	3816666	1			T21	221		T22	158		T23	110
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3031515	1			T21	227		T22	76		T23	26
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1027656	1			T22	106		T23	12		T24	44
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1190873	1			T22	109		T23	65		T24	86
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	425941	1			T23	12		T27	1112		T30	26
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1020201	1			T22	114		T23	4		T24	89
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	3805799	1			T21	224		T22	175		T23	99
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3036791	1			T21	224		T22	77		T23	23
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1031296	1			T22	88		T23	1		T24	74
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1192492	1			T22	103		T23	80		T24	58
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	427520	1			T23	13		T27	1271		T30	15
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1018954	1			T22	120		T23	13		T24	78
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	3814104	1			T21	237		T22	180		T23	67
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3025758	1			T21	211		T22	77		T23	24
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1028607	1			T22	66		T23	2		T24	56
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1196775	1			T22	138		T23	105		T24	87
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	427482	1			T23	18		T27	1158		T30	18
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1020126	1			T22	102		T23	13		T24	52
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	3814341	1			T21	206		T22	184		T23	78
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3034686	1			T21	242		T22	76		T23	8
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1027393	1			T22	139		T23	10		T24	64
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1194313	1			T22	82		T23	84		T24	76
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	427105	1			T23	36		T27	1332		T30	16
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1015014	1			T22	82		T23	13		T24	40
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	3825346	1			T21	206		T22	187		T23	161
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3028283	1			T21	242		T22	68		T23	44
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1022475	1			T22	112		T23	14		T24	64
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1196584	1			T22	104		T23	10		T24	78
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	426590	1			T27	1277		T30	8		T31	8835
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1013574	1			T22	92		T24	69		T25	114
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	3823367	1			T21	221		T22	173		T23	104
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3024865	1			T21	227		T22	77		T23	23
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1023401	1			T22	125		T23	8		T24	56
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1196288	1			T22	72		T23	69		T24	68
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	428936	1			T23	21		T27	1314		T30	15
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1015995	1			T22	116		T23	4		T24	76
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	3820622	1			T21	246		T22	181		T23	108
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3022842	1			T21	202		T22	75		T23	29
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1022019	1			T22	92		T23	13		T24	61
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1201776	1			T22	114		T23	60		T24	80
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	430363	1			T23	15		T27	1298		T30	20
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1015230	1			T22	101		T23	4		T24	68
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	3819072	1			T21	218		T22	187		T23	121
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3024261	1			T21	230		T22	83		T23	22
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1022839	1			T22	89		T23	12		T24	65
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1201081	1			T22	116		T23	51		T24	72
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	429141	1			T23	19		T27	1231		T30	24
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1016458	1			T22	88		T23	4		T24	76
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	3816886	1			T21	209		T22	167		T23	105
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3032676	1			T21	239		T22	75		T23	28
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1022758	1			T22	102		T23	21		T24	86
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1195014	1			T22	105		T23	49		T24	78
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	427654	1			T23	15		T27	1203		T30	11
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1017864	1			T22	114		T23	11		T24	54
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	3826789	1			T21	218		T22	187		T23	128
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3022315	1			T21	230		T22	71		T23	27
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1026089	1			T22	125		T23	12		T24	62
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1194321	1			T22	96		T23	50		T24	70
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	427972	1			T23	12		T27	1378		T30	18
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1015366	1			T22	84		T24	86		T25	98
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	3821552	1			T21	254		T22	175		T23	101
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3025309	1			T21	194		T22	65		T23	31
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1024018	1			T22	123		T23	12		T24	68
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1199347	1			T22	102		T23	62		T24	82
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	427716	1			T23	16		T27	1225		T30	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1014910	1			T22	98		T23	7		T24	57
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	3815772	1			T21	205		T22	184		T23	120
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3028329	1			T21	243		T22	68		T23	24
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1025556	1			T22	111		T23	8		T24	87
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1194824	1			T22	98		T23	53		T24	74
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	431118	1			T23	19		T27	1273		T30	21
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1017253	1			T22	102		T23	5		T24	58
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	3810770	1			T21	197		T22	192		T23	99
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3034766	1			T21	251		T22	72		T23	20
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1022294	1			T22	104		T23	14		T24	80
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1199062	1			T22	106		T23	68		T24	62
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	431187	1			T23	20		T27	1301		T30	7
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1014773	1			T22	89		T23	8		T24	73
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	3817218	1			T21	215		T22	178		T23	120
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3031577	1			T21	233		T22	78		T23	34
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1025724	1			T22	104		T23	26		T24	78
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1192514	1			T22	110		T23	39		T24	66
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	429589	1			T23	8		T27	1224		T30	16
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1016230	1			T22	93		T23	2		T24	86
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	3828504	1			T21	271		T22	197		T23	117
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3021100	1			T21	177		T22	77		T23	29
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1026294	1			T22	97		T23	10		T24	73
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1195847	1			T22	124		T23	60		T24	88
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	428932	1			T23	9		T27	1199		T30	9
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1012175	1			T22	68		T23	4		T24	48
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	3817602	1			T21	215		T22	201		T23	107
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3034102	1			T21	233		T22	71		T23	33
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1023502	1			T22	76		T23	7		T24	62
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1196727	1			T22	126		T23	65		T24	72
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	426851	1			T23	11		T27	1226		T30	12
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1014068	1			T22	89		T23	6		T24	91
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	3817522	1			T21	206		T22	178		T23	149
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3031463	1			T21	242		T22	84		T23	32
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1027566	1			T22	89		T23	6		T24	82
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1195984	1			T22	96		T23	33		T24	64
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	425234	1			T23	8		T27	1278		T30	26
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1015083	1			T22	116		T23	1		T24	59
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	3816697	1			T21	277		T22	174		T23	119
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3030164	1			T21	171		T22	80		T23	29
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1024227	1			T22	130		T23	8		T24	66
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1199191	1			T22	81		T23	50		T24	73
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	429350	1			T23	17		T27	1272		T30	21
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1013223	1			T22	98		T23	6		T24	98
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	3816458	1			T21	243		T22	201		T23	127
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3029506	1			T21	205		T22	79		T23	30
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1025806	1			T22	111		T23	14		T24	63
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1197694	1			T22	86		T23	41		T24	94
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	430034	1			T23	12		T27	1315		T30	26
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1013354	1			T22	86		T23	5		T24	62

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal