Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[1]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[2]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[3]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[4]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[5]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[6]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[7]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[8]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[9]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[10]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[11]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[12]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[13]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[14]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[15]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[16]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[17]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[18]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[19]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[20]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[21]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[22]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[23]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[24]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[25]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[26]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[27]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[28]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[29]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[30]	10512852	1			T21	448		T22	563		T23	229
bins_for_gpio_bits[31]	10512852	1			T21	448		T22	563		T23	229

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193270728

1

T21

7312

T22

12505

T23

5797

auto[1]

143140536

1

T21

7024

T22

5511

T23

1531

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

193264814

1

T21

7312

T22

12498

T23

5789

auto[1]

143146450

1

T21

7024

T22

5518

T23

1539

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	5841940	1			T21	258		T22	331		T23	167
bins_for_gpio_bits[0]	auto[0]	auto[1]	184097	1			T22	28		T23	4		T24	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	184289	1			T22	28		T23	5		T24	16
bins_for_gpio_bits[0]	auto[1]	auto[1]	4302526	1			T21	190		T22	176		T23	53
bins_for_gpio_bits[1]	auto[0]	auto[0]	5852614	1			T21	232		T22	372		T23	170
bins_for_gpio_bits[1]	auto[0]	auto[1]	183072	1			T22	26		T23	5		T24	15
bins_for_gpio_bits[1]	auto[1]	auto[0]	183302	1			T22	27		T23	5		T24	15
bins_for_gpio_bits[1]	auto[1]	auto[1]	4293864	1			T21	216		T22	138		T23	49
bins_for_gpio_bits[2]	auto[0]	auto[0]	5860782	1			T21	241		T22	331		T23	183
bins_for_gpio_bits[2]	auto[0]	auto[1]	182723	1			T22	23		T23	4		T24	16
bins_for_gpio_bits[2]	auto[1]	auto[0]	182882	1			T22	23		T23	4		T24	16
bins_for_gpio_bits[2]	auto[1]	auto[1]	4286465	1			T21	207		T22	186		T23	38
bins_for_gpio_bits[3]	auto[0]	auto[0]	5866673	1			T21	190		T22	407		T23	185
bins_for_gpio_bits[3]	auto[0]	auto[1]	183185	1			T22	23		T24	20		T25	30
bins_for_gpio_bits[3]	auto[1]	auto[0]	183404	1			T22	23		T24	20		T25	30
bins_for_gpio_bits[3]	auto[1]	auto[1]	4279590	1			T21	258		T22	110		T23	44
bins_for_gpio_bits[4]	auto[0]	auto[0]	5853763	1			T21	236		T22	365		T23	177
bins_for_gpio_bits[4]	auto[0]	auto[1]	183572	1			T22	27		T24	23		T25	29
bins_for_gpio_bits[4]	auto[1]	auto[0]	183729	1			T22	27		T24	24		T25	29
bins_for_gpio_bits[4]	auto[1]	auto[1]	4291788	1			T21	212		T22	144		T23	52
bins_for_gpio_bits[5]	auto[0]	auto[0]	5850272	1			T21	219		T22	396		T23	161
bins_for_gpio_bits[5]	auto[0]	auto[1]	183310	1			T22	24		T23	5		T24	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	183503	1			T22	24		T23	5		T24	17
bins_for_gpio_bits[5]	auto[1]	auto[1]	4295767	1			T21	229		T22	119		T23	58
bins_for_gpio_bits[6]	auto[0]	auto[0]	5855275	1			T21	227		T22	351		T23	194
bins_for_gpio_bits[6]	auto[0]	auto[1]	183899	1			T22	26		T24	21		T25	35
bins_for_gpio_bits[6]	auto[1]	auto[0]	184087	1			T22	27		T23	1		T24	21
bins_for_gpio_bits[6]	auto[1]	auto[1]	4289591	1			T21	221		T22	159		T23	34
bins_for_gpio_bits[7]	auto[0]	auto[0]	5859111	1			T21	221		T22	364		T23	175
bins_for_gpio_bits[7]	auto[0]	auto[1]	183242	1			T22	24		T23	4		T24	15
bins_for_gpio_bits[7]	auto[1]	auto[0]	183431	1			T22	25		T23	4		T24	15
bins_for_gpio_bits[7]	auto[1]	auto[1]	4287068	1			T21	227		T22	150		T23	46
bins_for_gpio_bits[8]	auto[0]	auto[0]	5860691	1			T21	213		T22	385		T23	182
bins_for_gpio_bits[8]	auto[0]	auto[1]	182811	1			T22	25		T23	1		T24	21
bins_for_gpio_bits[8]	auto[1]	auto[0]	182996	1			T22	25		T23	1		T24	21
bins_for_gpio_bits[8]	auto[1]	auto[1]	4286354	1			T21	235		T22	128		T23	45
bins_for_gpio_bits[9]	auto[0]	auto[0]	5848460	1			T21	199		T22	343		T23	198
bins_for_gpio_bits[9]	auto[0]	auto[1]	183270	1			T22	29		T24	21		T25	26
bins_for_gpio_bits[9]	auto[1]	auto[0]	183434	1			T22	29		T24	22		T25	27
bins_for_gpio_bits[9]	auto[1]	auto[1]	4297688	1			T21	249		T22	162		T23	31
bins_for_gpio_bits[10]	auto[0]	auto[0]	5864320	1			T21	271		T22	372		T23	188
bins_for_gpio_bits[10]	auto[0]	auto[1]	182903	1			T22	26		T23	2		T24	14
bins_for_gpio_bits[10]	auto[1]	auto[0]	183048	1			T22	26		T23	2		T24	14
bins_for_gpio_bits[10]	auto[1]	auto[1]	4282581	1			T21	177		T22	139		T23	37
bins_for_gpio_bits[11]	auto[0]	auto[0]	5854995	1			T21	253		T22	372		T23	168
bins_for_gpio_bits[11]	auto[0]	auto[1]	183840	1			T22	24		T23	3		T24	21
bins_for_gpio_bits[11]	auto[1]	auto[0]	184011	1			T22	24		T23	3		T24	21
bins_for_gpio_bits[11]	auto[1]	auto[1]	4290006	1			T21	195		T22	143		T23	55
bins_for_gpio_bits[12]	auto[0]	auto[0]	5861659	1			T21	263		T22	367		T23	171
bins_for_gpio_bits[12]	auto[0]	auto[1]	182573	1			T22	25		T23	4		T24	17
bins_for_gpio_bits[12]	auto[1]	auto[0]	182743	1			T22	25		T23	4		T24	17
bins_for_gpio_bits[12]	auto[1]	auto[1]	4285877	1			T21	185		T22	146		T23	50
bins_for_gpio_bits[13]	auto[0]	auto[0]	5851576	1			T21	221		T22	346		T23	186
bins_for_gpio_bits[13]	auto[0]	auto[1]	183459	1			T22	27		T23	1		T24	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	183619	1			T22	27		T23	1		T24	15
bins_for_gpio_bits[13]	auto[1]	auto[1]	4294198	1			T21	227		T22	163		T23	41
bins_for_gpio_bits[14]	auto[0]	auto[0]	5845768	1			T21	224		T22	338		T23	176
bins_for_gpio_bits[14]	auto[0]	auto[1]	183608	1			T22	28		T23	4		T24	18
bins_for_gpio_bits[14]	auto[1]	auto[0]	183819	1			T22	28		T23	4		T24	18
bins_for_gpio_bits[14]	auto[1]	auto[1]	4299657	1			T21	224		T22	169		T23	45
bins_for_gpio_bits[15]	auto[0]	auto[0]	5855911	1			T21	237		T22	356		T23	171
bins_for_gpio_bits[15]	auto[0]	auto[1]	183382	1			T22	28		T23	3		T24	18
bins_for_gpio_bits[15]	auto[1]	auto[0]	183575	1			T22	28		T23	3		T24	18
bins_for_gpio_bits[15]	auto[1]	auto[1]	4289984	1			T21	211		T22	151		T23	52
bins_for_gpio_bits[16]	auto[0]	auto[0]	5853012	1			T21	206		T22	378		T23	167
bins_for_gpio_bits[16]	auto[0]	auto[1]	182827	1			T22	27		T23	4		T24	16
bins_for_gpio_bits[16]	auto[1]	auto[0]	183035	1			T22	27		T23	5		T24	16
bins_for_gpio_bits[16]	auto[1]	auto[1]	4293978	1			T21	242		T22	131		T23	53
bins_for_gpio_bits[17]	auto[0]	auto[0]	5861506	1			T21	206		T22	377		T23	185
bins_for_gpio_bits[17]	auto[0]	auto[1]	182719	1			T22	26		T24	18		T25	28
bins_for_gpio_bits[17]	auto[1]	auto[0]	182899	1			T22	26		T24	19		T25	28
bins_for_gpio_bits[17]	auto[1]	auto[1]	4285728	1			T21	242		T22	134		T23	44
bins_for_gpio_bits[18]	auto[0]	auto[0]	5859648	1			T21	221		T22	342		T23	179
bins_for_gpio_bits[18]	auto[0]	auto[1]	183223	1			T22	28		T23	2		T24	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	183408	1			T22	28		T23	2		T24	17
bins_for_gpio_bits[18]	auto[1]	auto[1]	4286573	1			T21	227		T22	165		T23	46
bins_for_gpio_bits[19]	auto[0]	auto[0]	5861574	1			T21	246		T22	363		T23	179
bins_for_gpio_bits[19]	auto[0]	auto[1]	182645	1			T22	23		T23	2		T24	18
bins_for_gpio_bits[19]	auto[1]	auto[0]	182843	1			T22	24		T23	2		T24	18
bins_for_gpio_bits[19]	auto[1]	auto[1]	4285790	1			T21	202		T22	153		T23	46
bins_for_gpio_bits[20]	auto[0]	auto[0]	5859349	1			T21	218		T22	367		T23	183
bins_for_gpio_bits[20]	auto[0]	auto[1]	183480	1			T22	25		T23	1		T24	18
bins_for_gpio_bits[20]	auto[1]	auto[0]	183643	1			T22	25		T23	1		T24	18
bins_for_gpio_bits[20]	auto[1]	auto[1]	4286380	1			T21	230		T22	146		T23	44
bins_for_gpio_bits[21]	auto[0]	auto[0]	5851542	1			T21	209		T22	344		T23	172
bins_for_gpio_bits[21]	auto[0]	auto[1]	182942	1			T22	30		T23	2		T24	18
bins_for_gpio_bits[21]	auto[1]	auto[0]	183116	1			T22	30		T23	3		T24	18
bins_for_gpio_bits[21]	auto[1]	auto[1]	4295252	1			T21	239		T22	159		T23	52
bins_for_gpio_bits[22]	auto[0]	auto[0]	5863929	1			T21	218		T22	385		T23	190
bins_for_gpio_bits[22]	auto[0]	auto[1]	183092	1			T22	23		T24	18		T25	26
bins_for_gpio_bits[22]	auto[1]	auto[0]	183270	1			T22	23		T24	18		T25	26
bins_for_gpio_bits[22]	auto[1]	auto[1]	4282561	1			T21	230		T22	132		T23	39
bins_for_gpio_bits[23]	auto[0]	auto[0]	5861477	1			T21	254		T22	375		T23	173
bins_for_gpio_bits[23]	auto[0]	auto[1]	183258	1			T22	25		T23	1		T24	16
bins_for_gpio_bits[23]	auto[1]	auto[0]	183440	1			T22	25		T23	2		T24	17
bins_for_gpio_bits[23]	auto[1]	auto[1]	4284677	1			T21	194		T22	138		T23	53
bins_for_gpio_bits[24]	auto[0]	auto[0]	5852926	1			T21	205		T22	365		T23	178
bins_for_gpio_bits[24]	auto[0]	auto[1]	183041	1			T22	28		T23	2		T24	23
bins_for_gpio_bits[24]	auto[1]	auto[0]	183226	1			T22	28		T23	3		T24	23
bins_for_gpio_bits[24]	auto[1]	auto[1]	4293659	1			T21	243		T22	142		T23	46
bins_for_gpio_bits[25]	auto[0]	auto[0]	5849206	1			T21	197		T22	379		T23	178
bins_for_gpio_bits[25]	auto[0]	auto[1]	182701	1			T22	22		T23	3		T24	19
bins_for_gpio_bits[25]	auto[1]	auto[0]	182920	1			T22	23		T23	3		T24	20
bins_for_gpio_bits[25]	auto[1]	auto[1]	4298025	1			T21	251		T22	139		T23	45
bins_for_gpio_bits[26]	auto[0]	auto[0]	5852027	1			T21	215		T22	364		T23	184
bins_for_gpio_bits[26]	auto[0]	auto[1]	183202	1			T22	27		T23	1		T24	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	183429	1			T22	28		T23	1		T24	19
bins_for_gpio_bits[26]	auto[1]	auto[1]	4294194	1			T21	233		T22	144		T23	43
bins_for_gpio_bits[27]	auto[0]	auto[0]	5867370	1			T21	271		T22	399		T23	185
bins_for_gpio_bits[27]	auto[0]	auto[1]	183077	1			T22	19		T23	2		T24	18
bins_for_gpio_bits[27]	auto[1]	auto[0]	183275	1			T22	19		T23	2		T24	18
bins_for_gpio_bits[27]	auto[1]	auto[1]	4279130	1			T21	177		T22	126		T23	40
bins_for_gpio_bits[28]	auto[0]	auto[0]	5854428	1			T21	215		T22	377		T23	176
bins_for_gpio_bits[28]	auto[0]	auto[1]	183205	1			T22	25		T23	3		T24	19
bins_for_gpio_bits[28]	auto[1]	auto[0]	183403	1			T22	26		T23	3		T24	20
bins_for_gpio_bits[28]	auto[1]	auto[1]	4291816	1			T21	233		T22	135		T23	47
bins_for_gpio_bits[29]	auto[0]	auto[0]	5857417	1			T21	206		T22	334		T23	187
bins_for_gpio_bits[29]	auto[0]	auto[1]	183478	1			T22	29		T24	17		T25	26
bins_for_gpio_bits[29]	auto[1]	auto[0]	183655	1			T22	29		T23	1		T24	18
bins_for_gpio_bits[29]	auto[1]	auto[1]	4288302	1			T21	242		T22	171		T23	41
bins_for_gpio_bits[30]	auto[0]	auto[0]	5856649	1			T21	277		T22	359		T23	175
bins_for_gpio_bits[30]	auto[0]	auto[1]	183303	1			T22	26		T23	2		T24	25
bins_for_gpio_bits[30]	auto[1]	auto[0]	183466	1			T22	26		T23	2		T24	25
bins_for_gpio_bits[30]	auto[1]	auto[1]	4289434	1			T21	171		T22	152		T23	50
bins_for_gpio_bits[31]	auto[0]	auto[0]	5856898	1			T21	243		T22	373		T23	179
bins_for_gpio_bits[31]	auto[0]	auto[1]	182907	1			T22	25		T23	2		T24	17
bins_for_gpio_bits[31]	auto[1]	auto[0]	183060	1			T22	25		T23	3		T24	17
bins_for_gpio_bits[31]	auto[1]	auto[1]	4289987	1			T21	205		T22	140		T23	45