Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6369376 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
4252347 |
1 |
|
|
T26 |
533 |
|
T27 |
39636 |
|
T31 |
25675 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1862399 |
1 |
|
|
T26 |
247 |
|
T27 |
16519 |
|
T31 |
10919 |
| auto[1] |
auto[0] |
auto[1] |
270285 |
1 |
|
|
T26 |
63 |
|
T27 |
2348 |
|
T31 |
1798 |
| auto[1] |
auto[1] |
auto[0] |
1851063 |
1 |
|
|
T26 |
181 |
|
T27 |
18151 |
|
T31 |
11120 |
| auto[1] |
auto[1] |
auto[1] |
268600 |
1 |
|
|
T26 |
42 |
|
T27 |
2618 |
|
T31 |
1838 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |