Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6333360 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
4288363 |
1 |
|
|
T26 |
478 |
|
T27 |
37392 |
|
T31 |
26741 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8791042 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
1830681 |
1 |
|
|
T26 |
259 |
|
T27 |
15826 |
|
T31 |
14824 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6346235 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
4275488 |
1 |
|
|
T26 |
535 |
|
T27 |
41697 |
|
T31 |
25822 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1213544 |
1 |
|
|
T26 |
185 |
|
T27 |
14140 |
|
T31 |
5635 |
| auto[1] |
auto[0] |
auto[1] |
912835 |
1 |
|
|
T26 |
159 |
|
T27 |
8314 |
|
T31 |
7543 |
| auto[1] |
auto[1] |
auto[0] |
1231263 |
1 |
|
|
T26 |
91 |
|
T27 |
11731 |
|
T31 |
5363 |
| auto[1] |
auto[1] |
auto[1] |
917846 |
1 |
|
|
T26 |
100 |
|
T27 |
7512 |
|
T31 |
7281 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |