Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6362121 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
4259602 |
1 |
|
|
T26 |
337 |
|
T27 |
36693 |
|
T31 |
26475 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8796143 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
1825580 |
1 |
|
|
T26 |
310 |
|
T27 |
15767 |
|
T31 |
14989 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6348790 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
4272933 |
1 |
|
|
T26 |
645 |
|
T27 |
40256 |
|
T31 |
25782 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1225866 |
1 |
|
|
T26 |
219 |
|
T27 |
13054 |
|
T31 |
5237 |
| auto[1] |
auto[0] |
auto[1] |
916068 |
1 |
|
|
T26 |
192 |
|
T27 |
8406 |
|
T31 |
7300 |
| auto[1] |
auto[1] |
auto[0] |
1221487 |
1 |
|
|
T26 |
116 |
|
T27 |
11435 |
|
T31 |
5556 |
| auto[1] |
auto[1] |
auto[1] |
909512 |
1 |
|
|
T26 |
118 |
|
T27 |
7361 |
|
T31 |
7689 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |