Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6353186 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
4268537 |
1 |
|
|
T26 |
393 |
|
T27 |
39967 |
|
T31 |
25582 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8788795 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
1832928 |
1 |
|
|
T26 |
243 |
|
T27 |
14949 |
|
T31 |
14483 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6339085 |
1 |
|
|
T21 |
448 |
|
T22 |
355 |
|
T23 |
123 |
| auto[1] |
4282638 |
1 |
|
|
T26 |
510 |
|
T27 |
40151 |
|
T31 |
25078 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1238471 |
1 |
|
|
T26 |
170 |
|
T27 |
12352 |
|
T31 |
5144 |
| auto[1] |
auto[0] |
auto[1] |
923971 |
1 |
|
|
T26 |
155 |
|
T27 |
7205 |
|
T31 |
7415 |
| auto[1] |
auto[1] |
auto[0] |
1211239 |
1 |
|
|
T26 |
97 |
|
T27 |
12850 |
|
T31 |
5451 |
| auto[1] |
auto[1] |
auto[1] |
908957 |
1 |
|
|
T26 |
88 |
|
T27 |
7744 |
|
T31 |
7068 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |