Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 937
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T768 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1517842323 Jun 26 04:51:23 PM PDT 24 Jun 26 04:51:25 PM PDT 24 26015045 ps
T91 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1164575778 Jun 26 04:51:11 PM PDT 24 Jun 26 04:51:14 PM PDT 24 13019442 ps
T769 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2902059368 Jun 26 04:51:23 PM PDT 24 Jun 26 04:51:27 PM PDT 24 237912124 ps
T770 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1504944083 Jun 26 04:51:35 PM PDT 24 Jun 26 04:51:40 PM PDT 24 13947440 ps
T92 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1486921649 Jun 26 04:51:06 PM PDT 24 Jun 26 04:51:08 PM PDT 24 49729859 ps
T771 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.209575705 Jun 26 04:51:08 PM PDT 24 Jun 26 04:51:10 PM PDT 24 60780562 ps
T772 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3900966991 Jun 26 04:51:13 PM PDT 24 Jun 26 04:51:16 PM PDT 24 47476841 ps
T773 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3961956181 Jun 26 04:51:14 PM PDT 24 Jun 26 04:51:17 PM PDT 24 89933637 ps
T774 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.872899885 Jun 26 04:51:29 PM PDT 24 Jun 26 04:51:40 PM PDT 24 23101047 ps
T775 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3209742762 Jun 26 04:51:09 PM PDT 24 Jun 26 04:51:12 PM PDT 24 55019648 ps
T103 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.360314288 Jun 26 04:51:18 PM PDT 24 Jun 26 04:51:20 PM PDT 24 65099414 ps
T50 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.275426825 Jun 26 04:51:20 PM PDT 24 Jun 26 04:51:23 PM PDT 24 270618476 ps
T776 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4115607712 Jun 26 04:51:18 PM PDT 24 Jun 26 04:51:20 PM PDT 24 42278687 ps
T777 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1991651175 Jun 26 04:51:20 PM PDT 24 Jun 26 04:51:22 PM PDT 24 38809673 ps
T104 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.743211177 Jun 26 04:51:26 PM PDT 24 Jun 26 04:51:28 PM PDT 24 43326775 ps
T778 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1305597395 Jun 26 04:51:29 PM PDT 24 Jun 26 04:51:33 PM PDT 24 563145285 ps
T51 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.541205449 Jun 26 04:51:31 PM PDT 24 Jun 26 04:51:35 PM PDT 24 487339086 ps
T779 /workspace/coverage/cover_reg_top/1.gpio_intr_test.784196556 Jun 26 04:51:11 PM PDT 24 Jun 26 04:51:14 PM PDT 24 12630591 ps
T52 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2537390146 Jun 26 04:51:32 PM PDT 24 Jun 26 04:51:37 PM PDT 24 108156700 ps
T780 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2082219830 Jun 26 04:51:34 PM PDT 24 Jun 26 04:51:42 PM PDT 24 489017825 ps
T781 /workspace/coverage/cover_reg_top/7.gpio_intr_test.375776100 Jun 26 04:51:29 PM PDT 24 Jun 26 04:51:31 PM PDT 24 40381191 ps
T782 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1471250042 Jun 26 04:51:23 PM PDT 24 Jun 26 04:51:26 PM PDT 24 68960601 ps
T783 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2815330004 Jun 26 04:51:30 PM PDT 24 Jun 26 04:51:32 PM PDT 24 12019314 ps
T784 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1192849990 Jun 26 04:51:26 PM PDT 24 Jun 26 04:51:29 PM PDT 24 38247774 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.527174682 Jun 26 04:51:11 PM PDT 24 Jun 26 04:51:14 PM PDT 24 34925399 ps
T105 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.156834834 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:21 PM PDT 24 64037925 ps
T786 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.202415668 Jun 26 04:51:15 PM PDT 24 Jun 26 04:51:17 PM PDT 24 90121825 ps
T787 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2222200859 Jun 26 04:51:09 PM PDT 24 Jun 26 04:51:12 PM PDT 24 91439262 ps
T106 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.133086934 Jun 26 04:51:30 PM PDT 24 Jun 26 04:51:34 PM PDT 24 67377289 ps
T788 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2944488044 Jun 26 04:51:31 PM PDT 24 Jun 26 04:51:35 PM PDT 24 13511023 ps
T93 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1276025649 Jun 26 04:51:11 PM PDT 24 Jun 26 04:51:15 PM PDT 24 296947272 ps
T789 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2242485360 Jun 26 04:51:12 PM PDT 24 Jun 26 04:51:15 PM PDT 24 16014980 ps
T97 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1556241667 Jun 26 04:51:09 PM PDT 24 Jun 26 04:51:12 PM PDT 24 13956588 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.651662517 Jun 26 04:51:12 PM PDT 24 Jun 26 04:51:16 PM PDT 24 111314030 ps
T791 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2845323428 Jun 26 04:51:36 PM PDT 24 Jun 26 04:51:41 PM PDT 24 107358489 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.914268968 Jun 26 04:51:31 PM PDT 24 Jun 26 04:51:35 PM PDT 24 553113164 ps
T793 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3515497082 Jun 26 04:51:07 PM PDT 24 Jun 26 04:51:09 PM PDT 24 129103883 ps
T107 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.579011093 Jun 26 04:51:33 PM PDT 24 Jun 26 04:51:38 PM PDT 24 29293264 ps
T794 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3446972954 Jun 26 04:51:23 PM PDT 24 Jun 26 04:51:25 PM PDT 24 261930844 ps
T795 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2119930252 Jun 26 04:51:09 PM PDT 24 Jun 26 04:51:13 PM PDT 24 209293597 ps
T796 /workspace/coverage/cover_reg_top/28.gpio_intr_test.76250626 Jun 26 04:51:36 PM PDT 24 Jun 26 04:51:41 PM PDT 24 12188995 ps
T797 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1019687811 Jun 26 04:51:24 PM PDT 24 Jun 26 04:51:26 PM PDT 24 95463946 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.958881732 Jun 26 04:51:09 PM PDT 24 Jun 26 04:51:11 PM PDT 24 20037903 ps
T798 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1341422730 Jun 26 04:51:02 PM PDT 24 Jun 26 04:51:06 PM PDT 24 18198159 ps
T799 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1816383771 Jun 26 04:51:18 PM PDT 24 Jun 26 04:51:21 PM PDT 24 40909863 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.923210559 Jun 26 04:51:33 PM PDT 24 Jun 26 04:51:40 PM PDT 24 170555936 ps
T801 /workspace/coverage/cover_reg_top/23.gpio_intr_test.109672536 Jun 26 04:51:29 PM PDT 24 Jun 26 04:51:31 PM PDT 24 43094110 ps
T802 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3677080666 Jun 26 04:51:18 PM PDT 24 Jun 26 04:51:20 PM PDT 24 24933844 ps
T803 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1985924560 Jun 26 04:51:32 PM PDT 24 Jun 26 04:51:35 PM PDT 24 141974444 ps
T804 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.977859214 Jun 26 04:51:18 PM PDT 24 Jun 26 04:51:20 PM PDT 24 168077939 ps
T805 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1846159396 Jun 26 04:51:32 PM PDT 24 Jun 26 04:51:37 PM PDT 24 21529303 ps
T806 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.179926785 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:22 PM PDT 24 44544618 ps
T807 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4203356371 Jun 26 04:51:12 PM PDT 24 Jun 26 04:51:15 PM PDT 24 75361857 ps
T808 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3342330506 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:22 PM PDT 24 92594171 ps
T809 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2682735530 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:22 PM PDT 24 289255688 ps
T810 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1105891306 Jun 26 04:51:11 PM PDT 24 Jun 26 04:51:14 PM PDT 24 163649038 ps
T53 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2284215739 Jun 26 04:51:18 PM PDT 24 Jun 26 04:51:20 PM PDT 24 215610135 ps
T811 /workspace/coverage/cover_reg_top/32.gpio_intr_test.541474818 Jun 26 04:51:32 PM PDT 24 Jun 26 04:51:35 PM PDT 24 205213042 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.102948358 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:22 PM PDT 24 63940301 ps
T813 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2693310644 Jun 26 04:51:25 PM PDT 24 Jun 26 04:51:27 PM PDT 24 146099737 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1588033818 Jun 26 04:51:03 PM PDT 24 Jun 26 04:51:06 PM PDT 24 15298823 ps
T95 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2139081792 Jun 26 04:51:08 PM PDT 24 Jun 26 04:51:11 PM PDT 24 679841167 ps
T815 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1017575504 Jun 26 04:51:28 PM PDT 24 Jun 26 04:51:31 PM PDT 24 23988466 ps
T816 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3592979274 Jun 26 04:51:33 PM PDT 24 Jun 26 04:51:38 PM PDT 24 33726314 ps
T817 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2689041227 Jun 26 04:51:31 PM PDT 24 Jun 26 04:51:35 PM PDT 24 19801509 ps
T818 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4002032356 Jun 26 04:51:32 PM PDT 24 Jun 26 04:51:37 PM PDT 24 17017906 ps
T819 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3856892741 Jun 26 04:51:29 PM PDT 24 Jun 26 04:51:32 PM PDT 24 25811855 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2768735791 Jun 26 04:51:09 PM PDT 24 Jun 26 04:51:11 PM PDT 24 268275350 ps
T821 /workspace/coverage/cover_reg_top/34.gpio_intr_test.164709957 Jun 26 04:51:30 PM PDT 24 Jun 26 04:51:33 PM PDT 24 57047178 ps
T822 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1912267260 Jun 26 04:51:26 PM PDT 24 Jun 26 04:51:30 PM PDT 24 96672159 ps
T823 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2024414235 Jun 26 04:51:34 PM PDT 24 Jun 26 04:51:40 PM PDT 24 27465015 ps
T824 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3494767635 Jun 26 04:51:30 PM PDT 24 Jun 26 04:51:33 PM PDT 24 39074785 ps
T96 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3909831860 Jun 26 04:51:11 PM PDT 24 Jun 26 04:51:14 PM PDT 24 38959741 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3857414419 Jun 26 04:51:08 PM PDT 24 Jun 26 04:51:10 PM PDT 24 15802515 ps
T98 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1159526306 Jun 26 04:51:08 PM PDT 24 Jun 26 04:51:10 PM PDT 24 53702210 ps
T826 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.759945282 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:23 PM PDT 24 35260858 ps
T827 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3380290449 Jun 26 04:51:26 PM PDT 24 Jun 26 04:51:29 PM PDT 24 118064531 ps
T828 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1221605618 Jun 26 04:51:34 PM PDT 24 Jun 26 04:51:39 PM PDT 24 20122363 ps
T829 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1130397876 Jun 26 04:51:25 PM PDT 24 Jun 26 04:51:27 PM PDT 24 95681483 ps
T830 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2137515081 Jun 26 04:51:26 PM PDT 24 Jun 26 04:51:28 PM PDT 24 168313308 ps
T831 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2884569086 Jun 26 04:51:31 PM PDT 24 Jun 26 04:51:35 PM PDT 24 36286614 ps
T832 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3693235573 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:22 PM PDT 24 78394118 ps
T833 /workspace/coverage/cover_reg_top/0.gpio_intr_test.628586547 Jun 26 04:51:09 PM PDT 24 Jun 26 04:51:12 PM PDT 24 41424848 ps
T834 /workspace/coverage/cover_reg_top/9.gpio_intr_test.4056904035 Jun 26 04:51:20 PM PDT 24 Jun 26 04:51:28 PM PDT 24 57600738 ps
T835 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2255645530 Jun 26 04:51:19 PM PDT 24 Jun 26 04:51:24 PM PDT 24 199901100 ps
T836 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3474978572 Jun 26 04:51:18 PM PDT 24 Jun 26 04:51:20 PM PDT 24 145706330 ps
T837 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.872800679 Jun 26 04:51:32 PM PDT 24 Jun 26 04:51:37 PM PDT 24 81454122 ps
T838 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.718656037 Jun 26 04:35:16 PM PDT 24 Jun 26 04:35:21 PM PDT 24 152047612 ps
T839 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2417253712 Jun 26 04:35:20 PM PDT 24 Jun 26 04:35:26 PM PDT 24 146310900 ps
T840 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3005424365 Jun 26 04:35:04 PM PDT 24 Jun 26 04:35:07 PM PDT 24 64558057 ps
T841 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4057924049 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:15 PM PDT 24 90382282 ps
T842 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2718320641 Jun 26 04:35:20 PM PDT 24 Jun 26 04:35:27 PM PDT 24 54608678 ps
T843 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1281856432 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:15 PM PDT 24 37855109 ps
T844 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1787596140 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:28 PM PDT 24 98645721 ps
T845 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1772409975 Jun 26 04:35:08 PM PDT 24 Jun 26 04:35:10 PM PDT 24 34991553 ps
T846 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3889388847 Jun 26 04:34:58 PM PDT 24 Jun 26 04:35:03 PM PDT 24 30150197 ps
T847 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.122825336 Jun 26 04:35:10 PM PDT 24 Jun 26 04:35:13 PM PDT 24 104209464 ps
T848 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807303327 Jun 26 04:35:11 PM PDT 24 Jun 26 04:35:14 PM PDT 24 149432637 ps
T849 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.267949116 Jun 26 04:35:26 PM PDT 24 Jun 26 04:35:33 PM PDT 24 77928719 ps
T850 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.616293240 Jun 26 04:35:26 PM PDT 24 Jun 26 04:35:33 PM PDT 24 54574030 ps
T851 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1173192681 Jun 26 04:34:53 PM PDT 24 Jun 26 04:34:58 PM PDT 24 782824511 ps
T852 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3933630058 Jun 26 04:35:11 PM PDT 24 Jun 26 04:35:15 PM PDT 24 43998229 ps
T853 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.895933305 Jun 26 04:35:01 PM PDT 24 Jun 26 04:35:05 PM PDT 24 272782688 ps
T854 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2244963593 Jun 26 04:34:53 PM PDT 24 Jun 26 04:34:58 PM PDT 24 160976269 ps
T855 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2690259851 Jun 26 04:35:22 PM PDT 24 Jun 26 04:35:29 PM PDT 24 680666323 ps
T856 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3243488378 Jun 26 04:35:08 PM PDT 24 Jun 26 04:35:11 PM PDT 24 49526255 ps
T857 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3841481092 Jun 26 04:35:22 PM PDT 24 Jun 26 04:35:30 PM PDT 24 174354166 ps
T858 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1058015147 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:15 PM PDT 24 70112800 ps
T859 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1838426992 Jun 26 04:35:05 PM PDT 24 Jun 26 04:35:08 PM PDT 24 40481473 ps
T860 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3983283982 Jun 26 04:35:21 PM PDT 24 Jun 26 04:35:28 PM PDT 24 35166784 ps
T861 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2765828087 Jun 26 04:35:05 PM PDT 24 Jun 26 04:35:09 PM PDT 24 48790247 ps
T862 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.131817481 Jun 26 04:35:15 PM PDT 24 Jun 26 04:35:19 PM PDT 24 105952274 ps
T863 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3032009276 Jun 26 04:35:09 PM PDT 24 Jun 26 04:35:11 PM PDT 24 144859809 ps
T864 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926383821 Jun 26 04:35:15 PM PDT 24 Jun 26 04:35:19 PM PDT 24 82429648 ps
T865 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.872477007 Jun 26 04:34:53 PM PDT 24 Jun 26 04:34:58 PM PDT 24 265936356 ps
T866 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.908489933 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:25 PM PDT 24 357265814 ps
T867 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1378110940 Jun 26 04:35:21 PM PDT 24 Jun 26 04:35:28 PM PDT 24 121876730 ps
T868 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.463029480 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:15 PM PDT 24 205301412 ps
T869 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4256907674 Jun 26 04:35:26 PM PDT 24 Jun 26 04:35:33 PM PDT 24 500329073 ps
T870 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1494296928 Jun 26 04:35:13 PM PDT 24 Jun 26 04:35:17 PM PDT 24 34049340 ps
T871 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.495961652 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:31 PM PDT 24 69821214 ps
T872 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1767202562 Jun 26 04:34:51 PM PDT 24 Jun 26 04:34:56 PM PDT 24 534641718 ps
T873 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2327923574 Jun 26 04:35:07 PM PDT 24 Jun 26 04:35:10 PM PDT 24 52828997 ps
T874 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.729562755 Jun 26 04:35:03 PM PDT 24 Jun 26 04:35:06 PM PDT 24 45481569 ps
T875 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2291837499 Jun 26 04:35:43 PM PDT 24 Jun 26 04:35:49 PM PDT 24 101417911 ps
T876 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2010395725 Jun 26 04:34:55 PM PDT 24 Jun 26 04:35:01 PM PDT 24 126966005 ps
T877 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.522770302 Jun 26 04:35:24 PM PDT 24 Jun 26 04:35:32 PM PDT 24 96157210 ps
T878 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.685078216 Jun 26 04:34:51 PM PDT 24 Jun 26 04:34:56 PM PDT 24 40763051 ps
T879 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39159688 Jun 26 04:35:20 PM PDT 24 Jun 26 04:35:26 PM PDT 24 35245208 ps
T880 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3530931148 Jun 26 04:35:11 PM PDT 24 Jun 26 04:35:14 PM PDT 24 147702946 ps
T881 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3409940628 Jun 26 04:35:07 PM PDT 24 Jun 26 04:35:09 PM PDT 24 249734775 ps
T882 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2460939074 Jun 26 04:35:05 PM PDT 24 Jun 26 04:35:08 PM PDT 24 41886424 ps
T883 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2942195674 Jun 26 04:34:57 PM PDT 24 Jun 26 04:35:03 PM PDT 24 86531449 ps
T884 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3139769776 Jun 26 04:34:52 PM PDT 24 Jun 26 04:34:57 PM PDT 24 90935904 ps
T885 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.677407024 Jun 26 04:35:10 PM PDT 24 Jun 26 04:35:12 PM PDT 24 36823966 ps
T886 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2410558873 Jun 26 04:35:15 PM PDT 24 Jun 26 04:35:20 PM PDT 24 1161525259 ps
T887 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2930196172 Jun 26 04:34:54 PM PDT 24 Jun 26 04:34:59 PM PDT 24 546806293 ps
T888 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2279161166 Jun 26 04:34:52 PM PDT 24 Jun 26 04:34:57 PM PDT 24 52175928 ps
T889 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2743712683 Jun 26 04:35:09 PM PDT 24 Jun 26 04:35:11 PM PDT 24 94063180 ps
T890 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.643413618 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:23 PM PDT 24 35185752 ps
T891 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861847676 Jun 26 04:35:02 PM PDT 24 Jun 26 04:35:05 PM PDT 24 66198618 ps
T892 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3903712337 Jun 26 04:34:51 PM PDT 24 Jun 26 04:34:55 PM PDT 24 191624183 ps
T893 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2013477861 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:23 PM PDT 24 33536697 ps
T894 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990672143 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:24 PM PDT 24 39593964 ps
T895 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4069101589 Jun 26 04:34:53 PM PDT 24 Jun 26 04:34:59 PM PDT 24 109550253 ps
T896 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3156140499 Jun 26 04:35:04 PM PDT 24 Jun 26 04:35:07 PM PDT 24 78206088 ps
T897 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1550403870 Jun 26 04:34:59 PM PDT 24 Jun 26 04:35:04 PM PDT 24 24445288 ps
T898 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3193989578 Jun 26 04:35:16 PM PDT 24 Jun 26 04:35:20 PM PDT 24 345075242 ps
T899 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.852730950 Jun 26 04:35:16 PM PDT 24 Jun 26 04:35:20 PM PDT 24 37581086 ps
T900 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1667726698 Jun 26 04:35:02 PM PDT 24 Jun 26 04:35:05 PM PDT 24 398270841 ps
T901 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3044427220 Jun 26 04:36:07 PM PDT 24 Jun 26 04:36:12 PM PDT 24 64808718 ps
T902 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4081086206 Jun 26 04:35:19 PM PDT 24 Jun 26 04:35:24 PM PDT 24 38105732 ps
T903 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4207681433 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:25 PM PDT 24 218209386 ps
T904 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4280115071 Jun 26 04:35:15 PM PDT 24 Jun 26 04:35:19 PM PDT 24 67096090 ps
T905 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2840329261 Jun 26 04:35:23 PM PDT 24 Jun 26 04:35:31 PM PDT 24 190467703 ps
T906 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2412735082 Jun 26 04:34:57 PM PDT 24 Jun 26 04:35:03 PM PDT 24 614788957 ps
T907 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.414518845 Jun 26 04:35:10 PM PDT 24 Jun 26 04:35:13 PM PDT 24 84917166 ps
T908 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4187086017 Jun 26 04:34:52 PM PDT 24 Jun 26 04:34:58 PM PDT 24 50052276 ps
T909 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3272862516 Jun 26 04:35:06 PM PDT 24 Jun 26 04:35:09 PM PDT 24 54446284 ps
T910 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2726614474 Jun 26 04:34:52 PM PDT 24 Jun 26 04:34:57 PM PDT 24 65965275 ps
T911 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1763206993 Jun 26 04:35:06 PM PDT 24 Jun 26 04:35:08 PM PDT 24 33509472 ps
T912 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1060149504 Jun 26 04:35:08 PM PDT 24 Jun 26 04:35:10 PM PDT 24 61011259 ps
T913 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3300498942 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:23 PM PDT 24 85426527 ps
T914 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1016187685 Jun 26 04:35:12 PM PDT 24 Jun 26 04:35:15 PM PDT 24 65241160 ps
T915 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2230735933 Jun 26 04:35:20 PM PDT 24 Jun 26 04:35:26 PM PDT 24 417590370 ps
T916 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1190154322 Jun 26 04:34:54 PM PDT 24 Jun 26 04:35:00 PM PDT 24 146889122 ps
T917 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1535252851 Jun 26 04:35:07 PM PDT 24 Jun 26 04:35:09 PM PDT 24 39415660 ps
T918 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.480003949 Jun 26 04:35:02 PM PDT 24 Jun 26 04:35:06 PM PDT 24 104543097 ps
T919 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2063793832 Jun 26 04:34:57 PM PDT 24 Jun 26 04:35:03 PM PDT 24 38209104 ps
T920 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1438679790 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:24 PM PDT 24 66804323 ps
T921 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1975062098 Jun 26 04:35:13 PM PDT 24 Jun 26 04:35:16 PM PDT 24 65581275 ps
T922 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.820897413 Jun 26 04:34:54 PM PDT 24 Jun 26 04:35:00 PM PDT 24 205220935 ps
T923 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3363888613 Jun 26 04:35:11 PM PDT 24 Jun 26 04:35:14 PM PDT 24 187474888 ps
T924 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3499107827 Jun 26 04:35:33 PM PDT 24 Jun 26 04:35:40 PM PDT 24 89299801 ps
T925 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2936543872 Jun 26 04:35:15 PM PDT 24 Jun 26 04:35:19 PM PDT 24 105757156 ps
T926 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.758528690 Jun 26 04:34:57 PM PDT 24 Jun 26 04:35:03 PM PDT 24 47728698 ps
T927 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2683972090 Jun 26 04:35:13 PM PDT 24 Jun 26 04:35:17 PM PDT 24 66449646 ps
T928 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1073453878 Jun 26 04:34:55 PM PDT 24 Jun 26 04:35:01 PM PDT 24 192095092 ps
T929 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1626902684 Jun 26 04:35:18 PM PDT 24 Jun 26 04:35:25 PM PDT 24 290267675 ps
T930 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3205140440 Jun 26 04:34:52 PM PDT 24 Jun 26 04:34:58 PM PDT 24 79281782 ps
T931 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.419057623 Jun 26 04:35:20 PM PDT 24 Jun 26 04:35:26 PM PDT 24 245505324 ps
T932 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1288656343 Jun 26 04:36:13 PM PDT 24 Jun 26 04:36:17 PM PDT 24 330723756 ps
T933 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006876319 Jun 26 04:34:56 PM PDT 24 Jun 26 04:35:01 PM PDT 24 78437003 ps
T934 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.444186119 Jun 26 04:34:55 PM PDT 24 Jun 26 04:35:01 PM PDT 24 43635140 ps
T935 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2517970181 Jun 26 04:35:11 PM PDT 24 Jun 26 04:35:13 PM PDT 24 54168537 ps
T936 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2784301887 Jun 26 04:34:53 PM PDT 24 Jun 26 04:34:59 PM PDT 24 122637041 ps
T937 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1749901233 Jun 26 04:35:17 PM PDT 24 Jun 26 04:35:23 PM PDT 24 67278312 ps

Test location /workspace/coverage/default/30.gpio_stress_all.3053417324
Short name T27
Test name
Test status
Simulation time 42598675444 ps
CPU time 151.98 seconds
Started Jun 26 04:52:22 PM PDT 24
Finished Jun 26 04:54:56 PM PDT 24
Peak memory 198792 kb
Host smart-04ad8693-b323-4cc6-895f-67b00015c21c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053417324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3053417324
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.23955060
Short name T21
Test name
Test status
Simulation time 63941322 ps
CPU time 1.34 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 196904 kb
Host smart-137119bd-9ec0-491e-a41c-da8050864a4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23955060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 37.gpio_intr_with_filter_rand_intr_event.23955060
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1257902824
Short name T36
Test name
Test status
Simulation time 13308438257 ps
CPU time 360.79 seconds
Started Jun 26 04:52:03 PM PDT 24
Finished Jun 26 04:58:05 PM PDT 24
Peak memory 198832 kb
Host smart-6e875035-942f-4f2b-8d62-ad4942dfa683
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1257902824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1257902824
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.330006178
Short name T41
Test name
Test status
Simulation time 110879491 ps
CPU time 0.89 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:38 PM PDT 24
Peak memory 214196 kb
Host smart-e3c22a3f-68b4-4a08-bd60-c466991b1b7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330006178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.330006178
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.977388270
Short name T83
Test name
Test status
Simulation time 181731942 ps
CPU time 0.84 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 196652 kb
Host smart-6c389cbe-8dc4-44fb-a103-8d94d2acf29c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977388270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.977388270
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3543124895
Short name T2
Test name
Test status
Simulation time 5440626895 ps
CPU time 60.33 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:53:00 PM PDT 24
Peak memory 198768 kb
Host smart-8a220a6c-7638-41ef-85e9-9949820e6c96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543124895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3543124895
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.402674998
Short name T40
Test name
Test status
Simulation time 182879457 ps
CPU time 1.47 seconds
Started Jun 26 04:51:12 PM PDT 24
Finished Jun 26 04:51:16 PM PDT 24
Peak memory 198584 kb
Host smart-12b3bf59-2dbb-49ad-91f8-99a510b1d45e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402674998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.402674998
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3574797830
Short name T209
Test name
Test status
Simulation time 41921964 ps
CPU time 0.54 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:36 PM PDT 24
Peak memory 194548 kb
Host smart-1632d063-7141-448f-b4e2-9f3f956d2370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574797830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3574797830
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3663765859
Short name T100
Test name
Test status
Simulation time 29371546 ps
CPU time 0.75 seconds
Started Jun 26 04:51:08 PM PDT 24
Finished Jun 26 04:51:10 PM PDT 24
Peak memory 196644 kb
Host smart-38467226-f8e3-4657-a260-8f216bf6e12a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663765859 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3663765859
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.541205449
Short name T51
Test name
Test status
Simulation time 487339086 ps
CPU time 1.4 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 198620 kb
Host smart-f5ce45fe-fa89-4969-a4c4-493f977b8c91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541205449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.541205449
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2537390146
Short name T52
Test name
Test status
Simulation time 108156700 ps
CPU time 1.13 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 198636 kb
Host smart-4977723e-e44f-4ec2-be74-14450a5ae51f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537390146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2537390146
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2870678288
Short name T760
Test name
Test status
Simulation time 28484637 ps
CPU time 0.67 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:11 PM PDT 24
Peak memory 195276 kb
Host smart-315c6523-8c3b-4551-9114-dab2238c8c28
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870678288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2870678288
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2380196189
Short name T89
Test name
Test status
Simulation time 504656845 ps
CPU time 2.52 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:13 PM PDT 24
Peak memory 197572 kb
Host smart-6d6f62b1-ba95-4d7e-bcf0-b50704cb80ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380196189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2380196189
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1588033818
Short name T814
Test name
Test status
Simulation time 15298823 ps
CPU time 0.62 seconds
Started Jun 26 04:51:03 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 196020 kb
Host smart-82a93081-afab-4e7c-a8d9-ff37abbfddde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588033818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1588033818
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1223961516
Short name T725
Test name
Test status
Simulation time 32767970 ps
CPU time 0.71 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 197348 kb
Host smart-50d9cf68-df65-48c8-b7da-82a5b1df25d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223961516 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1223961516
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1880814712
Short name T79
Test name
Test status
Simulation time 11530209 ps
CPU time 0.64 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:02 PM PDT 24
Peak memory 196048 kb
Host smart-b61141a6-0b48-4a95-8e51-1dece5c3def0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880814712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1880814712
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.628586547
Short name T833
Test name
Test status
Simulation time 41424848 ps
CPU time 0.59 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:12 PM PDT 24
Peak memory 195044 kb
Host smart-a01e5d32-a8aa-4b24-961c-a3811cdf607a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628586547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.628586547
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1341422730
Short name T798
Test name
Test status
Simulation time 18198159 ps
CPU time 0.81 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 197608 kb
Host smart-72bc9369-a164-4b4c-b671-d317dde28165
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341422730 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1341422730
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1811720589
Short name T740
Test name
Test status
Simulation time 143080327 ps
CPU time 1.99 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 198736 kb
Host smart-51002036-450b-437b-8181-35130525a5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811720589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1811720589
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1492317882
Short name T118
Test name
Test status
Simulation time 1064079047 ps
CPU time 1.08 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:05 PM PDT 24
Peak memory 198700 kb
Host smart-235d3c0a-5279-4ad3-81fb-3d4e482c30ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492317882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1492317882
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.209575705
Short name T771
Test name
Test status
Simulation time 60780562 ps
CPU time 0.66 seconds
Started Jun 26 04:51:08 PM PDT 24
Finished Jun 26 04:51:10 PM PDT 24
Peak memory 196048 kb
Host smart-a9238686-de6a-4c76-b5a6-d6a96381eac7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209575705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.209575705
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2139081792
Short name T95
Test name
Test status
Simulation time 679841167 ps
CPU time 2.42 seconds
Started Jun 26 04:51:08 PM PDT 24
Finished Jun 26 04:51:11 PM PDT 24
Peak memory 197764 kb
Host smart-9436a11d-e78b-4b84-8f9a-64a167154003
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139081792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2139081792
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3287576778
Short name T87
Test name
Test status
Simulation time 40284030 ps
CPU time 0.59 seconds
Started Jun 26 04:51:13 PM PDT 24
Finished Jun 26 04:51:16 PM PDT 24
Peak memory 195048 kb
Host smart-14c24607-a065-4034-b877-d3a8a67779d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287576778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3287576778
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4203356371
Short name T807
Test name
Test status
Simulation time 75361857 ps
CPU time 1.02 seconds
Started Jun 26 04:51:12 PM PDT 24
Finished Jun 26 04:51:15 PM PDT 24
Peak memory 198608 kb
Host smart-28fc1a0c-acfb-4719-abef-8fa462b960cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203356371 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4203356371
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.958881732
Short name T94
Test name
Test status
Simulation time 20037903 ps
CPU time 0.6 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:11 PM PDT 24
Peak memory 195948 kb
Host smart-92f7e07f-d512-4175-988b-1f3d7f7f397c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958881732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.958881732
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.784196556
Short name T779
Test name
Test status
Simulation time 12630591 ps
CPU time 0.61 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 195052 kb
Host smart-d98dafc1-8d90-4ae9-9380-0e071ec8e1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784196556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.784196556
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3857414419
Short name T825
Test name
Test status
Simulation time 15802515 ps
CPU time 0.74 seconds
Started Jun 26 04:51:08 PM PDT 24
Finished Jun 26 04:51:10 PM PDT 24
Peak memory 196440 kb
Host smart-75cc910f-b22d-4dda-a923-02632e3598be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857414419 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3857414419
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.952266614
Short name T742
Test name
Test status
Simulation time 44358475 ps
CPU time 1.13 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:13 PM PDT 24
Peak memory 198480 kb
Host smart-6ae96481-bbab-40e6-9fdc-7ae3ba1ab1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952266614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.952266614
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1510412091
Short name T49
Test name
Test status
Simulation time 142073481 ps
CPU time 0.87 seconds
Started Jun 26 04:51:12 PM PDT 24
Finished Jun 26 04:51:16 PM PDT 24
Peak memory 197516 kb
Host smart-3b3d9271-56af-4f7d-9e3c-4addd209b473
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510412091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1510412091
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1673825577
Short name T721
Test name
Test status
Simulation time 52121984 ps
CPU time 0.85 seconds
Started Jun 26 04:51:23 PM PDT 24
Finished Jun 26 04:51:26 PM PDT 24
Peak memory 198504 kb
Host smart-85ab3f42-36b5-4f18-a1fd-212093f13cdb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673825577 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1673825577
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1846159396
Short name T805
Test name
Test status
Simulation time 21529303 ps
CPU time 0.61 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 195852 kb
Host smart-fd05aab0-a02c-41f9-a887-3fc328cbcc7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846159396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1846159396
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1171874946
Short name T722
Test name
Test status
Simulation time 12893017 ps
CPU time 0.6 seconds
Started Jun 26 04:51:23 PM PDT 24
Finished Jun 26 04:51:25 PM PDT 24
Peak memory 194428 kb
Host smart-ecf86d1a-3e5c-42ea-a26a-11f1b49ee8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171874946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1171874946
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1985924560
Short name T803
Test name
Test status
Simulation time 141974444 ps
CPU time 0.9 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 198448 kb
Host smart-4ab92c31-0069-47af-9d04-b8b849421bf1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985924560 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1985924560
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3031871566
Short name T724
Test name
Test status
Simulation time 99046240 ps
CPU time 2.7 seconds
Started Jun 26 04:51:14 PM PDT 24
Finished Jun 26 04:51:18 PM PDT 24
Peak memory 198620 kb
Host smart-11a072cf-78c6-493c-af20-0e20ee032813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031871566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3031871566
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1004610066
Short name T746
Test name
Test status
Simulation time 279596185 ps
CPU time 0.89 seconds
Started Jun 26 04:51:21 PM PDT 24
Finished Jun 26 04:51:23 PM PDT 24
Peak memory 197856 kb
Host smart-08d0ff3f-85f3-4b71-8940-e2cfe523e169
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004610066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1004610066
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.600089140
Short name T745
Test name
Test status
Simulation time 35846525 ps
CPU time 0.67 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:19 PM PDT 24
Peak memory 197508 kb
Host smart-b530dac5-4650-4048-a1de-6d3ae1fadd77
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600089140 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.600089140
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2583550128
Short name T117
Test name
Test status
Simulation time 16731465 ps
CPU time 0.6 seconds
Started Jun 26 04:51:23 PM PDT 24
Finished Jun 26 04:51:25 PM PDT 24
Peak memory 195276 kb
Host smart-df190b8c-508a-4553-8968-d84965b0606d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583550128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2583550128
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3469165987
Short name T741
Test name
Test status
Simulation time 23051171 ps
CPU time 0.58 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:21 PM PDT 24
Peak memory 195032 kb
Host smart-bfe74d8c-3b91-4133-ad3e-ce750df1d39b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469165987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3469165987
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.360314288
Short name T103
Test name
Test status
Simulation time 65099414 ps
CPU time 0.66 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:20 PM PDT 24
Peak memory 195236 kb
Host smart-bd8a6a4d-4d63-4007-9ef1-3b2a44e4b6e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360314288 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.360314288
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2255645530
Short name T835
Test name
Test status
Simulation time 199901100 ps
CPU time 3.44 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:24 PM PDT 24
Peak memory 198704 kb
Host smart-0c82be6e-7d9a-4c3c-8a84-c2c486aa7158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255645530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2255645530
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3495854970
Short name T765
Test name
Test status
Simulation time 480243495 ps
CPU time 0.89 seconds
Started Jun 26 04:51:20 PM PDT 24
Finished Jun 26 04:51:23 PM PDT 24
Peak memory 197768 kb
Host smart-332bb20c-2b7a-40fc-9de4-198c10d74453
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495854970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3495854970
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.102948358
Short name T812
Test name
Test status
Simulation time 63940301 ps
CPU time 1.61 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:22 PM PDT 24
Peak memory 198708 kb
Host smart-fa9da3c8-78fd-4faf-b337-76d39f5255e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102948358 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.102948358
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4115607712
Short name T776
Test name
Test status
Simulation time 42278687 ps
CPU time 0.6 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:20 PM PDT 24
Peak memory 195404 kb
Host smart-6025897c-cb3f-48fa-82a2-eb38ca932600
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115607712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4115607712
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1816383771
Short name T799
Test name
Test status
Simulation time 40909863 ps
CPU time 0.58 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:21 PM PDT 24
Peak memory 195028 kb
Host smart-d1d983e1-a93f-4da9-b3d8-66b0976d08fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816383771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1816383771
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.499952419
Short name T102
Test name
Test status
Simulation time 17352212 ps
CPU time 0.67 seconds
Started Jun 26 04:51:16 PM PDT 24
Finished Jun 26 04:51:18 PM PDT 24
Peak memory 195140 kb
Host smart-93f018a6-d147-4082-9582-70e51f22c614
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499952419 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.499952419
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1471250042
Short name T782
Test name
Test status
Simulation time 68960601 ps
CPU time 1.66 seconds
Started Jun 26 04:51:23 PM PDT 24
Finished Jun 26 04:51:26 PM PDT 24
Peak memory 198628 kb
Host smart-d3b088b7-a958-449a-8aa8-f5b7ca0746cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471250042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1471250042
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3991105757
Short name T48
Test name
Test status
Simulation time 187233356 ps
CPU time 1.18 seconds
Started Jun 26 04:51:20 PM PDT 24
Finished Jun 26 04:51:23 PM PDT 24
Peak memory 198600 kb
Host smart-85597f5f-3c8a-481d-a78a-94a8a1ebf71d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991105757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3991105757
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.914268968
Short name T792
Test name
Test status
Simulation time 553113164 ps
CPU time 0.96 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 198536 kb
Host smart-60de4367-f879-41e7-8903-24f4714fdb14
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914268968 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.914268968
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.933137276
Short name T757
Test name
Test status
Simulation time 16285179 ps
CPU time 0.61 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:20 PM PDT 24
Peak memory 195592 kb
Host smart-b280624d-e6f6-4cb4-823f-b798834198b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933137276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.933137276
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2098675898
Short name T718
Test name
Test status
Simulation time 11585817 ps
CPU time 0.57 seconds
Started Jun 26 04:51:25 PM PDT 24
Finished Jun 26 04:51:27 PM PDT 24
Peak memory 194964 kb
Host smart-d666d72b-9e05-4883-90a6-fbb1b9d22afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098675898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2098675898
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.872800679
Short name T837
Test name
Test status
Simulation time 81454122 ps
CPU time 0.72 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 196492 kb
Host smart-d0233bc3-9cc9-483e-a961-a299ebf15e65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872800679 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.872800679
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.923210559
Short name T800
Test name
Test status
Simulation time 170555936 ps
CPU time 3.02 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 198640 kb
Host smart-10daab94-9eb8-4e18-bc76-33263c7dc44f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923210559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.923210559
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3693235573
Short name T832
Test name
Test status
Simulation time 78394118 ps
CPU time 1.21 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:22 PM PDT 24
Peak memory 198724 kb
Host smart-b62378ec-a608-44a4-8484-1f62ba8cd8d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693235573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3693235573
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.872899885
Short name T774
Test name
Test status
Simulation time 23101047 ps
CPU time 0.66 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 198156 kb
Host smart-8f8e6101-ca24-4dda-b917-5679c1f35f87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872899885 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.872899885
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4206739081
Short name T90
Test name
Test status
Simulation time 49348401 ps
CPU time 0.62 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:34 PM PDT 24
Peak memory 195092 kb
Host smart-f6c7b5d1-3fe8-4246-9db3-9c5aa47223c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206739081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4206739081
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3062211936
Short name T747
Test name
Test status
Simulation time 25708042 ps
CPU time 0.61 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 194492 kb
Host smart-400b00f0-5ab6-4afc-a16c-0432bcec422f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062211936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3062211936
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.133086934
Short name T106
Test name
Test status
Simulation time 67377289 ps
CPU time 0.79 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:34 PM PDT 24
Peak memory 196648 kb
Host smart-de85403e-4736-41d9-980e-32b0215fd185
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133086934 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.133086934
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.3341820356
Short name T739
Test name
Test status
Simulation time 139458311 ps
CPU time 1.05 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 198488 kb
Host smart-1d80e7f6-1e04-4f2a-bb74-75db1229846e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341820356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.3341820356
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2693310644
Short name T813
Test name
Test status
Simulation time 146099737 ps
CPU time 0.84 seconds
Started Jun 26 04:51:25 PM PDT 24
Finished Jun 26 04:51:27 PM PDT 24
Peak memory 197784 kb
Host smart-36a122ff-afbb-4e26-b042-4171345af424
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693310644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2693310644
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3380290449
Short name T827
Test name
Test status
Simulation time 118064531 ps
CPU time 0.85 seconds
Started Jun 26 04:51:26 PM PDT 24
Finished Jun 26 04:51:29 PM PDT 24
Peak memory 198548 kb
Host smart-3518d7d9-f49e-44ab-a1d7-dc662b4a139e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380290449 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3380290449
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2017053500
Short name T116
Test name
Test status
Simulation time 22263320 ps
CPU time 0.59 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 195520 kb
Host smart-73124f06-dbec-4ae9-9796-d68f37071c55
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017053500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2017053500
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2556079076
Short name T723
Test name
Test status
Simulation time 16640509 ps
CPU time 0.6 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:51:55 PM PDT 24
Peak memory 195056 kb
Host smart-d0565978-d01a-4523-a5be-3b40f793e279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556079076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2556079076
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2884569086
Short name T831
Test name
Test status
Simulation time 36286614 ps
CPU time 0.63 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 196104 kb
Host smart-df2a2e4e-7a0d-4685-9b42-cf40b648faca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884569086 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2884569086
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2915503584
Short name T730
Test name
Test status
Simulation time 393419693 ps
CPU time 2.32 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 198688 kb
Host smart-2eb1a367-ac83-4227-819e-20b738e15de6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915503584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2915503584
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2137515081
Short name T830
Test name
Test status
Simulation time 168313308 ps
CPU time 0.86 seconds
Started Jun 26 04:51:26 PM PDT 24
Finished Jun 26 04:51:28 PM PDT 24
Peak memory 198456 kb
Host smart-23db3a1a-c7bc-4151-9623-fbb182e1364a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137515081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2137515081
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1019687811
Short name T797
Test name
Test status
Simulation time 95463946 ps
CPU time 0.83 seconds
Started Jun 26 04:51:24 PM PDT 24
Finished Jun 26 04:51:26 PM PDT 24
Peak memory 198584 kb
Host smart-4af0ed58-99cd-4e79-8432-08290e88d92f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019687811 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1019687811
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1869610672
Short name T86
Test name
Test status
Simulation time 21756070 ps
CPU time 0.61 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:34 PM PDT 24
Peak memory 196128 kb
Host smart-4f5f25e7-7d0b-4f84-95fb-cdb4951c4177
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869610672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1869610672
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2944488044
Short name T788
Test name
Test status
Simulation time 13511023 ps
CPU time 0.61 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 195028 kb
Host smart-0767b1f9-87b0-437d-99de-7803452ad204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944488044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2944488044
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2969614195
Short name T82
Test name
Test status
Simulation time 107362701 ps
CPU time 0.74 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:36 PM PDT 24
Peak memory 196696 kb
Host smart-480e77ab-551e-4aa3-ba18-191a78c1a27b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969614195 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2969614195
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1213102415
Short name T726
Test name
Test status
Simulation time 383688089 ps
CPU time 2.26 seconds
Started Jun 26 04:51:35 PM PDT 24
Finished Jun 26 04:51:42 PM PDT 24
Peak memory 198680 kb
Host smart-a3cfc956-2ab1-4d37-86a7-7c6d3134ad7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213102415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1213102415
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4139153863
Short name T47
Test name
Test status
Simulation time 91415834 ps
CPU time 0.88 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:32 PM PDT 24
Peak memory 197876 kb
Host smart-dfaf8645-7823-43be-930f-0cc65efde42c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139153863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4139153863
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1130397876
Short name T829
Test name
Test status
Simulation time 95681483 ps
CPU time 1.22 seconds
Started Jun 26 04:51:25 PM PDT 24
Finished Jun 26 04:51:27 PM PDT 24
Peak memory 198688 kb
Host smart-5be04f5c-495d-4f0f-9002-80bdd19c89cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130397876 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1130397876
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2125319224
Short name T80
Test name
Test status
Simulation time 34474635 ps
CPU time 0.59 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 194056 kb
Host smart-b071f108-5159-4f05-8996-11453bbd06bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125319224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2125319224
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1221605618
Short name T828
Test name
Test status
Simulation time 20122363 ps
CPU time 0.58 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:39 PM PDT 24
Peak memory 194300 kb
Host smart-42e187cd-ce21-424c-ab4a-d7a834830629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221605618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1221605618
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2689041227
Short name T817
Test name
Test status
Simulation time 19801509 ps
CPU time 0.77 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 196692 kb
Host smart-4afc20b0-3d77-44db-9ca4-1d3b6dc76630
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689041227 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2689041227
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3282170611
Short name T719
Test name
Test status
Simulation time 419754925 ps
CPU time 2.88 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 198660 kb
Host smart-5ffa4b77-c446-424f-8bda-3b887b408411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282170611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3282170611
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2024414235
Short name T823
Test name
Test status
Simulation time 27465015 ps
CPU time 0.76 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 198348 kb
Host smart-47809a0d-7ba8-4116-956d-9c55667dbf24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024414235 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2024414235
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1192849990
Short name T784
Test name
Test status
Simulation time 38247774 ps
CPU time 0.62 seconds
Started Jun 26 04:51:26 PM PDT 24
Finished Jun 26 04:51:29 PM PDT 24
Peak memory 196012 kb
Host smart-72e2a21e-72fe-4a02-8d6d-96ebbf4a582b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192849990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1192849990
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3387037651
Short name T756
Test name
Test status
Simulation time 27681852 ps
CPU time 0.61 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:34 PM PDT 24
Peak memory 194272 kb
Host smart-1c1b21ff-c459-4e99-af6f-d41c40912ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387037651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3387037651
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.743211177
Short name T104
Test name
Test status
Simulation time 43326775 ps
CPU time 0.91 seconds
Started Jun 26 04:51:26 PM PDT 24
Finished Jun 26 04:51:28 PM PDT 24
Peak memory 197848 kb
Host smart-1fc3ce9e-5ae0-4221-8265-0341737bf4ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743211177 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.743211177
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2082219830
Short name T780
Test name
Test status
Simulation time 489017825 ps
CPU time 3.11 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:42 PM PDT 24
Peak memory 198696 kb
Host smart-5b0fbec6-15eb-4bc6-baa8-10d078aef048
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082219830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2082219830
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2845323428
Short name T791
Test name
Test status
Simulation time 107358489 ps
CPU time 0.9 seconds
Started Jun 26 04:51:36 PM PDT 24
Finished Jun 26 04:51:41 PM PDT 24
Peak memory 198500 kb
Host smart-03711053-74dd-46c6-8805-539c6bcf3f22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845323428 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2845323428
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2607132660
Short name T753
Test name
Test status
Simulation time 23085718 ps
CPU time 0.58 seconds
Started Jun 26 04:51:36 PM PDT 24
Finished Jun 26 04:51:41 PM PDT 24
Peak memory 195816 kb
Host smart-d44957cd-9d98-45c9-baee-716578774e30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607132660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2607132660
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.4240063218
Short name T749
Test name
Test status
Simulation time 201711194 ps
CPU time 0.61 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 195140 kb
Host smart-37985097-b2a1-41db-9d6f-13ffcc739211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240063218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.4240063218
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.579011093
Short name T107
Test name
Test status
Simulation time 29293264 ps
CPU time 0.82 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:38 PM PDT 24
Peak memory 197536 kb
Host smart-336b7ff1-d28a-4942-8b59-e8e76ba42f7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579011093 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.579011093
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1912267260
Short name T822
Test name
Test status
Simulation time 96672159 ps
CPU time 2.13 seconds
Started Jun 26 04:51:26 PM PDT 24
Finished Jun 26 04:51:30 PM PDT 24
Peak memory 198680 kb
Host smart-a8a7c80d-c2f2-4306-9b8f-7aba5f823bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912267260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1912267260
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4161588294
Short name T37
Test name
Test status
Simulation time 93743379 ps
CPU time 0.94 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:36 PM PDT 24
Peak memory 197816 kb
Host smart-93bbeda4-6d5d-4343-b437-125575e9c9a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161588294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.4161588294
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.527174682
Short name T785
Test name
Test status
Simulation time 34925399 ps
CPU time 1.36 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 197408 kb
Host smart-3bcda586-c47a-41e1-b927-55fa68463faa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527174682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.527174682
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3909831860
Short name T96
Test name
Test status
Simulation time 38959741 ps
CPU time 0.67 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 195644 kb
Host smart-c51a1f53-f5c7-4267-bf35-6530c2d04857
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909831860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3909831860
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.202415668
Short name T786
Test name
Test status
Simulation time 90121825 ps
CPU time 0.79 seconds
Started Jun 26 04:51:15 PM PDT 24
Finished Jun 26 04:51:17 PM PDT 24
Peak memory 198516 kb
Host smart-a3a11ee3-7014-4774-9db1-4154e0c99dd3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202415668 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.202415668
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1164575778
Short name T91
Test name
Test status
Simulation time 13019442 ps
CPU time 0.65 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 195440 kb
Host smart-d5cabe34-b340-4a81-8698-66f0b31aab41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164575778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1164575778
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1888775094
Short name T764
Test name
Test status
Simulation time 39483966 ps
CPU time 0.6 seconds
Started Jun 26 04:51:08 PM PDT 24
Finished Jun 26 04:51:09 PM PDT 24
Peak memory 194368 kb
Host smart-40e0d9bf-a627-46e4-af4f-55b3411f8321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888775094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1888775094
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.158829330
Short name T101
Test name
Test status
Simulation time 17459293 ps
CPU time 0.67 seconds
Started Jun 26 04:51:10 PM PDT 24
Finished Jun 26 04:51:12 PM PDT 24
Peak memory 196188 kb
Host smart-3640e425-0b96-47eb-b923-2988c45ad4ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158829330 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.158829330
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.739229012
Short name T762
Test name
Test status
Simulation time 31534770 ps
CPU time 1.75 seconds
Started Jun 26 04:51:10 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 198688 kb
Host smart-c2cf8e99-1903-4f1a-8db1-334640e45a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739229012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.739229012
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3515497082
Short name T793
Test name
Test status
Simulation time 129103883 ps
CPU time 0.84 seconds
Started Jun 26 04:51:07 PM PDT 24
Finished Jun 26 04:51:09 PM PDT 24
Peak memory 197876 kb
Host smart-126aab14-55e3-42f6-a20f-6a93f5016dfd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515497082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3515497082
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2815330004
Short name T783
Test name
Test status
Simulation time 12019314 ps
CPU time 0.56 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:32 PM PDT 24
Peak memory 194380 kb
Host smart-396134c1-8401-4c4b-b5bd-0bd605540566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815330004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2815330004
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2848979402
Short name T717
Test name
Test status
Simulation time 15227017 ps
CPU time 0.61 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 194384 kb
Host smart-a59d5fb6-861d-4031-8c34-e66b28a73c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848979402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2848979402
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2130051366
Short name T729
Test name
Test status
Simulation time 41680848 ps
CPU time 0.58 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 194372 kb
Host smart-8b3cc277-d60c-402e-9f93-b458a7809eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130051366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2130051366
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.109672536
Short name T801
Test name
Test status
Simulation time 43094110 ps
CPU time 0.6 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 195024 kb
Host smart-aee177e4-302a-45cd-af7a-a010b000a81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109672536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.109672536
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3856892741
Short name T819
Test name
Test status
Simulation time 25811855 ps
CPU time 0.61 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:32 PM PDT 24
Peak memory 195080 kb
Host smart-5a761db5-cf8d-441b-b477-ea4b7e1a4dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856892741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3856892741
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.49371539
Short name T728
Test name
Test status
Simulation time 104489155 ps
CPU time 0.57 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:39 PM PDT 24
Peak memory 194396 kb
Host smart-464f0c0e-37e4-46d9-b6db-00e1c4d91eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49371539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.49371539
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.716059250
Short name T733
Test name
Test status
Simulation time 14736696 ps
CPU time 0.58 seconds
Started Jun 26 04:51:26 PM PDT 24
Finished Jun 26 04:51:29 PM PDT 24
Peak memory 194336 kb
Host smart-1eb70eb3-7705-4b08-b89e-809b616107a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716059250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.716059250
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.705136532
Short name T755
Test name
Test status
Simulation time 19681832 ps
CPU time 0.61 seconds
Started Jun 26 04:51:25 PM PDT 24
Finished Jun 26 04:51:27 PM PDT 24
Peak memory 194424 kb
Host smart-4e296e7b-58d0-45ff-bcd7-43ab1e4e5ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705136532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.705136532
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.76250626
Short name T796
Test name
Test status
Simulation time 12188995 ps
CPU time 0.57 seconds
Started Jun 26 04:51:36 PM PDT 24
Finished Jun 26 04:51:41 PM PDT 24
Peak memory 194296 kb
Host smart-5b8c7200-33b2-4daf-b342-e5c89b440595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76250626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.76250626
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4164989012
Short name T720
Test name
Test status
Simulation time 66494581 ps
CPU time 0.61 seconds
Started Jun 26 04:51:27 PM PDT 24
Finished Jun 26 04:51:29 PM PDT 24
Peak memory 194476 kb
Host smart-6719538b-15d1-4294-af71-7d7be0f8d647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164989012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4164989012
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.651662517
Short name T790
Test name
Test status
Simulation time 111314030 ps
CPU time 0.79 seconds
Started Jun 26 04:51:12 PM PDT 24
Finished Jun 26 04:51:16 PM PDT 24
Peak memory 196340 kb
Host smart-55d43505-b35f-4b04-a0e3-065572f27e60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651662517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.651662517
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1276025649
Short name T93
Test name
Test status
Simulation time 296947272 ps
CPU time 1.39 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:15 PM PDT 24
Peak memory 197316 kb
Host smart-315ab354-e3c6-452d-91d8-c941241bae67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276025649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1276025649
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3596382923
Short name T78
Test name
Test status
Simulation time 89567056 ps
CPU time 0.65 seconds
Started Jun 26 04:51:13 PM PDT 24
Finished Jun 26 04:51:16 PM PDT 24
Peak memory 195524 kb
Host smart-5c03a6f2-3787-4d7f-a895-2494868bd6c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596382923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3596382923
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3961956181
Short name T773
Test name
Test status
Simulation time 89933637 ps
CPU time 0.63 seconds
Started Jun 26 04:51:14 PM PDT 24
Finished Jun 26 04:51:17 PM PDT 24
Peak memory 197612 kb
Host smart-56bfbefb-23c5-4b27-8d0c-6f13eaf24369
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961956181 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3961956181
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.231205050
Short name T84
Test name
Test status
Simulation time 12721613 ps
CPU time 0.62 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:15 PM PDT 24
Peak memory 195496 kb
Host smart-d6e44bd5-eb93-4608-9512-42030fda99ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231205050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.231205050
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3900966991
Short name T772
Test name
Test status
Simulation time 47476841 ps
CPU time 0.63 seconds
Started Jun 26 04:51:13 PM PDT 24
Finished Jun 26 04:51:16 PM PDT 24
Peak memory 194496 kb
Host smart-809cc3d2-e9b0-4d5f-b92f-44bdc6958a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900966991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3900966991
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3278050542
Short name T743
Test name
Test status
Simulation time 43539784 ps
CPU time 2.22 seconds
Started Jun 26 04:51:10 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 198712 kb
Host smart-e7e5e215-2027-4ee8-bfe1-cbe0976b9a00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278050542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3278050542
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2768735791
Short name T820
Test name
Test status
Simulation time 268275350 ps
CPU time 1.14 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:11 PM PDT 24
Peak memory 198704 kb
Host smart-01e0b014-4220-4ba5-b03a-13479f887ac6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768735791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2768735791
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3592979274
Short name T816
Test name
Test status
Simulation time 33726314 ps
CPU time 0.55 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:38 PM PDT 24
Peak memory 194940 kb
Host smart-bbb13068-9e22-4871-92f2-43b389702ef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592979274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3592979274
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.654159838
Short name T732
Test name
Test status
Simulation time 55588265 ps
CPU time 0.59 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:32 PM PDT 24
Peak memory 194372 kb
Host smart-5526ce38-61d1-44f3-9da6-752a39bfa00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654159838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.654159838
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.541474818
Short name T811
Test name
Test status
Simulation time 205213042 ps
CPU time 0.61 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 194384 kb
Host smart-1bcf7063-a40f-47ad-a57f-b95b642e3c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541474818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.541474818
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3494767635
Short name T824
Test name
Test status
Simulation time 39074785 ps
CPU time 0.6 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:33 PM PDT 24
Peak memory 195056 kb
Host smart-7ee237dd-2a0a-46eb-b997-ecbb61c24eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494767635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3494767635
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.164709957
Short name T821
Test name
Test status
Simulation time 57047178 ps
CPU time 0.63 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:33 PM PDT 24
Peak memory 194320 kb
Host smart-033a1539-24cb-4564-9326-9e9a91131475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164709957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.164709957
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.635575712
Short name T750
Test name
Test status
Simulation time 55873490 ps
CPU time 0.61 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:34 PM PDT 24
Peak memory 195100 kb
Host smart-29a868fa-6df6-43b1-b5ce-28e43dfec559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635575712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.635575712
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3956464340
Short name T752
Test name
Test status
Simulation time 14195596 ps
CPU time 0.63 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 194336 kb
Host smart-c1bfc04d-cd0a-429d-bfd1-db11f03b6558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956464340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3956464340
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4002032356
Short name T818
Test name
Test status
Simulation time 17017906 ps
CPU time 0.62 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 195040 kb
Host smart-5398dca4-d980-416d-8f50-93699421002c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002032356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4002032356
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2370548669
Short name T754
Test name
Test status
Simulation time 12634582 ps
CPU time 0.61 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 194412 kb
Host smart-0cba7bba-9cfd-4302-b9f9-d709cc496ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370548669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2370548669
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.777570424
Short name T731
Test name
Test status
Simulation time 41122259 ps
CPU time 0.57 seconds
Started Jun 26 04:51:26 PM PDT 24
Finished Jun 26 04:51:28 PM PDT 24
Peak memory 195036 kb
Host smart-3e996e9f-c1b9-4017-ba04-e0014d9c70a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777570424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.777570424
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1486921649
Short name T92
Test name
Test status
Simulation time 49729859 ps
CPU time 0.89 seconds
Started Jun 26 04:51:06 PM PDT 24
Finished Jun 26 04:51:08 PM PDT 24
Peak memory 197344 kb
Host smart-1e502f96-71b5-40dc-89a7-1316a597db2d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486921649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1486921649
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2731338265
Short name T763
Test name
Test status
Simulation time 473693338 ps
CPU time 1.59 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:13 PM PDT 24
Peak memory 198604 kb
Host smart-c76fae55-3d83-4219-bc2f-f950c793cf3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731338265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2731338265
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2392070662
Short name T88
Test name
Test status
Simulation time 28283933 ps
CPU time 0.68 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:15 PM PDT 24
Peak memory 195456 kb
Host smart-369e7062-7861-4716-83cb-5a3eabe0a8a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392070662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2392070662
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2222200859
Short name T787
Test name
Test status
Simulation time 91439262 ps
CPU time 0.87 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:12 PM PDT 24
Peak memory 198488 kb
Host smart-0b3be948-9f97-4083-ac0c-0adba7323e85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222200859 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2222200859
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2465258946
Short name T759
Test name
Test status
Simulation time 16794346 ps
CPU time 0.67 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 195224 kb
Host smart-83b327b5-a609-4b24-8b82-72b6622e798b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465258946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2465258946
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.248067700
Short name T735
Test name
Test status
Simulation time 30461471 ps
CPU time 0.57 seconds
Started Jun 26 04:51:08 PM PDT 24
Finished Jun 26 04:51:09 PM PDT 24
Peak memory 194392 kb
Host smart-8ee8fc6f-69b6-4861-8380-363946605220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248067700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.248067700
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1105891306
Short name T810
Test name
Test status
Simulation time 163649038 ps
CPU time 0.89 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 198492 kb
Host smart-25fca704-c0e8-4a69-8464-3889bc2c261e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105891306 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1105891306
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3209742762
Short name T775
Test name
Test status
Simulation time 55019648 ps
CPU time 1.35 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:12 PM PDT 24
Peak memory 198640 kb
Host smart-63686934-8e2c-41a2-9673-5ffaa837cfa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209742762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3209742762
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1007951741
Short name T738
Test name
Test status
Simulation time 32934868 ps
CPU time 0.63 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 194532 kb
Host smart-79b6fb4b-7522-4381-b88b-77b4e37cdaf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007951741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1007951741
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1972103249
Short name T736
Test name
Test status
Simulation time 17406166 ps
CPU time 0.58 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 194416 kb
Host smart-1543cd72-d553-40d8-a8db-ffeb4a7c2ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972103249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1972103249
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2184108188
Short name T766
Test name
Test status
Simulation time 34306664 ps
CPU time 0.58 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:33 PM PDT 24
Peak memory 195016 kb
Host smart-98834fa6-011f-4290-97eb-596376bfd70c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184108188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2184108188
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1504944083
Short name T770
Test name
Test status
Simulation time 13947440 ps
CPU time 0.65 seconds
Started Jun 26 04:51:35 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 194436 kb
Host smart-9d4f32df-8fa1-49dd-98af-208e06a8509f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504944083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1504944083
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1017575504
Short name T815
Test name
Test status
Simulation time 23988466 ps
CPU time 0.58 seconds
Started Jun 26 04:51:28 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 194648 kb
Host smart-c88cd541-ef43-4e43-928b-7277c9189be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017575504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1017575504
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2583843851
Short name T751
Test name
Test status
Simulation time 13624162 ps
CPU time 0.59 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 194384 kb
Host smart-faef740b-ca2b-4ba5-adca-68af92a5eed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583843851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2583843851
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1758960731
Short name T734
Test name
Test status
Simulation time 33110272 ps
CPU time 0.61 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 194376 kb
Host smart-30c442c0-fe59-420b-a95c-a4a7950c8eeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758960731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1758960731
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.54429528
Short name T767
Test name
Test status
Simulation time 26199065 ps
CPU time 0.58 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:39 PM PDT 24
Peak memory 194248 kb
Host smart-83f6b47d-c2fb-4acc-839d-a5a72499bb45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54429528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.54429528
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2568735102
Short name T727
Test name
Test status
Simulation time 15133323 ps
CPU time 0.6 seconds
Started Jun 26 04:51:30 PM PDT 24
Finished Jun 26 04:51:32 PM PDT 24
Peak memory 194968 kb
Host smart-9d0dfb40-0a89-4438-9898-4f8043df0bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568735102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2568735102
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1645981644
Short name T744
Test name
Test status
Simulation time 16853693 ps
CPU time 0.59 seconds
Started Jun 26 04:51:27 PM PDT 24
Finished Jun 26 04:51:30 PM PDT 24
Peak memory 195040 kb
Host smart-4a0d20a2-5a8e-4dbe-aaef-eccb41dc13c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645981644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1645981644
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.133447469
Short name T737
Test name
Test status
Simulation time 48003493 ps
CPU time 1.37 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:12 PM PDT 24
Peak memory 198688 kb
Host smart-99ea6ae4-c34e-48ad-824e-78d12eebfc2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133447469 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.133447469
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1556241667
Short name T97
Test name
Test status
Simulation time 13956588 ps
CPU time 0.61 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:12 PM PDT 24
Peak memory 195556 kb
Host smart-f15a85d6-d308-4a7b-9947-1a6a76023579
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556241667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1556241667
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2242485360
Short name T789
Test name
Test status
Simulation time 16014980 ps
CPU time 0.6 seconds
Started Jun 26 04:51:12 PM PDT 24
Finished Jun 26 04:51:15 PM PDT 24
Peak memory 194332 kb
Host smart-eb52c694-2785-488e-b532-1d08d4b2926f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242485360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2242485360
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2119930252
Short name T795
Test name
Test status
Simulation time 209293597 ps
CPU time 0.88 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:13 PM PDT 24
Peak memory 196912 kb
Host smart-15f0a904-80af-467d-bcc2-af1a77e603bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119930252 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2119930252
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.4101086662
Short name T758
Test name
Test status
Simulation time 213377915 ps
CPU time 3.12 seconds
Started Jun 26 04:51:12 PM PDT 24
Finished Jun 26 04:51:18 PM PDT 24
Peak memory 198616 kb
Host smart-1c2d5635-922b-43cd-8d7f-cd41974ab98c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101086662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.4101086662
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.891950350
Short name T38
Test name
Test status
Simulation time 151996113 ps
CPU time 0.88 seconds
Started Jun 26 04:51:11 PM PDT 24
Finished Jun 26 04:51:14 PM PDT 24
Peak memory 197520 kb
Host smart-c9847ece-5477-417d-8382-1259b63575ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891950350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.891950350
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3474978572
Short name T836
Test name
Test status
Simulation time 145706330 ps
CPU time 0.87 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:20 PM PDT 24
Peak memory 198604 kb
Host smart-5f602915-b9f9-45b6-92cb-56219deb85c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474978572 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3474978572
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1159526306
Short name T98
Test name
Test status
Simulation time 53702210 ps
CPU time 0.68 seconds
Started Jun 26 04:51:08 PM PDT 24
Finished Jun 26 04:51:10 PM PDT 24
Peak memory 195912 kb
Host smart-d6395746-e5b0-4665-9e09-f42198ac4954
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159526306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1159526306
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1991651175
Short name T777
Test name
Test status
Simulation time 38809673 ps
CPU time 0.6 seconds
Started Jun 26 04:51:20 PM PDT 24
Finished Jun 26 04:51:22 PM PDT 24
Peak memory 194996 kb
Host smart-536b0a42-fef1-47e2-b214-c0293ef291d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991651175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1991651175
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3342330506
Short name T808
Test name
Test status
Simulation time 92594171 ps
CPU time 0.8 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:22 PM PDT 24
Peak memory 196840 kb
Host smart-04cf55db-5b45-407e-b38d-87425f4af659
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342330506 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3342330506
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3677080666
Short name T802
Test name
Test status
Simulation time 24933844 ps
CPU time 1.19 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:20 PM PDT 24
Peak memory 198720 kb
Host smart-24d41132-4209-4c5c-bcea-edbb5fa2f635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677080666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3677080666
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.275426825
Short name T50
Test name
Test status
Simulation time 270618476 ps
CPU time 0.89 seconds
Started Jun 26 04:51:20 PM PDT 24
Finished Jun 26 04:51:23 PM PDT 24
Peak memory 197764 kb
Host smart-19771477-6538-4a6d-8e20-7b64b21aff83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275426825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.275426825
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.179926785
Short name T806
Test name
Test status
Simulation time 44544618 ps
CPU time 1.11 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:22 PM PDT 24
Peak memory 198692 kb
Host smart-caacc7b5-b3be-40ad-9ede-f3f858237ad5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179926785 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.179926785
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3292896326
Short name T81
Test name
Test status
Simulation time 14121067 ps
CPU time 0.63 seconds
Started Jun 26 04:51:17 PM PDT 24
Finished Jun 26 04:51:18 PM PDT 24
Peak memory 195284 kb
Host smart-2fff12df-6f0c-4b6a-8951-188dca79e8e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292896326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3292896326
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.375776100
Short name T781
Test name
Test status
Simulation time 40381191 ps
CPU time 0.61 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 195032 kb
Host smart-64ca1652-d151-4d0e-8378-3e08f72d26b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375776100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.375776100
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3174858764
Short name T99
Test name
Test status
Simulation time 131774769 ps
CPU time 0.8 seconds
Started Jun 26 04:51:22 PM PDT 24
Finished Jun 26 04:51:25 PM PDT 24
Peak memory 196916 kb
Host smart-7dca775b-b2d0-45a0-85a9-53ce5b058d3e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174858764 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3174858764
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1305597395
Short name T778
Test name
Test status
Simulation time 563145285 ps
CPU time 2.18 seconds
Started Jun 26 04:51:29 PM PDT 24
Finished Jun 26 04:51:33 PM PDT 24
Peak memory 198640 kb
Host smart-e465c0d9-ac8f-49d9-947c-f71edb57074a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305597395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1305597395
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.221646800
Short name T39
Test name
Test status
Simulation time 119087451 ps
CPU time 0.85 seconds
Started Jun 26 04:51:27 PM PDT 24
Finished Jun 26 04:51:30 PM PDT 24
Peak memory 197728 kb
Host smart-fe661c35-2417-4957-b985-15541025492a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221646800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.221646800
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1813352958
Short name T748
Test name
Test status
Simulation time 25684838 ps
CPU time 1.1 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:21 PM PDT 24
Peak memory 198756 kb
Host smart-fceb565b-3300-4361-92d1-9126a0a5fdaf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813352958 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1813352958
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1517842323
Short name T768
Test name
Test status
Simulation time 26015045 ps
CPU time 0.66 seconds
Started Jun 26 04:51:23 PM PDT 24
Finished Jun 26 04:51:25 PM PDT 24
Peak memory 195008 kb
Host smart-b1c1d84e-9840-47b0-9738-6d4456a9aee3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517842323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1517842323
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1951110838
Short name T761
Test name
Test status
Simulation time 30095430 ps
CPU time 0.61 seconds
Started Jun 26 04:51:17 PM PDT 24
Finished Jun 26 04:51:19 PM PDT 24
Peak memory 195040 kb
Host smart-63de0e8e-2acb-47af-8e0d-52e0e8f01908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951110838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1951110838
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.156834834
Short name T105
Test name
Test status
Simulation time 64037925 ps
CPU time 0.89 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:21 PM PDT 24
Peak memory 197596 kb
Host smart-6f317fc1-cdf3-46ed-bdbf-b3366f9e4ec3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156834834 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.156834834
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2902059368
Short name T769
Test name
Test status
Simulation time 237912124 ps
CPU time 2.33 seconds
Started Jun 26 04:51:23 PM PDT 24
Finished Jun 26 04:51:27 PM PDT 24
Peak memory 198640 kb
Host smart-8188e8b3-6a47-44fc-a992-b1cd9e8f4dea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902059368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2902059368
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2284215739
Short name T53
Test name
Test status
Simulation time 215610135 ps
CPU time 0.87 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:20 PM PDT 24
Peak memory 197632 kb
Host smart-0525ba5e-99b4-4377-a59e-a102306f355c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284215739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2284215739
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.977859214
Short name T804
Test name
Test status
Simulation time 168077939 ps
CPU time 0.85 seconds
Started Jun 26 04:51:18 PM PDT 24
Finished Jun 26 04:51:20 PM PDT 24
Peak memory 198584 kb
Host smart-9a2c1e57-df5d-44ff-94c3-144cb443e71c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977859214 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.977859214
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2838587767
Short name T85
Test name
Test status
Simulation time 38730595 ps
CPU time 0.57 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:22 PM PDT 24
Peak memory 193924 kb
Host smart-565868e0-dac1-444a-8d2d-0c513abc2d5c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838587767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2838587767
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.4056904035
Short name T834
Test name
Test status
Simulation time 57600738 ps
CPU time 0.57 seconds
Started Jun 26 04:51:20 PM PDT 24
Finished Jun 26 04:51:28 PM PDT 24
Peak memory 194300 kb
Host smart-d1bad6c7-8e1e-478a-b724-20d6ae13789e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056904035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.4056904035
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2682735530
Short name T809
Test name
Test status
Simulation time 289255688 ps
CPU time 0.71 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:22 PM PDT 24
Peak memory 195616 kb
Host smart-a08bc8df-8e47-43cd-9f06-5a92bde2a3db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682735530 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2682735530
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.759945282
Short name T826
Test name
Test status
Simulation time 35260858 ps
CPU time 1.75 seconds
Started Jun 26 04:51:19 PM PDT 24
Finished Jun 26 04:51:23 PM PDT 24
Peak memory 198620 kb
Host smart-8e66ea5c-9910-468b-a165-6e3deba6b77d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759945282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.759945282
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3446972954
Short name T794
Test name
Test status
Simulation time 261930844 ps
CPU time 0.87 seconds
Started Jun 26 04:51:23 PM PDT 24
Finished Jun 26 04:51:25 PM PDT 24
Peak memory 197584 kb
Host smart-058a1f57-382f-4fb2-82bc-e32dc75686fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446972954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3446972954
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3230582202
Short name T15
Test name
Test status
Simulation time 78042742 ps
CPU time 0.62 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 194468 kb
Host smart-974b5566-9e90-4c5d-9396-1cf318274a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230582202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3230582202
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.727015451
Short name T563
Test name
Test status
Simulation time 2849350139 ps
CPU time 22.98 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 197664 kb
Host smart-fad8998b-27b7-41e6-897b-b1e779699334
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727015451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.727015451
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.4129254735
Short name T564
Test name
Test status
Simulation time 42798356 ps
CPU time 0.79 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:57 PM PDT 24
Peak memory 196404 kb
Host smart-9694feec-3a81-4e65-a35e-6cc542542d7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129254735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.4129254735
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2764799603
Short name T226
Test name
Test status
Simulation time 667044449 ps
CPU time 1.44 seconds
Started Jun 26 04:51:28 PM PDT 24
Finished Jun 26 04:51:31 PM PDT 24
Peak memory 197544 kb
Host smart-c5516b3f-164d-4684-83cb-c84b8941a2d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764799603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2764799603
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.365638159
Short name T120
Test name
Test status
Simulation time 51914965 ps
CPU time 2.09 seconds
Started Jun 26 04:51:40 PM PDT 24
Finished Jun 26 04:51:45 PM PDT 24
Peak memory 198656 kb
Host smart-e4eb8db7-01fb-4e94-bd0c-7649995d2fd3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365638159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.365638159
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1246900098
Short name T609
Test name
Test status
Simulation time 277525901 ps
CPU time 1.68 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:38 PM PDT 24
Peak memory 196416 kb
Host smart-e3e51d0a-bcf9-4e51-998c-2f64e32a57d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246900098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1246900098
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4004860980
Short name T545
Test name
Test status
Simulation time 138569346 ps
CPU time 1.1 seconds
Started Jun 26 04:51:32 PM PDT 24
Finished Jun 26 04:51:36 PM PDT 24
Peak memory 197396 kb
Host smart-c5b53ead-7a8f-453e-86e0-f0eaf9bf3eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004860980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4004860980
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3873807619
Short name T425
Test name
Test status
Simulation time 17597334 ps
CPU time 0.73 seconds
Started Jun 26 04:51:35 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 194956 kb
Host smart-8558bf66-1711-4444-b2e3-da99f04fd504
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873807619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3873807619
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3458764366
Short name T326
Test name
Test status
Simulation time 495183890 ps
CPU time 5.39 seconds
Started Jun 26 04:51:42 PM PDT 24
Finished Jun 26 04:51:49 PM PDT 24
Peak memory 198568 kb
Host smart-c44edc7d-a0c3-4197-a22b-b1b9b5d5d615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458764366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3458764366
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.640538313
Short name T386
Test name
Test status
Simulation time 83674389 ps
CPU time 0.72 seconds
Started Jun 26 04:51:31 PM PDT 24
Finished Jun 26 04:51:35 PM PDT 24
Peak memory 195456 kb
Host smart-46b984b0-f80a-45c2-838e-ec6733335a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640538313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.640538313
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.628743595
Short name T549
Test name
Test status
Simulation time 324351174 ps
CPU time 1.05 seconds
Started Jun 26 04:51:33 PM PDT 24
Finished Jun 26 04:51:37 PM PDT 24
Peak memory 196324 kb
Host smart-4a86d491-1846-46b2-89a3-c74d4cc918bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628743595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.628743595
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2405765123
Short name T445
Test name
Test status
Simulation time 8069621449 ps
CPU time 109.62 seconds
Started Jun 26 04:51:42 PM PDT 24
Finished Jun 26 04:53:33 PM PDT 24
Peak memory 198688 kb
Host smart-8e61c8ed-8dd7-45c3-8a03-981b3ff958cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405765123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2405765123
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.627960199
Short name T65
Test name
Test status
Simulation time 253321436389 ps
CPU time 1219.02 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 05:12:14 PM PDT 24
Peak memory 198840 kb
Host smart-e6d87d17-c3e2-4435-8d40-7a72d7a90efb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=627960199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.627960199
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.302772973
Short name T435
Test name
Test status
Simulation time 12347832 ps
CPU time 0.57 seconds
Started Jun 26 04:51:40 PM PDT 24
Finished Jun 26 04:51:43 PM PDT 24
Peak memory 195252 kb
Host smart-3c052dd4-5d56-48fb-a95b-5567d5268072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302772973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.302772973
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1585751633
Short name T249
Test name
Test status
Simulation time 57226826 ps
CPU time 0.71 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:02 PM PDT 24
Peak memory 194736 kb
Host smart-2cc79354-8cb1-4b35-89a5-610ddcd43397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585751633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1585751633
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3454358908
Short name T552
Test name
Test status
Simulation time 511707282 ps
CPU time 17.93 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:19 PM PDT 24
Peak memory 197668 kb
Host smart-d8335f3c-46b6-4a24-abc5-9aa3587a8c74
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454358908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3454358908
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3635720868
Short name T521
Test name
Test status
Simulation time 157613294 ps
CPU time 0.65 seconds
Started Jun 26 04:51:46 PM PDT 24
Finished Jun 26 04:51:48 PM PDT 24
Peak memory 195308 kb
Host smart-148a580b-269d-433c-a89c-8e0f007b3a0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635720868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3635720868
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1680717993
Short name T166
Test name
Test status
Simulation time 341291925 ps
CPU time 1.06 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:51:43 PM PDT 24
Peak memory 197192 kb
Host smart-56b15f55-48ee-4a42-84f2-b4bf2d34922c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680717993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1680717993
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2776638616
Short name T273
Test name
Test status
Simulation time 72132945 ps
CPU time 2.93 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:42 PM PDT 24
Peak memory 198712 kb
Host smart-68c82c65-d618-47d8-ad8d-0a1b491056f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776638616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2776638616
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1781113861
Short name T240
Test name
Test status
Simulation time 137289751 ps
CPU time 3.44 seconds
Started Jun 26 04:51:35 PM PDT 24
Finished Jun 26 04:51:43 PM PDT 24
Peak memory 197636 kb
Host smart-9c42ea0d-724b-44c5-b582-f56d27b0ca7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781113861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1781113861
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1994335977
Short name T216
Test name
Test status
Simulation time 62681280 ps
CPU time 1.11 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 197392 kb
Host smart-e7c5f8b1-d278-47bc-989a-11cc8523050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994335977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1994335977
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.925331351
Short name T462
Test name
Test status
Simulation time 55596273 ps
CPU time 0.74 seconds
Started Jun 26 04:52:09 PM PDT 24
Finished Jun 26 04:52:12 PM PDT 24
Peak memory 196768 kb
Host smart-54fc1488-158a-490b-8c1a-9861e1691cd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925331351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.925331351
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2302718388
Short name T145
Test name
Test status
Simulation time 144253002 ps
CPU time 2.7 seconds
Started Jun 26 04:51:46 PM PDT 24
Finished Jun 26 04:51:50 PM PDT 24
Peak memory 198576 kb
Host smart-676e1108-7902-43fa-9516-04e1f077f489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302718388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2302718388
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.4168223398
Short name T43
Test name
Test status
Simulation time 121301147 ps
CPU time 0.8 seconds
Started Jun 26 04:51:36 PM PDT 24
Finished Jun 26 04:51:41 PM PDT 24
Peak memory 215128 kb
Host smart-1d8caa61-f63c-4247-b8a6-abd0e82a5859
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168223398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.4168223398
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.875275682
Short name T265
Test name
Test status
Simulation time 306570009 ps
CPU time 1.35 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:51:43 PM PDT 24
Peak memory 197448 kb
Host smart-7c77cb36-5f1f-491a-8767-edd9b86a41e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875275682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.875275682
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4093120926
Short name T320
Test name
Test status
Simulation time 157637440 ps
CPU time 0.98 seconds
Started Jun 26 04:52:01 PM PDT 24
Finished Jun 26 04:52:05 PM PDT 24
Peak memory 197684 kb
Host smart-c06bd26e-e7b7-4d66-b483-3c4e5abb1d0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093120926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4093120926
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.730828983
Short name T382
Test name
Test status
Simulation time 10981710125 ps
CPU time 137.82 seconds
Started Jun 26 04:51:48 PM PDT 24
Finished Jun 26 04:54:06 PM PDT 24
Peak memory 198768 kb
Host smart-906c5840-6bd3-468f-b5b0-cf2b3f35dd09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730828983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.730828983
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3229210848
Short name T440
Test name
Test status
Simulation time 38184215 ps
CPU time 0.58 seconds
Started Jun 26 04:52:07 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 194852 kb
Host smart-929a5c68-d820-4061-b0c7-14193777d237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229210848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3229210848
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1979280831
Short name T704
Test name
Test status
Simulation time 17091656 ps
CPU time 0.66 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:51:59 PM PDT 24
Peak memory 194892 kb
Host smart-4d9d6797-39fd-43bd-a7e9-d34c4ca93536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979280831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1979280831
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2572485971
Short name T389
Test name
Test status
Simulation time 1747760464 ps
CPU time 22.2 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:52:19 PM PDT 24
Peak memory 196184 kb
Host smart-58085abd-b81f-42a8-82da-f163747b5dfd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572485971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2572485971
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.896288211
Short name T401
Test name
Test status
Simulation time 41697624 ps
CPU time 0.77 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:08 PM PDT 24
Peak memory 196564 kb
Host smart-f179fc2f-6f7a-4ea1-a725-f4f4c511a870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896288211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.896288211
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.586337022
Short name T14
Test name
Test status
Simulation time 180455260 ps
CPU time 0.99 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:52 PM PDT 24
Peak memory 196576 kb
Host smart-b8f81f26-853b-4e4f-b08c-a062e99d5ffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586337022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.586337022
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.157018029
Short name T119
Test name
Test status
Simulation time 118356726 ps
CPU time 2.34 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 198640 kb
Host smart-50b2ed82-92a1-4b6b-8019-937acbcd8558
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157018029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.157018029
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1184357971
Short name T56
Test name
Test status
Simulation time 105423744 ps
CPU time 1 seconds
Started Jun 26 04:52:01 PM PDT 24
Finished Jun 26 04:52:05 PM PDT 24
Peak memory 196304 kb
Host smart-b3b363b4-6aaa-4d27-91be-a1053910a6b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184357971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1184357971
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1111232892
Short name T664
Test name
Test status
Simulation time 22056146 ps
CPU time 0.88 seconds
Started Jun 26 04:52:04 PM PDT 24
Finished Jun 26 04:52:07 PM PDT 24
Peak memory 197216 kb
Host smart-560876ec-e0ff-4614-805d-7ac3399037b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111232892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1111232892
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.195782695
Short name T174
Test name
Test status
Simulation time 23141961 ps
CPU time 0.85 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 197012 kb
Host smart-0f52767c-500f-4b22-b90b-81e06afdf199
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195782695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.195782695
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3634355925
Short name T114
Test name
Test status
Simulation time 148846418 ps
CPU time 2.48 seconds
Started Jun 26 04:51:58 PM PDT 24
Finished Jun 26 04:52:04 PM PDT 24
Peak memory 198616 kb
Host smart-db5383ec-47bf-4985-a52b-819529b3579e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634355925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3634355925
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3929261297
Short name T436
Test name
Test status
Simulation time 234292672 ps
CPU time 1.34 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:51:57 PM PDT 24
Peak memory 196860 kb
Host smart-93110c17-ba30-4180-9409-5561a65a37f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929261297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3929261297
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.25432217
Short name T400
Test name
Test status
Simulation time 67808787 ps
CPU time 1.14 seconds
Started Jun 26 04:51:43 PM PDT 24
Finished Jun 26 04:51:46 PM PDT 24
Peak memory 196156 kb
Host smart-87286282-91d7-4a2e-a59f-6452f75c659b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25432217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.25432217
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.658025492
Short name T182
Test name
Test status
Simulation time 9895581823 ps
CPU time 73.56 seconds
Started Jun 26 04:51:43 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 198760 kb
Host smart-b9b197ed-cc93-4435-83eb-b52658d56949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658025492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.658025492
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2862466406
Short name T147
Test name
Test status
Simulation time 20235215 ps
CPU time 0.58 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:57 PM PDT 24
Peak memory 194552 kb
Host smart-ee5fd4da-e1bd-4d26-98cd-1c7e34d49c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862466406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2862466406
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2512929082
Short name T23
Test name
Test status
Simulation time 234282659 ps
CPU time 0.87 seconds
Started Jun 26 04:51:41 PM PDT 24
Finished Jun 26 04:51:44 PM PDT 24
Peak memory 197984 kb
Host smart-cc21ca36-13c8-4643-8193-dfa8ac90fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512929082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2512929082
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3087265804
Short name T125
Test name
Test status
Simulation time 1367203882 ps
CPU time 23.42 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 197496 kb
Host smart-aab98c5d-4b89-490b-a5ef-c42b56b26675
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087265804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3087265804
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1127028098
Short name T351
Test name
Test status
Simulation time 34492384 ps
CPU time 0.68 seconds
Started Jun 26 04:51:58 PM PDT 24
Finished Jun 26 04:52:02 PM PDT 24
Peak memory 195332 kb
Host smart-5062b104-3a04-4395-a5fd-9d5b67725845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127028098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1127028098
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1007258260
Short name T371
Test name
Test status
Simulation time 143125847 ps
CPU time 1.28 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:58 PM PDT 24
Peak memory 197464 kb
Host smart-64785266-8211-4a94-aa2d-2c7212447fda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007258260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1007258260
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3928100132
Short name T510
Test name
Test status
Simulation time 347148161 ps
CPU time 3.37 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:53 PM PDT 24
Peak memory 197000 kb
Host smart-90338ccd-0c77-4ef7-b45d-6b56b84068cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928100132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3928100132
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.541096807
Short name T202
Test name
Test status
Simulation time 178296277 ps
CPU time 2.56 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:51:57 PM PDT 24
Peak memory 198716 kb
Host smart-0f8347c0-e221-4ae9-bc3f-544fbf202025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541096807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
541096807
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1562630431
Short name T156
Test name
Test status
Simulation time 107082238 ps
CPU time 0.76 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 196204 kb
Host smart-7b22f543-feaa-4b2a-9ebb-53009566b176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562630431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1562630431
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1486414253
Short name T595
Test name
Test status
Simulation time 38625183 ps
CPU time 0.68 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 194888 kb
Host smart-d75d1f0f-7698-4c12-ae4f-4b833c4228db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486414253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1486414253
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1129862356
Short name T423
Test name
Test status
Simulation time 1946241051 ps
CPU time 3.5 seconds
Started Jun 26 04:51:48 PM PDT 24
Finished Jun 26 04:51:53 PM PDT 24
Peak memory 198572 kb
Host smart-33701239-8aae-4aab-ac3c-49e57a8053e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129862356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1129862356
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1547285728
Short name T633
Test name
Test status
Simulation time 146120677 ps
CPU time 1.1 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:51:59 PM PDT 24
Peak memory 196420 kb
Host smart-47e17c2a-825c-49a9-93c3-bb4fc33b49a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547285728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1547285728
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2536622309
Short name T197
Test name
Test status
Simulation time 141378886 ps
CPU time 1.29 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 197264 kb
Host smart-bf32db86-3d3b-422a-986c-1d5c0450a97b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536622309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2536622309
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3636565189
Short name T292
Test name
Test status
Simulation time 44630729 ps
CPU time 0.59 seconds
Started Jun 26 04:51:48 PM PDT 24
Finished Jun 26 04:51:50 PM PDT 24
Peak memory 195356 kb
Host smart-2e105731-c4b4-46dc-a85a-f93b6fe17ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636565189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3636565189
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3650246703
Short name T711
Test name
Test status
Simulation time 29107916 ps
CPU time 0.76 seconds
Started Jun 26 04:51:44 PM PDT 24
Finished Jun 26 04:51:46 PM PDT 24
Peak memory 195836 kb
Host smart-91a86051-63ed-448c-ae83-9a0aabed8817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650246703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3650246703
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.353073898
Short name T154
Test name
Test status
Simulation time 693883103 ps
CPU time 6.47 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:52:02 PM PDT 24
Peak memory 196832 kb
Host smart-1d68de86-c793-42dd-a801-90c039ff4ec3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353073898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.353073898
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1027781417
Short name T252
Test name
Test status
Simulation time 50122662 ps
CPU time 0.79 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:51:56 PM PDT 24
Peak memory 196520 kb
Host smart-a83d6c85-35b4-4cbc-a18c-83bb04603af8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027781417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1027781417
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2383732138
Short name T263
Test name
Test status
Simulation time 117871292 ps
CPU time 0.81 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:02 PM PDT 24
Peak memory 196212 kb
Host smart-dcfafef2-44cf-40a1-a52a-58f1839c747f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383732138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2383732138
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.546415037
Short name T159
Test name
Test status
Simulation time 41002181 ps
CPU time 0.95 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:51:55 PM PDT 24
Peak memory 196868 kb
Host smart-518ffe08-59a2-4254-a26e-f1476e390c15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546415037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.546415037
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3323314641
Short name T699
Test name
Test status
Simulation time 426883816 ps
CPU time 2.01 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:03 PM PDT 24
Peak memory 196864 kb
Host smart-52be9edd-4bd5-4e16-b433-68c9f4c6682e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323314641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3323314641
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.824195954
Short name T395
Test name
Test status
Simulation time 130264037 ps
CPU time 0.71 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:27 PM PDT 24
Peak memory 195640 kb
Host smart-dcaadb76-e33c-4180-a2b9-876eca62b029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824195954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.824195954
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1848181191
Short name T516
Test name
Test status
Simulation time 117000953 ps
CPU time 1.32 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 197960 kb
Host smart-2ebba73e-b8a9-4f6f-9e43-e24a2a85a19b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848181191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1848181191
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2482702529
Short name T688
Test name
Test status
Simulation time 194595148 ps
CPU time 2.77 seconds
Started Jun 26 04:52:01 PM PDT 24
Finished Jun 26 04:52:06 PM PDT 24
Peak memory 198612 kb
Host smart-d2c6ad83-637c-4a2f-89eb-b73e3ad9114c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482702529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2482702529
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.337195422
Short name T550
Test name
Test status
Simulation time 284190222 ps
CPU time 1.39 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:03 PM PDT 24
Peak memory 197492 kb
Host smart-6547c9c8-47f9-499f-b472-b9dbd8e23828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337195422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.337195422
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3158492359
Short name T257
Test name
Test status
Simulation time 62880353 ps
CPU time 1.01 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 197968 kb
Host smart-7951e72d-bf4f-480b-8404-c2a6d6215d06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158492359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3158492359
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.294759789
Short name T484
Test name
Test status
Simulation time 7741012834 ps
CPU time 182.26 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:55:03 PM PDT 24
Peak memory 198748 kb
Host smart-963984ab-eee3-4fa9-b09a-895584c3aca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294759789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.294759789
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3005440530
Short name T219
Test name
Test status
Simulation time 20752886 ps
CPU time 0.55 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:08 PM PDT 24
Peak memory 194580 kb
Host smart-9a8f2112-eeaf-4cfa-a93b-5d0a910588ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005440530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3005440530
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3299856872
Short name T291
Test name
Test status
Simulation time 47731158 ps
CPU time 0.86 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:51:57 PM PDT 24
Peak memory 196984 kb
Host smart-b8949099-2129-49a3-a43e-06f774296c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299856872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3299856872
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4095713744
Short name T603
Test name
Test status
Simulation time 930544426 ps
CPU time 27.67 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:28 PM PDT 24
Peak memory 198580 kb
Host smart-fd13f9e6-d88a-481c-901c-22f35f29f4ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095713744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4095713744
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.612022525
Short name T418
Test name
Test status
Simulation time 178199364 ps
CPU time 0.78 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 196476 kb
Host smart-3d12a75b-3c4f-4f98-a546-7b118e646479
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612022525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.612022525
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1765510258
Short name T429
Test name
Test status
Simulation time 49915979 ps
CPU time 0.91 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:08 PM PDT 24
Peak memory 197368 kb
Host smart-efeec31c-1a54-4c77-a121-4c8a3b276026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765510258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1765510258
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.4159731859
Short name T334
Test name
Test status
Simulation time 227497375 ps
CPU time 2.41 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 196952 kb
Host smart-d9fd084e-5380-4b38-9161-a969ac84a4d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159731859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.4159731859
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2406100592
Short name T454
Test name
Test status
Simulation time 806278546 ps
CPU time 3.18 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 197664 kb
Host smart-694a6996-60eb-4cb4-a462-7955e7b6bb63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406100592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2406100592
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.443287714
Short name T235
Test name
Test status
Simulation time 64936523 ps
CPU time 1.3 seconds
Started Jun 26 04:52:04 PM PDT 24
Finished Jun 26 04:52:07 PM PDT 24
Peak memory 196532 kb
Host smart-2d52e159-3d9d-4b3b-b4d7-d65dfb5eba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443287714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.443287714
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3412518649
Short name T315
Test name
Test status
Simulation time 58049076 ps
CPU time 1.31 seconds
Started Jun 26 04:51:50 PM PDT 24
Finished Jun 26 04:51:53 PM PDT 24
Peak memory 198624 kb
Host smart-ce44edf2-5f81-4066-880a-9e30bbc3f477
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412518649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3412518649
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1016155238
Short name T536
Test name
Test status
Simulation time 1557517960 ps
CPU time 3.21 seconds
Started Jun 26 04:52:10 PM PDT 24
Finished Jun 26 04:52:16 PM PDT 24
Peak memory 198552 kb
Host smart-9f8d2abe-fd18-458c-aa55-dc7c952d42b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016155238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1016155238
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1872387587
Short name T495
Test name
Test status
Simulation time 113001051 ps
CPU time 0.9 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:58 PM PDT 24
Peak memory 196220 kb
Host smart-0e51b3e9-e6e1-42f8-be2a-71885c83aada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872387587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1872387587
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.726947028
Short name T288
Test name
Test status
Simulation time 84383458 ps
CPU time 1.32 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 196876 kb
Host smart-cbfde79d-f2a2-4c14-b14f-4ede629dc081
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726947028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.726947028
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2771234827
Short name T142
Test name
Test status
Simulation time 116183353427 ps
CPU time 215.67 seconds
Started Jun 26 04:51:50 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 198820 kb
Host smart-6131669b-1d8f-420c-86d1-d52ec8320258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771234827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2771234827
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.555528501
Short name T562
Test name
Test status
Simulation time 84798969 ps
CPU time 0.57 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:21 PM PDT 24
Peak memory 194592 kb
Host smart-464a7c46-8f17-4e26-9798-028bb37f7121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555528501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.555528501
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.947148647
Short name T578
Test name
Test status
Simulation time 23688889 ps
CPU time 0.76 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 196512 kb
Host smart-294af792-23da-4704-b718-613e4fa86a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947148647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.947148647
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1028604948
Short name T499
Test name
Test status
Simulation time 3623827015 ps
CPU time 24.43 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:32 PM PDT 24
Peak memory 198712 kb
Host smart-df1dd1b5-4d68-498a-b254-1c63f1c3f7a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028604948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1028604948
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2321647957
Short name T629
Test name
Test status
Simulation time 25982976 ps
CPU time 0.65 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 195064 kb
Host smart-84069932-f680-4e1a-876d-f41f33520f13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321647957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2321647957
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3187083586
Short name T708
Test name
Test status
Simulation time 56493324 ps
CPU time 0.76 seconds
Started Jun 26 04:52:25 PM PDT 24
Finished Jun 26 04:52:29 PM PDT 24
Peak memory 196068 kb
Host smart-1fb8be79-7078-4ba9-943e-49dc840cd359
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187083586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3187083586
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1137043496
Short name T406
Test name
Test status
Simulation time 67748567 ps
CPU time 2.53 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:02 PM PDT 24
Peak memory 196964 kb
Host smart-5d16b287-fad2-4770-9066-f6a96addf41a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137043496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1137043496
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3148460272
Short name T473
Test name
Test status
Simulation time 76603249 ps
CPU time 1.32 seconds
Started Jun 26 04:52:15 PM PDT 24
Finished Jun 26 04:52:19 PM PDT 24
Peak memory 196764 kb
Host smart-8c037127-c317-4ea4-8d8d-582f64bd4c83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148460272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3148460272
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.973861780
Short name T110
Test name
Test status
Simulation time 69354702 ps
CPU time 1.02 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:58 PM PDT 24
Peak memory 196464 kb
Host smart-e7a8183f-47e9-4b64-a503-3dd3b1ae5cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973861780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.973861780
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.235483778
Short name T322
Test name
Test status
Simulation time 63282759 ps
CPU time 0.75 seconds
Started Jun 26 04:51:50 PM PDT 24
Finished Jun 26 04:51:52 PM PDT 24
Peak memory 196100 kb
Host smart-3ea9b952-2619-4f16-85f3-6579c45fa315
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235483778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.235483778
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4028266198
Short name T566
Test name
Test status
Simulation time 248655738 ps
CPU time 3.21 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:14 PM PDT 24
Peak memory 198536 kb
Host smart-e8b3cc14-f22a-4219-8b0f-6d9bb6fa96cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028266198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4028266198
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2479577817
Short name T398
Test name
Test status
Simulation time 71962858 ps
CPU time 1.02 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:18 PM PDT 24
Peak memory 197072 kb
Host smart-61a4434a-868b-40b2-b1f3-1fc75ffef18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479577817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2479577817
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3227410105
Short name T610
Test name
Test status
Simulation time 544956499 ps
CPU time 1.03 seconds
Started Jun 26 04:52:00 PM PDT 24
Finished Jun 26 04:52:04 PM PDT 24
Peak memory 197028 kb
Host smart-372a15b5-3aa4-471b-8e53-dd11aa2b5120
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227410105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3227410105
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.823883342
Short name T374
Test name
Test status
Simulation time 11096301200 ps
CPU time 141.19 seconds
Started Jun 26 04:52:23 PM PDT 24
Finished Jun 26 04:54:46 PM PDT 24
Peak memory 198732 kb
Host smart-203a47ae-1ce3-4cca-8528-9ceed5954757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823883342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.823883342
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1443808085
Short name T63
Test name
Test status
Simulation time 145201769978 ps
CPU time 1164.31 seconds
Started Jun 26 04:52:09 PM PDT 24
Finished Jun 26 05:11:36 PM PDT 24
Peak memory 198896 kb
Host smart-c23b4649-11b2-4125-b1bc-ae3a4ba5c507
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1443808085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1443808085
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.3882490950
Short name T644
Test name
Test status
Simulation time 12027829 ps
CPU time 0.56 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:52:15 PM PDT 24
Peak memory 195392 kb
Host smart-2377cebc-7a44-4e1d-8609-aa724b1c8a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882490950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.3882490950
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2085839401
Short name T405
Test name
Test status
Simulation time 81634453 ps
CPU time 0.7 seconds
Started Jun 26 04:52:17 PM PDT 24
Finished Jun 26 04:52:21 PM PDT 24
Peak memory 194840 kb
Host smart-8e8b9602-2448-4bb5-bfe9-e1fdace33c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085839401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2085839401
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3074973710
Short name T138
Test name
Test status
Simulation time 2079702488 ps
CPU time 3.9 seconds
Started Jun 26 04:52:11 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 197160 kb
Host smart-e422ca91-c680-4d9b-afb5-fbb669f797ad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074973710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3074973710
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1799086898
Short name T446
Test name
Test status
Simulation time 302805856 ps
CPU time 0.97 seconds
Started Jun 26 04:52:25 PM PDT 24
Finished Jun 26 04:52:30 PM PDT 24
Peak memory 197224 kb
Host smart-bcc2a92e-6290-4e21-9095-e3e07eb1c775
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799086898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1799086898
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.247559253
Short name T167
Test name
Test status
Simulation time 27463910 ps
CPU time 0.69 seconds
Started Jun 26 04:52:11 PM PDT 24
Finished Jun 26 04:52:14 PM PDT 24
Peak memory 195604 kb
Host smart-4f5ba22d-9e33-4b14-b65a-9dea508b4e3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247559253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.247559253
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2543682619
Short name T113
Test name
Test status
Simulation time 285256360 ps
CPU time 1.42 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 197172 kb
Host smart-23ed00dc-dcec-4137-aaf6-42cdd097e28c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543682619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2543682619
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1559452429
Short name T487
Test name
Test status
Simulation time 68461870 ps
CPU time 1.61 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 196832 kb
Host smart-dd7e5d86-924b-49c0-94ab-0f607c20cb15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559452429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1559452429
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3200301425
Short name T152
Test name
Test status
Simulation time 31762715 ps
CPU time 1.21 seconds
Started Jun 26 04:51:59 PM PDT 24
Finished Jun 26 04:52:04 PM PDT 24
Peak memory 197244 kb
Host smart-b55f2ef7-b2ec-4e56-b0dc-b22bc1da76c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200301425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3200301425
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3956520238
Short name T411
Test name
Test status
Simulation time 106247629 ps
CPU time 1.14 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 196528 kb
Host smart-ed1dee11-3dd3-40e8-8fa8-9fcffb750d12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956520238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3956520238
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.710092822
Short name T636
Test name
Test status
Simulation time 385066220 ps
CPU time 4.34 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 198492 kb
Host smart-2c674ae2-d62c-4f11-9266-6f7d88fd9efa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710092822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.710092822
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.1285650777
Short name T328
Test name
Test status
Simulation time 118870870 ps
CPU time 0.96 seconds
Started Jun 26 04:52:26 PM PDT 24
Finished Jun 26 04:52:31 PM PDT 24
Peak memory 196156 kb
Host smart-d2789be1-a39f-4e3b-ab2e-2eaf16dfed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285650777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.1285650777
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3294482684
Short name T251
Test name
Test status
Simulation time 364945441 ps
CPU time 1.27 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:09 PM PDT 24
Peak memory 197504 kb
Host smart-7358e879-a455-4f57-836a-3a27ffd2af62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294482684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3294482684
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1367969571
Short name T255
Test name
Test status
Simulation time 5307380829 ps
CPU time 126.62 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:54:23 PM PDT 24
Peak memory 198796 kb
Host smart-88977dc2-6bf8-4bb6-b684-c4a34489a15e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367969571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1367969571
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.2489207323
Short name T66
Test name
Test status
Simulation time 225183897316 ps
CPU time 1253.94 seconds
Started Jun 26 04:52:02 PM PDT 24
Finished Jun 26 05:12:58 PM PDT 24
Peak memory 198840 kb
Host smart-047388c1-7dfe-44b0-8c4d-dc0e2e9d9bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2489207323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.2489207323
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3636883253
Short name T507
Test name
Test status
Simulation time 17369155 ps
CPU time 0.58 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 194660 kb
Host smart-b79b85e6-3f4a-4a21-9384-e20743b2e5ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636883253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3636883253
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.4246213615
Short name T331
Test name
Test status
Simulation time 21605530 ps
CPU time 0.72 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 195412 kb
Host smart-630e7a7c-a0ac-4ae6-bffd-5dbae0133229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246213615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.4246213615
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3392039050
Short name T448
Test name
Test status
Simulation time 2937837360 ps
CPU time 26.38 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:45 PM PDT 24
Peak memory 198736 kb
Host smart-a8e12005-1d07-4170-883a-702ef19c8c0f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392039050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3392039050
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.463498157
Short name T356
Test name
Test status
Simulation time 148822944 ps
CPU time 0.78 seconds
Started Jun 26 04:52:26 PM PDT 24
Finished Jun 26 04:52:30 PM PDT 24
Peak memory 197140 kb
Host smart-a0387a31-6b13-49e3-8678-52b14053d7b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463498157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.463498157
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1028125686
Short name T308
Test name
Test status
Simulation time 178989311 ps
CPU time 1.38 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:18 PM PDT 24
Peak memory 197816 kb
Host smart-d537d5be-7423-4516-853e-ba19d11f843e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028125686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1028125686
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1724269603
Short name T409
Test name
Test status
Simulation time 169505716 ps
CPU time 1.48 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 198708 kb
Host smart-3116f682-1e05-40cc-9439-0c45239257b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724269603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1724269603
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3020745973
Short name T366
Test name
Test status
Simulation time 56337405 ps
CPU time 1.16 seconds
Started Jun 26 04:51:59 PM PDT 24
Finished Jun 26 04:52:03 PM PDT 24
Peak memory 196332 kb
Host smart-25ebadab-5116-42b4-9efe-e769cb93af75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020745973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3020745973
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2516930677
Short name T187
Test name
Test status
Simulation time 30932978 ps
CPU time 1.07 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 197240 kb
Host smart-07fb4efe-a5bb-44d3-bd47-ee972809519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516930677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2516930677
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1562574352
Short name T62
Test name
Test status
Simulation time 95554351 ps
CPU time 1.06 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:09 PM PDT 24
Peak memory 196448 kb
Host smart-264791c3-78d2-4d5d-9163-ac76cd3a6271
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562574352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1562574352
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1075008331
Short name T352
Test name
Test status
Simulation time 402402029 ps
CPU time 1.59 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 198580 kb
Host smart-f61eab14-b866-442b-b5fd-4427e89292fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075008331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1075008331
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3485476978
Short name T341
Test name
Test status
Simulation time 50068923 ps
CPU time 1.06 seconds
Started Jun 26 04:51:58 PM PDT 24
Finished Jun 26 04:52:03 PM PDT 24
Peak memory 196280 kb
Host smart-9deb2e5d-eef6-4f6d-8764-3665f2e5778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485476978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3485476978
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4040446339
Short name T544
Test name
Test status
Simulation time 170803787 ps
CPU time 1.24 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 197104 kb
Host smart-fe4bc484-94da-403d-ba0f-abcdeef4d587
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040446339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4040446339
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2172118499
Short name T364
Test name
Test status
Simulation time 7164510583 ps
CPU time 136.44 seconds
Started Jun 26 04:52:15 PM PDT 24
Finished Jun 26 04:54:34 PM PDT 24
Peak memory 198720 kb
Host smart-e83246de-d131-49f9-a1ac-7f761578beef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172118499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2172118499
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3042863877
Short name T35
Test name
Test status
Simulation time 136989431360 ps
CPU time 1094.36 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 05:10:30 PM PDT 24
Peak memory 198960 kb
Host smart-7c88d017-6f50-42a7-99f2-c718d7fd8139
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3042863877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3042863877
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.4269141854
Short name T593
Test name
Test status
Simulation time 23431597 ps
CPU time 0.57 seconds
Started Jun 26 04:52:23 PM PDT 24
Finished Jun 26 04:52:26 PM PDT 24
Peak memory 194592 kb
Host smart-02df3868-a743-4ad0-b63d-429b64dd536e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269141854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.4269141854
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2526578991
Short name T376
Test name
Test status
Simulation time 77004566 ps
CPU time 0.75 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:18 PM PDT 24
Peak memory 195940 kb
Host smart-bfa1c74e-43b2-413e-9117-d688131e0808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526578991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2526578991
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2313027019
Short name T224
Test name
Test status
Simulation time 844754668 ps
CPU time 21.42 seconds
Started Jun 26 04:52:34 PM PDT 24
Finished Jun 26 04:52:59 PM PDT 24
Peak memory 198696 kb
Host smart-ef26e81f-3244-47a1-9ba5-2a1e548b6d1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313027019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2313027019
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1783149072
Short name T438
Test name
Test status
Simulation time 69838670 ps
CPU time 1.04 seconds
Started Jun 26 04:52:07 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 197020 kb
Host smart-cd9bc1bd-c32b-42d2-a8c4-ed3eaac0c106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783149072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1783149072
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3244625968
Short name T682
Test name
Test status
Simulation time 118866434 ps
CPU time 1.03 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 196768 kb
Host smart-20b03d04-ab37-45f9-9713-a4bb8767d84f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244625968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3244625968
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.4140197966
Short name T220
Test name
Test status
Simulation time 85333319 ps
CPU time 3.39 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:04 PM PDT 24
Peak memory 198568 kb
Host smart-fb3b27a0-c521-48e0-8cbf-114ee04b6a3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140197966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.4140197966
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2830208199
Short name T184
Test name
Test status
Simulation time 345554997 ps
CPU time 2.02 seconds
Started Jun 26 04:52:22 PM PDT 24
Finished Jun 26 04:52:26 PM PDT 24
Peak memory 196392 kb
Host smart-f4ff8ed4-0743-4445-8764-97187e853266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830208199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2830208199
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2221490190
Short name T233
Test name
Test status
Simulation time 447196369 ps
CPU time 1.06 seconds
Started Jun 26 04:52:20 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 197044 kb
Host smart-d8928a49-f19c-4f23-9cd2-7879aea81789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221490190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2221490190
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.858196799
Short name T427
Test name
Test status
Simulation time 65154731 ps
CPU time 1.19 seconds
Started Jun 26 04:52:26 PM PDT 24
Finished Jun 26 04:52:30 PM PDT 24
Peak memory 196408 kb
Host smart-6c698c9d-83be-401d-a42c-fe7285075ba4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858196799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.858196799
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.4199201382
Short name T8
Test name
Test status
Simulation time 199476981 ps
CPU time 2.33 seconds
Started Jun 26 04:52:09 PM PDT 24
Finished Jun 26 04:52:13 PM PDT 24
Peak memory 198668 kb
Host smart-50b2c6f8-9b68-4ec9-9af4-add7682b0c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199201382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.4199201382
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2771893354
Short name T482
Test name
Test status
Simulation time 125230672 ps
CPU time 1.04 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 196236 kb
Host smart-b31c15bf-cb42-4223-9723-c319bd483920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771893354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2771893354
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.567864806
Short name T134
Test name
Test status
Simulation time 215170574 ps
CPU time 1.06 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 196444 kb
Host smart-016022f8-c1f9-4134-bf79-4fd27f280e60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567864806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.567864806
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.96512689
Short name T606
Test name
Test status
Simulation time 23440378758 ps
CPU time 52.13 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:53:08 PM PDT 24
Peak memory 198836 kb
Host smart-bcebfab1-8601-4c84-b9df-f8dd45d40e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96512689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gp
io_stress_all.96512689
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.326911488
Short name T655
Test name
Test status
Simulation time 14601704 ps
CPU time 0.55 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:52:15 PM PDT 24
Peak memory 194648 kb
Host smart-aefc3c34-1df9-4e44-be07-5ea9c72c5917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326911488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.326911488
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2894998729
Short name T391
Test name
Test status
Simulation time 47899387 ps
CPU time 0.72 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 195880 kb
Host smart-a8689d90-9b19-452b-920a-ec7e142f6d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894998729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2894998729
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.4193701652
Short name T313
Test name
Test status
Simulation time 833081108 ps
CPU time 24.72 seconds
Started Jun 26 04:52:09 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 198580 kb
Host smart-3bf0641f-b850-4780-955e-2cf134b35c40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193701652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.4193701652
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.4030685374
Short name T179
Test name
Test status
Simulation time 59530250 ps
CPU time 0.88 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 196668 kb
Host smart-2b8cd3bb-3671-4b8c-98c5-a1fe275b2f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030685374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.4030685374
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2688879849
Short name T572
Test name
Test status
Simulation time 67564671 ps
CPU time 0.74 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 196148 kb
Host smart-8500fa6d-41e0-40f5-990d-c8e5111d84f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688879849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2688879849
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1939045196
Short name T592
Test name
Test status
Simulation time 25523942 ps
CPU time 1.05 seconds
Started Jun 26 04:52:07 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 196584 kb
Host smart-66e0e7ae-0365-480e-ad6b-392ed33ef352
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939045196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1939045196
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3912550624
Short name T529
Test name
Test status
Simulation time 121821614 ps
CPU time 2.51 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 198684 kb
Host smart-23f36d5e-eca3-4ce0-a4d5-1134d9706189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912550624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3912550624
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.323996042
Short name T177
Test name
Test status
Simulation time 83472397 ps
CPU time 0.83 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:16 PM PDT 24
Peak memory 196640 kb
Host smart-0965b0a2-2ae7-4a25-9fdf-918c936d52c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323996042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.323996042
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2659220658
Short name T164
Test name
Test status
Simulation time 80468723 ps
CPU time 0.77 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 196740 kb
Host smart-460ca386-0e9a-42c5-bf66-a8a4c033fda0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659220658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2659220658
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2672664471
Short name T242
Test name
Test status
Simulation time 2514556800 ps
CPU time 3.91 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:21 PM PDT 24
Peak memory 198656 kb
Host smart-14aa39de-5771-4b0b-a18e-0ae838cebace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672664471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2672664471
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1752827205
Short name T201
Test name
Test status
Simulation time 30316651 ps
CPU time 0.92 seconds
Started Jun 26 04:52:17 PM PDT 24
Finished Jun 26 04:52:21 PM PDT 24
Peak memory 197608 kb
Host smart-4c1c8f55-326c-444e-87fd-250bd8eaf7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752827205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1752827205
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.195782299
Short name T535
Test name
Test status
Simulation time 169375681 ps
CPU time 1.27 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:08 PM PDT 24
Peak memory 198704 kb
Host smart-1bce4b01-38df-4e8d-95d8-90579040bc9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195782299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.195782299
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3754921509
Short name T130
Test name
Test status
Simulation time 963999587 ps
CPU time 23.26 seconds
Started Jun 26 04:52:15 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 198620 kb
Host smart-543a20db-40a7-4af9-8706-7057117a35de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754921509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3754921509
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3731939104
Short name T714
Test name
Test status
Simulation time 20298048474 ps
CPU time 173.78 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:55:07 PM PDT 24
Peak memory 198948 kb
Host smart-5e1815e9-df71-4e85-bbfc-4329761363c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3731939104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3731939104
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2527736220
Short name T677
Test name
Test status
Simulation time 12718674 ps
CPU time 0.56 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:52:14 PM PDT 24
Peak memory 194580 kb
Host smart-aece7002-2ce4-476e-84ec-d60d432690d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527736220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2527736220
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1877467735
Short name T294
Test name
Test status
Simulation time 148240079 ps
CPU time 0.67 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 194804 kb
Host smart-79b14ef9-8d41-4fe3-8788-055372c0c161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877467735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1877467735
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.4206157687
Short name T299
Test name
Test status
Simulation time 895768197 ps
CPU time 12 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 198560 kb
Host smart-1df81c8a-2a74-4cb3-ba0f-5f866a9efdda
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206157687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.4206157687
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.809847529
Short name T340
Test name
Test status
Simulation time 36272801 ps
CPU time 0.71 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 196268 kb
Host smart-ecc04682-fe5b-4091-8b99-1c523e9114ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809847529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.809847529
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4277373260
Short name T637
Test name
Test status
Simulation time 338757492 ps
CPU time 1.36 seconds
Started Jun 26 04:52:07 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 197752 kb
Host smart-b44df96e-265f-4ff6-9269-6748c83dfefa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277373260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4277373260
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2406447749
Short name T457
Test name
Test status
Simulation time 63526631 ps
CPU time 2.46 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:18 PM PDT 24
Peak memory 198604 kb
Host smart-f0be710b-644a-47d8-88cb-d54c8012a5fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406447749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2406447749
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3590775317
Short name T394
Test name
Test status
Simulation time 263708962 ps
CPU time 1.05 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:52:15 PM PDT 24
Peak memory 196220 kb
Host smart-ea391b64-2fd0-4fbb-b2bb-55ca42e8b3d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590775317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3590775317
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.396760339
Short name T293
Test name
Test status
Simulation time 29066563 ps
CPU time 1 seconds
Started Jun 26 04:52:11 PM PDT 24
Finished Jun 26 04:52:15 PM PDT 24
Peak memory 196476 kb
Host smart-3be5f0fd-ede6-414a-b161-ee67107275f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396760339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.396760339
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3200331350
Short name T302
Test name
Test status
Simulation time 83706306 ps
CPU time 0.81 seconds
Started Jun 26 04:52:04 PM PDT 24
Finished Jun 26 04:52:06 PM PDT 24
Peak memory 196620 kb
Host smart-2e599b38-54fc-4028-b239-0ff58d481d63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200331350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3200331350
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1069095569
Short name T173
Test name
Test status
Simulation time 80108845 ps
CPU time 3.38 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:19 PM PDT 24
Peak memory 198596 kb
Host smart-8b7f0bf8-77d3-49c8-bb54-802ec695fc16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069095569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1069095569
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1087952949
Short name T232
Test name
Test status
Simulation time 119275524 ps
CPU time 1.13 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:52:16 PM PDT 24
Peak memory 196452 kb
Host smart-dde631d5-536c-47ce-9b73-33d9d7889393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087952949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1087952949
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1556038093
Short name T659
Test name
Test status
Simulation time 28867997 ps
CPU time 0.75 seconds
Started Jun 26 04:52:10 PM PDT 24
Finished Jun 26 04:52:13 PM PDT 24
Peak memory 195824 kb
Host smart-d7764f20-3237-4bc3-b5c7-513d2a1b653d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556038093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1556038093
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3364761333
Short name T625
Test name
Test status
Simulation time 20322748701 ps
CPU time 218 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:56:11 PM PDT 24
Peak memory 198472 kb
Host smart-843e42f8-bde5-4646-a548-57d1902ef22b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364761333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3364761333
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3375648062
Short name T456
Test name
Test status
Simulation time 11206781 ps
CPU time 0.58 seconds
Started Jun 26 04:51:51 PM PDT 24
Finished Jun 26 04:51:53 PM PDT 24
Peak memory 194572 kb
Host smart-17e0af89-1d06-4b2e-8eef-06178e323632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375648062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3375648062
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.933083190
Short name T365
Test name
Test status
Simulation time 15892821 ps
CPU time 0.62 seconds
Started Jun 26 04:51:45 PM PDT 24
Finished Jun 26 04:51:46 PM PDT 24
Peak memory 195276 kb
Host smart-e7dbb63f-9016-4fe4-aca7-de7e3198cc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933083190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.933083190
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.4120831846
Short name T556
Test name
Test status
Simulation time 8731577512 ps
CPU time 23.26 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:52:21 PM PDT 24
Peak memory 197548 kb
Host smart-c60f59a3-5dce-4f8c-96f9-f29f8a19f50f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120831846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.4120831846
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.408486327
Short name T3
Test name
Test status
Simulation time 62144094 ps
CPU time 0.92 seconds
Started Jun 26 04:51:48 PM PDT 24
Finished Jun 26 04:51:51 PM PDT 24
Peak memory 198560 kb
Host smart-0b39f220-9491-4d4c-8e1a-e07bdedd383c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408486327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.408486327
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1257051682
Short name T433
Test name
Test status
Simulation time 114721207 ps
CPU time 0.82 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:51 PM PDT 24
Peak memory 196980 kb
Host smart-59f6822b-52ad-46d7-aa17-b17c040ced4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257051682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1257051682
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.305283144
Short name T716
Test name
Test status
Simulation time 55532258 ps
CPU time 2.09 seconds
Started Jun 26 04:51:44 PM PDT 24
Finished Jun 26 04:51:48 PM PDT 24
Peak memory 198744 kb
Host smart-406d711e-6ba5-4d79-9beb-45ada6415f13
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305283144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.305283144
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3111866060
Short name T547
Test name
Test status
Simulation time 404040490 ps
CPU time 2.02 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 196872 kb
Host smart-7e28427f-fe2a-404e-94c4-540f3538e873
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111866060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3111866060
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.809493736
Short name T253
Test name
Test status
Simulation time 16165611 ps
CPU time 0.67 seconds
Started Jun 26 04:51:41 PM PDT 24
Finished Jun 26 04:51:44 PM PDT 24
Peak memory 194936 kb
Host smart-be47f334-133c-4414-bf23-3a20d5381720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809493736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.809493736
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.923821593
Short name T310
Test name
Test status
Simulation time 113386400 ps
CPU time 1.13 seconds
Started Jun 26 04:51:45 PM PDT 24
Finished Jun 26 04:51:47 PM PDT 24
Peak memory 197680 kb
Host smart-f042d71c-34a9-41f4-b7e9-3d7bda113583
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923821593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.923821593
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.523917893
Short name T701
Test name
Test status
Simulation time 277309906 ps
CPU time 1.54 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 198664 kb
Host smart-ffe12dae-7f09-4479-8e39-b59fde1586f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523917893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.523917893
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.630318862
Short name T54
Test name
Test status
Simulation time 66546416 ps
CPU time 0.78 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:51:43 PM PDT 24
Peak memory 214176 kb
Host smart-19375d2c-6c1d-44ab-9baa-3e7cfa738eb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630318862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.630318862
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2781941294
Short name T458
Test name
Test status
Simulation time 317375618 ps
CPU time 1.48 seconds
Started Jun 26 04:51:47 PM PDT 24
Finished Jun 26 04:51:49 PM PDT 24
Peak memory 196236 kb
Host smart-3bb23c77-9060-401a-b44c-1025d0313bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781941294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2781941294
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2842418631
Short name T558
Test name
Test status
Simulation time 503249015 ps
CPU time 1.3 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:51:59 PM PDT 24
Peak memory 197360 kb
Host smart-992e2d98-07e8-48ab-9204-7c366ad25977
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842418631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2842418631
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3831103661
Short name T337
Test name
Test status
Simulation time 33639298985 ps
CPU time 155.31 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 198776 kb
Host smart-c158cd0f-5f9a-4e6c-b630-843d62b16ebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831103661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3831103661
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1758806481
Short name T247
Test name
Test status
Simulation time 51890976 ps
CPU time 0.59 seconds
Started Jun 26 04:52:23 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 195488 kb
Host smart-96dd3540-65e5-49d7-8cfb-602c04de4134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758806481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1758806481
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2008876824
Short name T186
Test name
Test status
Simulation time 14576042 ps
CPU time 0.61 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:16 PM PDT 24
Peak memory 194628 kb
Host smart-528ec221-22ac-4cd7-bbd2-091af7b4031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008876824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2008876824
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1714185463
Short name T605
Test name
Test status
Simulation time 452245459 ps
CPU time 11.99 seconds
Started Jun 26 04:52:17 PM PDT 24
Finished Jun 26 04:52:32 PM PDT 24
Peak memory 197628 kb
Host smart-1de17e39-b54e-4a1d-9d4b-5cb07b778eb4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714185463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1714185463
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.714814389
Short name T502
Test name
Test status
Simulation time 24314929 ps
CPU time 0.64 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 194980 kb
Host smart-79d72c11-cc58-48d2-bdcd-b60b848dc2fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714814389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.714814389
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2858236403
Short name T168
Test name
Test status
Simulation time 163284619 ps
CPU time 0.83 seconds
Started Jun 26 04:52:07 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 196840 kb
Host smart-ebbdc896-667c-4e61-abf2-7a81e52b441a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858236403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2858236403
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.4008457746
Short name T207
Test name
Test status
Simulation time 75105710 ps
CPU time 0.85 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 196492 kb
Host smart-f01f0ab2-468d-43f4-86e2-c18741acd588
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008457746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.4008457746
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.980858235
Short name T188
Test name
Test status
Simulation time 1533244845 ps
CPU time 3.28 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 197612 kb
Host smart-c9683baa-8d01-4a31-b5d2-1a7df24a83de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980858235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
980858235
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1125729565
Short name T377
Test name
Test status
Simulation time 51325091 ps
CPU time 1.24 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 197324 kb
Host smart-c7669a2f-ce9b-4855-a675-ef44a90c27aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125729565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1125729565
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2745078169
Short name T475
Test name
Test status
Simulation time 32409263 ps
CPU time 1.11 seconds
Started Jun 26 04:52:17 PM PDT 24
Finished Jun 26 04:52:21 PM PDT 24
Peak memory 197348 kb
Host smart-6d838290-988f-49bd-b3d5-5e5f901ac83f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745078169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2745078169
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3887194252
Short name T607
Test name
Test status
Simulation time 574070626 ps
CPU time 4.67 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 198624 kb
Host smart-d4504e6e-1bfc-4cdd-89b7-82a2aa79915a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887194252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3887194252
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3467519311
Short name T647
Test name
Test status
Simulation time 442684856 ps
CPU time 1.23 seconds
Started Jun 26 04:52:15 PM PDT 24
Finished Jun 26 04:52:19 PM PDT 24
Peak memory 197344 kb
Host smart-f1e2c699-cd7f-4d6a-91fe-4dfbfff512f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467519311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3467519311
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1693840045
Short name T329
Test name
Test status
Simulation time 159487465 ps
CPU time 0.79 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:08 PM PDT 24
Peak memory 195776 kb
Host smart-2df4a4c5-9f69-43d2-adf5-231e14e83397
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693840045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1693840045
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.973000629
Short name T332
Test name
Test status
Simulation time 7470249914 ps
CPU time 53.67 seconds
Started Jun 26 04:52:12 PM PDT 24
Finished Jun 26 04:53:12 PM PDT 24
Peak memory 198720 kb
Host smart-422d1454-0afd-486e-b72d-ca066daa1fb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973000629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.973000629
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3071968933
Short name T707
Test name
Test status
Simulation time 22825244 ps
CPU time 0.58 seconds
Started Jun 26 04:52:04 PM PDT 24
Finished Jun 26 04:52:06 PM PDT 24
Peak memory 195448 kb
Host smart-345d1525-6715-4b0a-9646-2a48905b30cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071968933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3071968933
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4074225707
Short name T643
Test name
Test status
Simulation time 17041576 ps
CPU time 0.62 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 194612 kb
Host smart-64973f90-8b0d-4b1f-8622-0dd6ef7cd445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074225707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4074225707
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4032697506
Short name T57
Test name
Test status
Simulation time 112147392 ps
CPU time 5.64 seconds
Started Jun 26 04:52:17 PM PDT 24
Finished Jun 26 04:52:26 PM PDT 24
Peak memory 198676 kb
Host smart-7132c526-9c8d-421e-a097-43a3d0e0a12d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032697506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4032697506
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2912357632
Short name T684
Test name
Test status
Simulation time 1387209883 ps
CPU time 0.95 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 196932 kb
Host smart-6be13b92-1bf8-4621-8a1b-b26b95be1c13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912357632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2912357632
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2623621369
Short name T354
Test name
Test status
Simulation time 132021291 ps
CPU time 1.09 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 196420 kb
Host smart-fb42237a-5d12-4f85-8e22-7d04f48047ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623621369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2623621369
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.376924819
Short name T498
Test name
Test status
Simulation time 135917218 ps
CPU time 3.31 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 198660 kb
Host smart-2b81218d-2506-4889-8015-7d5925e1dfed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376924819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.376924819
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3338615392
Short name T286
Test name
Test status
Simulation time 601908221 ps
CPU time 2.98 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:24 PM PDT 24
Peak memory 197880 kb
Host smart-f8759e2c-e2ff-414d-95ff-9107a7edbfd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338615392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3338615392
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1262285275
Short name T686
Test name
Test status
Simulation time 120601860 ps
CPU time 0.99 seconds
Started Jun 26 04:52:00 PM PDT 24
Finished Jun 26 04:52:04 PM PDT 24
Peak memory 197232 kb
Host smart-f24a02f4-b033-45cf-9408-053ba1833b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262285275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1262285275
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3443499384
Short name T621
Test name
Test status
Simulation time 30931577 ps
CPU time 1.09 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:18 PM PDT 24
Peak memory 197400 kb
Host smart-9553e927-d15d-4545-ad95-d5c539740d74
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443499384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3443499384
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3287629103
Short name T19
Test name
Test status
Simulation time 248510724 ps
CPU time 3.09 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:13 PM PDT 24
Peak memory 198544 kb
Host smart-54f60828-e05e-407c-853e-d243b44e62b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287629103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3287629103
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1717063741
Short name T22
Test name
Test status
Simulation time 112871708 ps
CPU time 1.11 seconds
Started Jun 26 04:52:01 PM PDT 24
Finished Jun 26 04:52:05 PM PDT 24
Peak memory 196944 kb
Host smart-1e6ba49d-a779-403b-a690-7eab46d61618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717063741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1717063741
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.519080730
Short name T404
Test name
Test status
Simulation time 191627342 ps
CPU time 1.04 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 196176 kb
Host smart-9e68560c-9e51-4544-ab40-d4cb6c7b8a87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519080730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.519080730
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.776518224
Short name T477
Test name
Test status
Simulation time 2560441680 ps
CPU time 29.62 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:51 PM PDT 24
Peak memory 198704 kb
Host smart-1115bbd8-d232-415e-adc1-6049f6b9795b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776518224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.776518224
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.421818350
Short name T634
Test name
Test status
Simulation time 835152912389 ps
CPU time 1288.25 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 05:14:03 PM PDT 24
Peak memory 198936 kb
Host smart-d36f942a-cb31-4a1f-8a16-12a4a81b0b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=421818350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.421818350
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.947949588
Short name T150
Test name
Test status
Simulation time 30670205 ps
CPU time 0.56 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 194648 kb
Host smart-1c20f662-d8d3-4db0-b786-2c1b3bd71a8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947949588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.947949588
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2516035658
Short name T645
Test name
Test status
Simulation time 33156613 ps
CPU time 0.64 seconds
Started Jun 26 04:52:26 PM PDT 24
Finished Jun 26 04:52:30 PM PDT 24
Peak memory 195356 kb
Host smart-fab00d73-0bb0-4a8d-96d7-37f39d8fe0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516035658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2516035658
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.959556631
Short name T474
Test name
Test status
Simulation time 211256718 ps
CPU time 6.08 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 197416 kb
Host smart-8dc02642-046d-430b-b668-7251e5cc7e75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959556631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.959556631
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2023893205
Short name T33
Test name
Test status
Simulation time 219416583 ps
CPU time 0.99 seconds
Started Jun 26 04:52:32 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 197184 kb
Host smart-8a7d8423-e0c4-4011-b9c8-391af2480067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023893205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2023893205
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.4139068350
Short name T191
Test name
Test status
Simulation time 80248791 ps
CPU time 0.74 seconds
Started Jun 26 04:52:04 PM PDT 24
Finished Jun 26 04:52:06 PM PDT 24
Peak memory 196752 kb
Host smart-7b92516e-ed53-4635-ad3d-d392351bc363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139068350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.4139068350
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1249198773
Short name T297
Test name
Test status
Simulation time 104399886 ps
CPU time 0.92 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 196568 kb
Host smart-9edc1c54-afb5-47b4-a6a4-47fcba29fbb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249198773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1249198773
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3910454785
Short name T676
Test name
Test status
Simulation time 168763248 ps
CPU time 2.93 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 197816 kb
Host smart-1de525d6-f572-4983-9937-f76c07da175e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910454785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3910454785
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4140032683
Short name T383
Test name
Test status
Simulation time 80068020 ps
CPU time 0.98 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:16 PM PDT 24
Peak memory 196688 kb
Host smart-47b04292-2e84-49c8-9576-c0588e5025e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140032683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4140032683
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.992629865
Short name T497
Test name
Test status
Simulation time 133326132 ps
CPU time 1.29 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:28 PM PDT 24
Peak memory 197732 kb
Host smart-2c309f22-756c-47f7-8469-d778987fac13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992629865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.992629865
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.276352767
Short name T568
Test name
Test status
Simulation time 392667290 ps
CPU time 4.6 seconds
Started Jun 26 04:52:35 PM PDT 24
Finished Jun 26 04:52:43 PM PDT 24
Peak memory 198572 kb
Host smart-169be6a8-d51d-4c01-b8bb-7fa52729f3b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276352767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.276352767
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.281599900
Short name T318
Test name
Test status
Simulation time 60610865 ps
CPU time 1.14 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 196444 kb
Host smart-f059b442-109e-40e5-84b6-98fd201288a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281599900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.281599900
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1191793239
Short name T123
Test name
Test status
Simulation time 25134548 ps
CPU time 0.82 seconds
Started Jun 26 04:52:06 PM PDT 24
Finished Jun 26 04:52:09 PM PDT 24
Peak memory 195968 kb
Host smart-ec14310d-a408-4991-ad51-48d795c6980b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191793239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1191793239
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.789898459
Short name T514
Test name
Test status
Simulation time 19223757886 ps
CPU time 115.92 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:54:17 PM PDT 24
Peak memory 198784 kb
Host smart-a6c52710-722e-4a2e-9753-83013b35b1bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789898459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.789898459
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.948084600
Short name T542
Test name
Test status
Simulation time 59659573600 ps
CPU time 971.61 seconds
Started Jun 26 04:52:15 PM PDT 24
Finished Jun 26 05:08:29 PM PDT 24
Peak memory 198796 kb
Host smart-a911f7f6-b6ed-489c-8d9e-ab4fe65ab47b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=948084600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.948084600
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.3702583556
Short name T559
Test name
Test status
Simulation time 25218713 ps
CPU time 0.6 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 195468 kb
Host smart-63e4364e-cfe6-41bd-a0ee-20f5c4d8f503
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702583556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.3702583556
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3457938218
Short name T584
Test name
Test status
Simulation time 21192235 ps
CPU time 0.74 seconds
Started Jun 26 04:52:28 PM PDT 24
Finished Jun 26 04:52:32 PM PDT 24
Peak memory 195768 kb
Host smart-4bee3f2a-5e67-4fb6-a428-75e4c646c5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457938218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3457938218
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2223847743
Short name T380
Test name
Test status
Simulation time 984403427 ps
CPU time 27.17 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 197608 kb
Host smart-ffb69d48-e128-4ad8-be93-0b0619340749
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223847743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2223847743
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3052811124
Short name T432
Test name
Test status
Simulation time 68639309 ps
CPU time 1.02 seconds
Started Jun 26 04:52:32 PM PDT 24
Finished Jun 26 04:52:37 PM PDT 24
Peak memory 198536 kb
Host smart-ff0f56b2-946c-46b7-ac87-728dd5cbb484
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052811124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3052811124
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3472899808
Short name T151
Test name
Test status
Simulation time 332175613 ps
CPU time 0.74 seconds
Started Jun 26 04:52:20 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 195920 kb
Host smart-776868e0-9992-4541-8833-1acea8d218d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472899808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3472899808
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3012902514
Short name T196
Test name
Test status
Simulation time 94648832 ps
CPU time 0.96 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 196588 kb
Host smart-48f356ec-5e9c-46bf-9fe7-af821fc6e6c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012902514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3012902514
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.258924245
Short name T488
Test name
Test status
Simulation time 262314157 ps
CPU time 1.59 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 196572 kb
Host smart-84d098bb-5bbb-4b8e-88fa-e3537ffa3cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258924245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
258924245
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3852380582
Short name T238
Test name
Test status
Simulation time 32582499 ps
CPU time 0.72 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:35 PM PDT 24
Peak memory 196664 kb
Host smart-20fa3b0f-3ff9-4d7d-9316-d42765bc96ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852380582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3852380582
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.713595270
Short name T421
Test name
Test status
Simulation time 224809659 ps
CPU time 1.01 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 196496 kb
Host smart-2977d20e-a32a-4c62-8a2c-8caa30eb01b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713595270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.713595270
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2086391959
Short name T576
Test name
Test status
Simulation time 671345210 ps
CPU time 3.86 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 198608 kb
Host smart-bfd4b22c-4492-4c84-840b-2531f4d967f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086391959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2086391959
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3669426804
Short name T539
Test name
Test status
Simulation time 127665099 ps
CPU time 1.1 seconds
Started Jun 26 04:52:34 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 196104 kb
Host smart-5d4ec6fa-c33e-4dcb-bd80-7c0099852311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669426804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3669426804
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.657026717
Short name T608
Test name
Test status
Simulation time 100632028 ps
CPU time 1 seconds
Started Jun 26 04:52:09 PM PDT 24
Finished Jun 26 04:52:13 PM PDT 24
Peak memory 197548 kb
Host smart-c2bc29bc-abec-4f14-a260-5d9e79ebd293
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657026717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.657026717
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2437422408
Short name T149
Test name
Test status
Simulation time 16136439805 ps
CPU time 131.55 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 198756 kb
Host smart-5540d38a-9cac-4259-a006-16bb1dbc9575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437422408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2437422408
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.115280666
Short name T526
Test name
Test status
Simulation time 14260470 ps
CPU time 0.58 seconds
Started Jun 26 04:52:22 PM PDT 24
Finished Jun 26 04:52:24 PM PDT 24
Peak memory 194584 kb
Host smart-771cc2a2-2080-4f70-bfd8-855f4c86e0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115280666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.115280666
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.811511832
Short name T217
Test name
Test status
Simulation time 24827424 ps
CPU time 0.64 seconds
Started Jun 26 04:52:40 PM PDT 24
Finished Jun 26 04:52:43 PM PDT 24
Peak memory 194536 kb
Host smart-7f2214af-298e-4389-b99a-e7a8a08ba851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811511832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.811511832
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3730696526
Short name T208
Test name
Test status
Simulation time 1487661149 ps
CPU time 16.9 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 197712 kb
Host smart-13f60059-0661-402e-8417-fe0a73e81ce9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730696526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3730696526
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.845773649
Short name T333
Test name
Test status
Simulation time 47682085 ps
CPU time 0.85 seconds
Started Jun 26 04:52:14 PM PDT 24
Finished Jun 26 04:52:18 PM PDT 24
Peak memory 196544 kb
Host smart-e00f98c4-d3f2-4831-b26e-c4537622cb04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845773649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.845773649
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1412868603
Short name T586
Test name
Test status
Simulation time 88308141 ps
CPU time 0.73 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:37 PM PDT 24
Peak memory 194900 kb
Host smart-f1a1c93b-46d7-472a-9787-b2700585d312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412868603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1412868603
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.170387311
Short name T703
Test name
Test status
Simulation time 287527019 ps
CPU time 3.21 seconds
Started Jun 26 04:52:17 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 198680 kb
Host smart-0aab5359-b144-4599-90b1-eb02184bd905
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170387311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.170387311
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.408766986
Short name T11
Test name
Test status
Simulation time 247077573 ps
CPU time 1.81 seconds
Started Jun 26 04:52:18 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 197356 kb
Host smart-4c9a19c4-a734-41e4-a654-6d6727c9d6d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408766986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
408766986
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3654312190
Short name T657
Test name
Test status
Simulation time 26201590 ps
CPU time 0.99 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:33 PM PDT 24
Peak memory 196572 kb
Host smart-0cf56189-79dd-4e91-9639-ea54a874b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654312190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3654312190
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1686827155
Short name T124
Test name
Test status
Simulation time 19266493 ps
CPU time 0.66 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 194928 kb
Host smart-63711694-377d-442a-8f85-008ca7853adc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686827155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1686827155
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3687538093
Short name T538
Test name
Test status
Simulation time 1324963327 ps
CPU time 2.38 seconds
Started Jun 26 04:52:28 PM PDT 24
Finished Jun 26 04:52:33 PM PDT 24
Peak memory 198616 kb
Host smart-b403f53f-3c6c-4949-ab67-f4bbb1d4af8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687538093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3687538093
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2869494084
Short name T565
Test name
Test status
Simulation time 161719441 ps
CPU time 1.36 seconds
Started Jun 26 04:52:15 PM PDT 24
Finished Jun 26 04:52:19 PM PDT 24
Peak memory 197320 kb
Host smart-35f6765c-7d74-4337-833b-79abb8575222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869494084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2869494084
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.404661681
Short name T489
Test name
Test status
Simulation time 254310082 ps
CPU time 1.02 seconds
Started Jun 26 04:52:20 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 196076 kb
Host smart-f1698326-9dfb-4acd-9b61-b787ad34596d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404661681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.404661681
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3190084593
Short name T468
Test name
Test status
Simulation time 51146842233 ps
CPU time 90.13 seconds
Started Jun 26 04:52:17 PM PDT 24
Finished Jun 26 04:53:50 PM PDT 24
Peak memory 198716 kb
Host smart-a0525bbd-6fb7-42c8-88fe-0467868ce425
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190084593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3190084593
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2675622194
Short name T46
Test name
Test status
Simulation time 108096003 ps
CPU time 0.58 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 195356 kb
Host smart-15ccaf77-a199-44ff-8c12-9434393095f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675622194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2675622194
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2397010192
Short name T254
Test name
Test status
Simulation time 91753084 ps
CPU time 0.82 seconds
Started Jun 26 04:52:37 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 196020 kb
Host smart-85913f31-cb90-436d-a06d-2537a909ade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397010192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2397010192
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.337687901
Short name T417
Test name
Test status
Simulation time 178357667 ps
CPU time 5.94 seconds
Started Jun 26 04:52:15 PM PDT 24
Finished Jun 26 04:52:24 PM PDT 24
Peak memory 198584 kb
Host smart-a919cea3-ca46-4852-a9b7-02a5e10cd466
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337687901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.337687901
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.847828986
Short name T5
Test name
Test status
Simulation time 709750751 ps
CPU time 0.95 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 198344 kb
Host smart-32fd02d0-aafa-4142-adff-21e37a31cbb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847828986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.847828986
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.767697603
Short name T624
Test name
Test status
Simulation time 66301964 ps
CPU time 1.1 seconds
Started Jun 26 04:52:20 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 196664 kb
Host smart-cb1ae6a3-83da-4b24-aa52-cf80a435a9a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767697603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.767697603
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.209172046
Short name T412
Test name
Test status
Simulation time 61578866 ps
CPU time 2.2 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 198576 kb
Host smart-01de3d5a-70e1-45bb-9c5b-535493ea61cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209172046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.209172046
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.983894973
Short name T256
Test name
Test status
Simulation time 161352327 ps
CPU time 2.9 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:42 PM PDT 24
Peak memory 196484 kb
Host smart-b6d8d620-9598-4d68-9c1f-b450580e9c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983894973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
983894973
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.117002548
Short name T485
Test name
Test status
Simulation time 31340896 ps
CPU time 1.04 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:28 PM PDT 24
Peak memory 197216 kb
Host smart-bc573522-f442-46c4-91cd-4a3718ba2fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117002548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.117002548
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2316729222
Short name T203
Test name
Test status
Simulation time 92904164 ps
CPU time 0.79 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 197212 kb
Host smart-c9e3e169-22e3-42b7-ac50-809ff97fcf42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316729222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2316729222
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.627146378
Short name T627
Test name
Test status
Simulation time 232418853 ps
CPU time 5.41 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:46 PM PDT 24
Peak memory 198924 kb
Host smart-b8a85f70-f154-4e67-8596-40e9a220ed1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627146378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ran
dom_long_reg_writes_reg_reads.627146378
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3540390813
Short name T357
Test name
Test status
Simulation time 496735041 ps
CPU time 1.43 seconds
Started Jun 26 04:52:16 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 197464 kb
Host smart-54b1bd05-a911-45b0-8366-831d4402d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540390813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3540390813
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2336699284
Short name T581
Test name
Test status
Simulation time 57352162 ps
CPU time 1.04 seconds
Started Jun 26 04:52:32 PM PDT 24
Finished Jun 26 04:52:37 PM PDT 24
Peak memory 196340 kb
Host smart-d3806286-bd5b-444c-a04f-f491387fa374
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336699284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2336699284
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.138119652
Short name T9
Test name
Test status
Simulation time 13234010942 ps
CPU time 130.73 seconds
Started Jun 26 04:52:40 PM PDT 24
Finished Jun 26 04:54:53 PM PDT 24
Peak memory 198712 kb
Host smart-be642317-0a70-4a5d-9e8c-47cbda83035d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138119652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.138119652
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2502550491
Short name T670
Test name
Test status
Simulation time 45155682 ps
CPU time 0.59 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:42 PM PDT 24
Peak memory 194496 kb
Host smart-8da90a1d-3123-49bb-8201-983ccab0adbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502550491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2502550491
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3750670645
Short name T675
Test name
Test status
Simulation time 106508904 ps
CPU time 0.85 seconds
Started Jun 26 04:52:23 PM PDT 24
Finished Jun 26 04:52:26 PM PDT 24
Peak memory 197700 kb
Host smart-3a730533-ccbc-48a2-8d19-061f12f34ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750670645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3750670645
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1414134655
Short name T685
Test name
Test status
Simulation time 780255581 ps
CPU time 5.83 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 196100 kb
Host smart-c947a093-7e33-4eb6-84d1-a0c28fe48a3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414134655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1414134655
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2537978867
Short name T546
Test name
Test status
Simulation time 25080126 ps
CPU time 0.63 seconds
Started Jun 26 04:52:23 PM PDT 24
Finished Jun 26 04:52:26 PM PDT 24
Peak memory 195020 kb
Host smart-084ab98e-6e32-4ed4-8ca6-2acafbc843d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537978867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2537978867
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3316480378
Short name T127
Test name
Test status
Simulation time 41719808 ps
CPU time 1.15 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 196384 kb
Host smart-ee42eed6-2d12-455e-b89a-f1eb7c3be060
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316480378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3316480378
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2326894114
Short name T346
Test name
Test status
Simulation time 313838390 ps
CPU time 3.09 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 198652 kb
Host smart-f7b24846-be84-4d11-b34d-c27ba36237bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326894114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2326894114
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3814728628
Short name T663
Test name
Test status
Simulation time 1959869422 ps
CPU time 2.72 seconds
Started Jun 26 04:52:20 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 197884 kb
Host smart-f72fcbed-f1f2-4ca8-9f59-6c3dc333657f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814728628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3814728628
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3436019548
Short name T385
Test name
Test status
Simulation time 240870396 ps
CPU time 1.22 seconds
Started Jun 26 04:52:25 PM PDT 24
Finished Jun 26 04:52:29 PM PDT 24
Peak memory 198676 kb
Host smart-85ba9db4-dc0d-410c-81b9-170ed9daa9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436019548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3436019548
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.151228279
Short name T269
Test name
Test status
Simulation time 30191982 ps
CPU time 0.78 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:37 PM PDT 24
Peak memory 196840 kb
Host smart-c21e5917-11d0-4cfe-ace2-210e720308a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151228279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.151228279
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.238099535
Short name T70
Test name
Test status
Simulation time 214034673 ps
CPU time 1.57 seconds
Started Jun 26 04:52:46 PM PDT 24
Finished Jun 26 04:52:49 PM PDT 24
Peak memory 198536 kb
Host smart-e3682650-ec6a-45b2-bfdb-e026ecf4d2cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238099535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.238099535
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1936286501
Short name T665
Test name
Test status
Simulation time 51379496 ps
CPU time 0.96 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 196356 kb
Host smart-fb98fcd6-05fc-4235-8d25-a01ed0dd2119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936286501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1936286501
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2596289847
Short name T28
Test name
Test status
Simulation time 179882079 ps
CPU time 0.95 seconds
Started Jun 26 04:52:19 PM PDT 24
Finished Jun 26 04:52:22 PM PDT 24
Peak memory 197040 kb
Host smart-9412eae7-b26c-430e-8906-952482907979
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596289847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2596289847
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.897999304
Short name T597
Test name
Test status
Simulation time 54659342689 ps
CPU time 149.23 seconds
Started Jun 26 04:52:32 PM PDT 24
Finished Jun 26 04:55:05 PM PDT 24
Peak memory 198796 kb
Host smart-dadb75ea-15f0-4c56-8e14-375bc8ffb078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897999304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.897999304
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.319905975
Short name T68
Test name
Test status
Simulation time 110190077524 ps
CPU time 444.43 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:59:52 PM PDT 24
Peak memory 198820 kb
Host smart-0970d8fb-8131-46a1-8f00-b820501ba392
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=319905975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.319905975
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.691809323
Short name T599
Test name
Test status
Simulation time 15259926 ps
CPU time 0.58 seconds
Started Jun 26 04:52:22 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 194580 kb
Host smart-218abde7-3172-498f-a10f-c76d6483d9fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691809323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.691809323
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1431540320
Short name T218
Test name
Test status
Simulation time 30603934 ps
CPU time 0.9 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 197028 kb
Host smart-14d5a017-943c-45fb-a631-0103575fc0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431540320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1431540320
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.37992496
Short name T129
Test name
Test status
Simulation time 443423211 ps
CPU time 22.15 seconds
Started Jun 26 04:52:38 PM PDT 24
Finished Jun 26 04:53:03 PM PDT 24
Peak memory 196980 kb
Host smart-190d85f3-da44-4e12-917d-41de33547229
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37992496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.37992496
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1504575319
Short name T504
Test name
Test status
Simulation time 265220997 ps
CPU time 0.96 seconds
Started Jun 26 04:52:27 PM PDT 24
Finished Jun 26 04:52:31 PM PDT 24
Peak memory 198560 kb
Host smart-ea25dc79-bdfb-4e08-8199-55a1ef1109fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504575319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1504575319
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2197391060
Short name T479
Test name
Test status
Simulation time 52191939 ps
CPU time 1.35 seconds
Started Jun 26 04:52:28 PM PDT 24
Finished Jun 26 04:52:32 PM PDT 24
Peak memory 197688 kb
Host smart-1aa984d0-6231-4aed-bb6f-32a8e9fffa8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197391060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2197391060
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3759289660
Short name T585
Test name
Test status
Simulation time 69223771 ps
CPU time 2.66 seconds
Started Jun 26 04:52:46 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 198600 kb
Host smart-2f7fad78-de12-4bc2-a55f-cca75b725730
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759289660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3759289660
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.726424330
Short name T442
Test name
Test status
Simulation time 141298929 ps
CPU time 3.11 seconds
Started Jun 26 04:52:20 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 197840 kb
Host smart-211ac99a-9f51-4da9-93c8-2096d434bef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726424330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
726424330
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2422238614
Short name T543
Test name
Test status
Simulation time 174839868 ps
CPU time 1.3 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 197672 kb
Host smart-b9a887cd-4214-4247-b901-32868d611cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422238614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2422238614
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.963017733
Short name T689
Test name
Test status
Simulation time 26252503 ps
CPU time 0.8 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 196176 kb
Host smart-28417aea-a95a-449f-973a-9b72433eddc5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963017733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.963017733
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1304899079
Short name T284
Test name
Test status
Simulation time 242056768 ps
CPU time 2.19 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:35 PM PDT 24
Peak memory 198540 kb
Host smart-cd192668-deb2-4e52-a6f5-1c0dda71a8aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304899079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1304899079
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2177957222
Short name T392
Test name
Test status
Simulation time 53693343 ps
CPU time 1.2 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:35 PM PDT 24
Peak memory 196520 kb
Host smart-3027911b-14af-4246-b836-594a581b783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177957222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2177957222
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1353092442
Short name T570
Test name
Test status
Simulation time 46938679 ps
CPU time 0.82 seconds
Started Jun 26 04:52:38 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 196496 kb
Host smart-45f0cdde-0318-40df-ae32-da751ed09043
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353092442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1353092442
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3240306592
Short name T519
Test name
Test status
Simulation time 15796816067 ps
CPU time 41 seconds
Started Jun 26 04:52:34 PM PDT 24
Finished Jun 26 04:53:19 PM PDT 24
Peak memory 198620 kb
Host smart-727bb527-d3d0-48d0-96a9-984ff3a98446
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240306592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3240306592
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2956312304
Short name T579
Test name
Test status
Simulation time 73181476 ps
CPU time 0.52 seconds
Started Jun 26 04:52:23 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 194468 kb
Host smart-6d20279a-5097-4d2b-ad81-edec74fbaf68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956312304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2956312304
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.4142877493
Short name T300
Test name
Test status
Simulation time 139127358 ps
CPU time 0.78 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:28 PM PDT 24
Peak memory 195732 kb
Host smart-8dce052b-61e8-46af-b217-524f5bd7d421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142877493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.4142877493
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1705182976
Short name T278
Test name
Test status
Simulation time 1130217064 ps
CPU time 9.56 seconds
Started Jun 26 04:52:25 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 197228 kb
Host smart-b2413711-69b2-4483-bf5d-36fea8cf257f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705182976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1705182976
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3146707321
Short name T532
Test name
Test status
Simulation time 170595700 ps
CPU time 0.87 seconds
Started Jun 26 04:52:35 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 196632 kb
Host smart-b23877c7-087b-4842-bfb2-b3f5b1acb404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146707321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3146707321
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1162415215
Short name T370
Test name
Test status
Simulation time 42427646 ps
CPU time 0.73 seconds
Started Jun 26 04:52:37 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 195900 kb
Host smart-de495f65-3b4c-476c-96aa-a909972d142e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162415215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1162415215
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2665690232
Short name T139
Test name
Test status
Simulation time 498651592 ps
CPU time 3.28 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:31 PM PDT 24
Peak memory 198536 kb
Host smart-7c12d972-573e-492c-94f6-99973f06b153
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665690232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2665690232
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2339725272
Short name T639
Test name
Test status
Simulation time 66054217 ps
CPU time 1.22 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:42 PM PDT 24
Peak memory 197408 kb
Host smart-3b0b5370-9ac5-403f-9733-af98ee848034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339725272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2339725272
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1572298678
Short name T60
Test name
Test status
Simulation time 34233910 ps
CPU time 1.31 seconds
Started Jun 26 04:52:32 PM PDT 24
Finished Jun 26 04:52:37 PM PDT 24
Peak memory 197604 kb
Host smart-7dd416a9-2edb-4e25-a170-4ab22be928ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572298678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1572298678
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.927421768
Short name T668
Test name
Test status
Simulation time 38507186 ps
CPU time 0.94 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:35 PM PDT 24
Peak memory 197172 kb
Host smart-3d217a1e-9e36-415c-8241-5863cd1834be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927421768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.927421768
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.4058775764
Short name T155
Test name
Test status
Simulation time 305168401 ps
CPU time 3.7 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 198460 kb
Host smart-16e72732-096f-40e5-8834-1ac0e1be299b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058775764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.4058775764
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.946759232
Short name T271
Test name
Test status
Simulation time 96198405 ps
CPU time 0.75 seconds
Started Jun 26 04:52:43 PM PDT 24
Finished Jun 26 04:52:46 PM PDT 24
Peak memory 195860 kb
Host smart-5772253a-f636-4306-8180-ec77b524c5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946759232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.946759232
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1535033449
Short name T303
Test name
Test status
Simulation time 159909950 ps
CPU time 1.23 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 196276 kb
Host smart-7f0c15ad-b813-475e-b69b-b9b0719ee9b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535033449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1535033449
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3159895695
Short name T75
Test name
Test status
Simulation time 15399602849 ps
CPU time 211.26 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:56:22 PM PDT 24
Peak memory 198728 kb
Host smart-c932cd6a-c264-4758-9813-c157fd8f18fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159895695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3159895695
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1831830256
Short name T494
Test name
Test status
Simulation time 17094859663 ps
CPU time 467.85 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 05:00:33 PM PDT 24
Peak memory 198876 kb
Host smart-5cc0b3c8-b42d-4577-9bbb-4dc19ab4e5b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1831830256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1831830256
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2078894581
Short name T379
Test name
Test status
Simulation time 12387460 ps
CPU time 0.57 seconds
Started Jun 26 04:52:23 PM PDT 24
Finished Jun 26 04:52:27 PM PDT 24
Peak memory 194548 kb
Host smart-28c8d8ca-8786-47de-8700-312fc971a0a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078894581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2078894581
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.333112567
Short name T467
Test name
Test status
Simulation time 26826895 ps
CPU time 0.8 seconds
Started Jun 26 04:52:46 PM PDT 24
Finished Jun 26 04:52:48 PM PDT 24
Peak memory 196756 kb
Host smart-212ebb3f-bd0e-457c-8caf-7399f866b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333112567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.333112567
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.800501794
Short name T408
Test name
Test status
Simulation time 1379014715 ps
CPU time 20.31 seconds
Started Jun 26 04:52:38 PM PDT 24
Finished Jun 26 04:53:01 PM PDT 24
Peak memory 198580 kb
Host smart-2fad96dc-31cd-45c2-878b-d4a6b7e13c30
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800501794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.800501794
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2032434914
Short name T172
Test name
Test status
Simulation time 101171218 ps
CPU time 0.89 seconds
Started Jun 26 04:52:38 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 197056 kb
Host smart-716118c5-58ca-4208-8b0d-31e16042fac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032434914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2032434914
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2369053919
Short name T430
Test name
Test status
Simulation time 185969940 ps
CPU time 0.87 seconds
Started Jun 26 04:52:28 PM PDT 24
Finished Jun 26 04:52:33 PM PDT 24
Peak memory 198052 kb
Host smart-a8f3c36d-dc9f-4db7-87ec-3f18bb4a0d6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369053919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2369053919
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3807862998
Short name T349
Test name
Test status
Simulation time 233616535 ps
CPU time 2.34 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 198528 kb
Host smart-442f46e3-64c2-4c2c-80e8-178d93444b14
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807862998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3807862998
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1542442768
Short name T505
Test name
Test status
Simulation time 52076406 ps
CPU time 1.55 seconds
Started Jun 26 04:52:27 PM PDT 24
Finished Jun 26 04:52:32 PM PDT 24
Peak memory 196692 kb
Host smart-9b7b3225-02cd-43a3-a5eb-1e7f4bdf21e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542442768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1542442768
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1919736450
Short name T369
Test name
Test status
Simulation time 286373663 ps
CPU time 0.93 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:44 PM PDT 24
Peak memory 196484 kb
Host smart-7902fc71-c179-4554-9490-82c6d27db862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919736450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1919736450
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.707808615
Short name T241
Test name
Test status
Simulation time 81906469 ps
CPU time 0.68 seconds
Started Jun 26 04:52:46 PM PDT 24
Finished Jun 26 04:52:48 PM PDT 24
Peak memory 195540 kb
Host smart-d4257aaf-5414-46f0-a6e5-b10596a69621
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707808615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.707808615
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.391930420
Short name T632
Test name
Test status
Simulation time 273907695 ps
CPU time 1.56 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 198560 kb
Host smart-ae9e4cf2-15c8-4354-adde-d6771fbdebe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391930420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.391930420
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1909009060
Short name T350
Test name
Test status
Simulation time 110708970 ps
CPU time 0.77 seconds
Started Jun 26 04:52:26 PM PDT 24
Finished Jun 26 04:52:30 PM PDT 24
Peak memory 196568 kb
Host smart-0769f2d3-9c7e-4194-8a47-6b6bd85ae9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909009060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1909009060
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1316416912
Short name T424
Test name
Test status
Simulation time 316018721 ps
CPU time 1.25 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:29 PM PDT 24
Peak memory 197200 kb
Host smart-c130f37a-ac8d-4f46-a92b-87034e5c1d12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316416912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1316416912
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.74466510
Short name T712
Test name
Test status
Simulation time 15438139683 ps
CPU time 218.55 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:56:12 PM PDT 24
Peak memory 198768 kb
Host smart-e395cad1-5448-4546-ab77-6266e22ed82a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74466510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gp
io_stress_all.74466510
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.45056087
Short name T496
Test name
Test status
Simulation time 184193612 ps
CPU time 0.57 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:51:54 PM PDT 24
Peak memory 194780 kb
Host smart-87929578-1d93-43ac-9382-3ca00ffb0203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45056087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.45056087
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.475820201
Short name T213
Test name
Test status
Simulation time 51326738 ps
CPU time 0.62 seconds
Started Jun 26 04:51:42 PM PDT 24
Finished Jun 26 04:51:45 PM PDT 24
Peak memory 194516 kb
Host smart-8286e5df-5200-4be7-83da-1ab20d702a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475820201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.475820201
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2782164155
Short name T205
Test name
Test status
Simulation time 187136692 ps
CPU time 9.86 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:49 PM PDT 24
Peak memory 197232 kb
Host smart-9b3e5d5d-7f18-4c07-9863-b80e0c15c64e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782164155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2782164155
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1648675885
Short name T590
Test name
Test status
Simulation time 36544697 ps
CPU time 0.77 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:51:54 PM PDT 24
Peak memory 196368 kb
Host smart-fe68dbf4-8155-402a-a276-1111f7794ded
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648675885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1648675885
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.4114338910
Short name T225
Test name
Test status
Simulation time 1197138235 ps
CPU time 1.57 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:52 PM PDT 24
Peak memory 198640 kb
Host smart-51504f98-2972-473d-afe6-e05a02940a92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114338910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.4114338910
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.951963796
Short name T388
Test name
Test status
Simulation time 234510114 ps
CPU time 2.48 seconds
Started Jun 26 04:52:03 PM PDT 24
Finished Jun 26 04:52:07 PM PDT 24
Peak memory 198688 kb
Host smart-b79d30cd-cae2-41bc-9e75-687e1d70c64b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951963796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.951963796
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2963062448
Short name T272
Test name
Test status
Simulation time 205349975 ps
CPU time 1.29 seconds
Started Jun 26 04:51:47 PM PDT 24
Finished Jun 26 04:51:49 PM PDT 24
Peak memory 196468 kb
Host smart-435442df-5c41-40f6-b113-2119fd126944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963062448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2963062448
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3224406665
Short name T674
Test name
Test status
Simulation time 98773291 ps
CPU time 0.81 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:51 PM PDT 24
Peak memory 196084 kb
Host smart-4dae8a22-c7f3-4651-b670-d8bd25a10f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224406665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3224406665
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.951546877
Short name T109
Test name
Test status
Simulation time 23715788 ps
CPU time 0.72 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:51:56 PM PDT 24
Peak memory 196028 kb
Host smart-dbaab1c9-785f-4c96-9b49-781432be0c7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951546877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.951546877
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1703449780
Short name T1
Test name
Test status
Simulation time 262179540 ps
CPU time 3.14 seconds
Started Jun 26 04:51:40 PM PDT 24
Finished Jun 26 04:51:46 PM PDT 24
Peak memory 198500 kb
Host smart-811da495-32db-4cd6-a135-7cfc4ff1539f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703449780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1703449780
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2203649312
Short name T42
Test name
Test status
Simulation time 2002295097 ps
CPU time 0.93 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:39 PM PDT 24
Peak memory 214236 kb
Host smart-54030434-93d7-4593-9284-db7d1d6d5b8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203649312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2203649312
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2778946911
Short name T553
Test name
Test status
Simulation time 221285337 ps
CPU time 1.09 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:51:59 PM PDT 24
Peak memory 196244 kb
Host smart-225d46de-4ccb-418a-92fa-fa77f84513cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778946911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2778946911
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.123605760
Short name T246
Test name
Test status
Simulation time 594010666 ps
CPU time 1.35 seconds
Started Jun 26 04:52:09 PM PDT 24
Finished Jun 26 04:52:13 PM PDT 24
Peak memory 196136 kb
Host smart-6b32fce5-18e2-4101-aed8-13b3f206f1df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123605760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.123605760
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1892767993
Short name T414
Test name
Test status
Simulation time 27106345592 ps
CPU time 168.45 seconds
Started Jun 26 04:52:04 PM PDT 24
Finished Jun 26 04:54:54 PM PDT 24
Peak memory 198752 kb
Host smart-f5c9b143-d6bf-4819-a809-77a30d5fd561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892767993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1892767993
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.4138076133
Short name T437
Test name
Test status
Simulation time 55951598177 ps
CPU time 729.71 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 05:04:04 PM PDT 24
Peak memory 198868 kb
Host smart-5a390c01-010a-4d7c-ab8f-182ea6305f08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4138076133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.4138076133
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.984179241
Short name T285
Test name
Test status
Simulation time 66040918 ps
CPU time 0.59 seconds
Started Jun 26 04:52:35 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 194532 kb
Host smart-8476d3e2-57c1-41df-8991-9c57c203d2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984179241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.984179241
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2296180239
Short name T653
Test name
Test status
Simulation time 23462250 ps
CPU time 0.75 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:42 PM PDT 24
Peak memory 196564 kb
Host smart-ff2b95cd-014b-4f7b-9528-9adf5e6a9695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296180239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2296180239
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3045187378
Short name T324
Test name
Test status
Simulation time 422491665 ps
CPU time 5.91 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 196212 kb
Host smart-55a6da04-c8e7-4582-9f19-82c452adf3c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045187378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3045187378
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1772977124
Short name T407
Test name
Test status
Simulation time 182669666 ps
CPU time 0.77 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:33 PM PDT 24
Peak memory 196508 kb
Host smart-3ac1ff0c-66c3-4f2f-9bf4-2ea5837e9233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772977124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1772977124
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.4194404145
Short name T694
Test name
Test status
Simulation time 75816642 ps
CPU time 1.31 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 197692 kb
Host smart-1001f067-7d3e-4574-a013-bfac06afa48c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194404145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.4194404145
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.702824905
Short name T476
Test name
Test status
Simulation time 144590525 ps
CPU time 2.9 seconds
Started Jun 26 04:52:26 PM PDT 24
Finished Jun 26 04:52:32 PM PDT 24
Peak memory 198764 kb
Host smart-63f82fb2-6d32-446a-aedc-44af1b269d99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702824905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.gpio_intr_with_filter_rand_intr_event.702824905
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1673187778
Short name T702
Test name
Test status
Simulation time 121667822 ps
CPU time 2.36 seconds
Started Jun 26 04:52:34 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 197688 kb
Host smart-8c64d785-d92d-4dcc-b57e-b5055c3b7acb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673187778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1673187778
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1221121930
Short name T358
Test name
Test status
Simulation time 349495244 ps
CPU time 1.18 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:35 PM PDT 24
Peak memory 197204 kb
Host smart-82235f0e-2e85-4758-b8a1-9bbf3792a10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221121930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1221121930
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1872861961
Short name T693
Test name
Test status
Simulation time 95799263 ps
CPU time 1.16 seconds
Started Jun 26 04:52:35 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 196564 kb
Host smart-2e2d133e-63f7-4227-8dcb-fd2004f4e287
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872861961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1872861961
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3448311364
Short name T460
Test name
Test status
Simulation time 155577779 ps
CPU time 2.44 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:44 PM PDT 24
Peak memory 198620 kb
Host smart-a0cde834-5f1f-4198-9756-11e24ef07ca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448311364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3448311364
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.810059076
Short name T692
Test name
Test status
Simulation time 39923170 ps
CPU time 1.09 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:51 PM PDT 24
Peak memory 196428 kb
Host smart-f6b27042-e026-4587-ac17-ce04befbc813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810059076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.810059076
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1633615703
Short name T230
Test name
Test status
Simulation time 196068347 ps
CPU time 0.94 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:36 PM PDT 24
Peak memory 196128 kb
Host smart-57469e5a-41ed-4e89-89d7-fc24b74b40ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633615703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1633615703
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_alert_test.582040190
Short name T367
Test name
Test status
Simulation time 11796118 ps
CPU time 0.62 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 195352 kb
Host smart-a1e69559-e3e4-4a71-a541-e7a072994f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582040190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.582040190
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.4011022433
Short name T234
Test name
Test status
Simulation time 127467651 ps
CPU time 0.74 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 196512 kb
Host smart-5e0f62b7-91cb-42f7-903a-1b0aecc56e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011022433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.4011022433
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.888570862
Short name T604
Test name
Test status
Simulation time 887289107 ps
CPU time 6.57 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 197532 kb
Host smart-5dd5d4e6-2239-4abc-9ede-6e69742893e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888570862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.888570862
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2819771846
Short name T594
Test name
Test status
Simulation time 1327409397 ps
CPU time 1.12 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 197116 kb
Host smart-91b87463-79a5-42d5-b442-eb9d6521c258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819771846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2819771846
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.6740326
Short name T77
Test name
Test status
Simulation time 203661798 ps
CPU time 1.18 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 196488 kb
Host smart-28e58338-0a0e-465e-975f-30af4493316a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6740326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.6740326
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1275941354
Short name T520
Test name
Test status
Simulation time 77691482 ps
CPU time 3.17 seconds
Started Jun 26 04:52:25 PM PDT 24
Finished Jun 26 04:52:31 PM PDT 24
Peak memory 198676 kb
Host smart-2abed8a3-4a45-49bd-9edc-06d0eb1f31bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275941354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1275941354
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.161733958
Short name T396
Test name
Test status
Simulation time 145714549 ps
CPU time 3.18 seconds
Started Jun 26 04:52:22 PM PDT 24
Finished Jun 26 04:52:27 PM PDT 24
Peak memory 197720 kb
Host smart-4476c299-c173-4a1a-982d-c943593a605a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161733958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
161733958
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3861655780
Short name T221
Test name
Test status
Simulation time 83462583 ps
CPU time 1.02 seconds
Started Jun 26 04:52:30 PM PDT 24
Finished Jun 26 04:52:35 PM PDT 24
Peak memory 196500 kb
Host smart-b6a6a345-adef-4687-9611-9d91816bb475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861655780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3861655780
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2593063000
Short name T426
Test name
Test status
Simulation time 100233311 ps
CPU time 1.36 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:37 PM PDT 24
Peak memory 198612 kb
Host smart-24ccbde4-9743-4e1c-a940-fa1b5c66a001
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593063000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2593063000
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2894184435
Short name T32
Test name
Test status
Simulation time 143551015 ps
CPU time 2.66 seconds
Started Jun 26 04:52:28 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 198592 kb
Host smart-4e8592b0-8bf9-4ffe-a350-a0be5f0e96a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894184435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2894184435
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2049885692
Short name T215
Test name
Test status
Simulation time 67174844 ps
CPU time 1.26 seconds
Started Jun 26 04:52:37 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 197032 kb
Host smart-b2048fc7-27eb-40f1-9cfd-55fd5527f83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049885692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2049885692
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.514898307
Short name T309
Test name
Test status
Simulation time 274787849 ps
CPU time 1.13 seconds
Started Jun 26 04:52:35 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 196472 kb
Host smart-69d573ee-fe53-4501-92d6-4074a4f4c897
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514898307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.514898307
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.307369380
Short name T6
Test name
Test status
Simulation time 33476860733 ps
CPU time 171.15 seconds
Started Jun 26 04:52:32 PM PDT 24
Finished Jun 26 04:55:27 PM PDT 24
Peak memory 198752 kb
Host smart-b29255df-6bc5-4bc9-a21a-24025c2d32c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307369380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.307369380
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.3099678999
Short name T705
Test name
Test status
Simulation time 49174658217 ps
CPU time 387.44 seconds
Started Jun 26 04:52:28 PM PDT 24
Finished Jun 26 04:59:00 PM PDT 24
Peak memory 207040 kb
Host smart-4508cfeb-1935-4ca3-8195-089cab33a3b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3099678999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.3099678999
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.965952773
Short name T339
Test name
Test status
Simulation time 42494477 ps
CPU time 0.58 seconds
Started Jun 26 04:52:34 PM PDT 24
Finished Jun 26 04:52:38 PM PDT 24
Peak memory 195264 kb
Host smart-bbcdb3d3-9ae6-4805-89e6-dbd8d57967b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965952773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.965952773
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1026066215
Short name T137
Test name
Test status
Simulation time 153954480 ps
CPU time 0.89 seconds
Started Jun 26 04:52:27 PM PDT 24
Finished Jun 26 04:52:31 PM PDT 24
Peak memory 197696 kb
Host smart-d2569407-0ff4-4714-8ae4-b1cf6013cf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026066215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1026066215
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1146092699
Short name T296
Test name
Test status
Simulation time 840284675 ps
CPU time 11.44 seconds
Started Jun 26 04:52:28 PM PDT 24
Finished Jun 26 04:52:43 PM PDT 24
Peak memory 197348 kb
Host smart-7f3bcc7b-d1fa-4965-905a-9b8b11e7bf08
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146092699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1146092699
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3973475574
Short name T431
Test name
Test status
Simulation time 71003609 ps
CPU time 1.03 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 197080 kb
Host smart-533a68a5-4f92-4230-b7a3-61e60b651368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973475574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3973475574
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1900679299
Short name T336
Test name
Test status
Simulation time 318351352 ps
CPU time 1.24 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:42 PM PDT 24
Peak memory 197776 kb
Host smart-11f7ae40-5338-4eaf-9c20-964d405cfe16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900679299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1900679299
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1581348322
Short name T695
Test name
Test status
Simulation time 58447520 ps
CPU time 2.42 seconds
Started Jun 26 04:52:34 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 198604 kb
Host smart-fc82c552-201b-4904-9de5-2bbbb895d027
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581348322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1581348322
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3854986149
Short name T26
Test name
Test status
Simulation time 86656214 ps
CPU time 1.45 seconds
Started Jun 26 04:52:31 PM PDT 24
Finished Jun 26 04:52:37 PM PDT 24
Peak memory 196664 kb
Host smart-035fa234-8382-4aab-838e-cf40ac1e2cb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854986149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3854986149
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3234253201
Short name T397
Test name
Test status
Simulation time 20270306 ps
CPU time 0.68 seconds
Started Jun 26 04:52:37 PM PDT 24
Finished Jun 26 04:52:40 PM PDT 24
Peak memory 195636 kb
Host smart-7e04ad10-35e7-494f-b0fd-bd03bbeee718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234253201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3234253201
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.127697797
Short name T662
Test name
Test status
Simulation time 38528906 ps
CPU time 1.01 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:51 PM PDT 24
Peak memory 196712 kb
Host smart-3d1d5313-2ac4-4e1f-a7fa-4f60958abbc1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127697797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.127697797
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2827804132
Short name T330
Test name
Test status
Simulation time 735259506 ps
CPU time 5.3 seconds
Started Jun 26 04:52:41 PM PDT 24
Finished Jun 26 04:52:48 PM PDT 24
Peak memory 198632 kb
Host smart-d281e981-22e9-4e29-82e5-4c0c7a97c081
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827804132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2827804132
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1910186473
Short name T649
Test name
Test status
Simulation time 192254096 ps
CPU time 1.15 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:28 PM PDT 24
Peak memory 196916 kb
Host smart-f3d43037-3ae5-4a21-bb06-2fb2c75db290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910186473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1910186473
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3283352232
Short name T261
Test name
Test status
Simulation time 31405292 ps
CPU time 0.93 seconds
Started Jun 26 04:52:24 PM PDT 24
Finished Jun 26 04:52:29 PM PDT 24
Peak memory 196844 kb
Host smart-b1787db2-97b4-46b7-82d4-4d666f29decd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283352232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3283352232
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.84698903
Short name T530
Test name
Test status
Simulation time 6864348756 ps
CPU time 170.94 seconds
Started Jun 26 04:52:26 PM PDT 24
Finished Jun 26 04:55:20 PM PDT 24
Peak memory 198572 kb
Host smart-5568bbe6-22f3-4b57-9f8f-5076c24effcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84698903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gp
io_stress_all.84698903
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2801160316
Short name T420
Test name
Test status
Simulation time 23255124 ps
CPU time 0.58 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:39 PM PDT 24
Peak memory 194836 kb
Host smart-4fb2112f-106b-463f-8c7d-38e2d2493772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801160316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2801160316
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1879148899
Short name T587
Test name
Test status
Simulation time 52720698 ps
CPU time 0.71 seconds
Started Jun 26 04:52:47 PM PDT 24
Finished Jun 26 04:52:49 PM PDT 24
Peak memory 195520 kb
Host smart-344cdfd7-61f1-4df5-8ffd-cd6853504e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879148899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1879148899
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.821550329
Short name T223
Test name
Test status
Simulation time 239923903 ps
CPU time 11.83 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 197592 kb
Host smart-8e3a185f-5f43-4083-8876-cd758c12f924
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821550329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.821550329
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3704905208
Short name T135
Test name
Test status
Simulation time 84894170 ps
CPU time 1.06 seconds
Started Jun 26 04:52:46 PM PDT 24
Finished Jun 26 04:52:48 PM PDT 24
Peak memory 197152 kb
Host smart-6422a77e-f609-41bc-a14e-e5165fb3edeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704905208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3704905208
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.671514129
Short name T169
Test name
Test status
Simulation time 97034704 ps
CPU time 1.24 seconds
Started Jun 26 04:52:38 PM PDT 24
Finished Jun 26 04:52:42 PM PDT 24
Peak memory 197324 kb
Host smart-62b6da7d-5031-4031-900c-ac44016ee6c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671514129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.671514129
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1305960907
Short name T275
Test name
Test status
Simulation time 631292654 ps
CPU time 3.13 seconds
Started Jun 26 04:52:36 PM PDT 24
Finished Jun 26 04:52:42 PM PDT 24
Peak memory 198608 kb
Host smart-8f277a79-7e41-4f4c-908d-56841904bcfb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305960907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1305960907
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.889148651
Short name T611
Test name
Test status
Simulation time 386071895 ps
CPU time 2.72 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:48 PM PDT 24
Peak memory 198668 kb
Host smart-998c5cdf-9dcd-4302-a037-13022aff4162
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889148651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
889148651
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2704300509
Short name T561
Test name
Test status
Simulation time 146798732 ps
CPU time 1 seconds
Started Jun 26 04:52:41 PM PDT 24
Finished Jun 26 04:52:44 PM PDT 24
Peak memory 196592 kb
Host smart-c40718b1-594a-41ea-8929-510801a8dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704300509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2704300509
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.36793539
Short name T128
Test name
Test status
Simulation time 67691076 ps
CPU time 1.04 seconds
Started Jun 26 04:52:43 PM PDT 24
Finished Jun 26 04:52:46 PM PDT 24
Peak memory 197096 kb
Host smart-75ebc9a9-3d32-4a37-b43c-cadc0f04b1cf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36793539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup_
pulldown.36793539
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1339872923
Short name T620
Test name
Test status
Simulation time 355078407 ps
CPU time 2.72 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 198480 kb
Host smart-bf91480a-e50c-49f9-839b-91c55c44c344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339872923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1339872923
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1674737937
Short name T16
Test name
Test status
Simulation time 39280915 ps
CPU time 1.19 seconds
Started Jun 26 04:52:29 PM PDT 24
Finished Jun 26 04:52:34 PM PDT 24
Peak memory 198596 kb
Host smart-6eebc5b0-0713-4835-9014-dcf12b067680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674737937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1674737937
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.572266290
Short name T672
Test name
Test status
Simulation time 173887246 ps
CPU time 1.27 seconds
Started Jun 26 04:52:39 PM PDT 24
Finished Jun 26 04:52:43 PM PDT 24
Peak memory 197388 kb
Host smart-1b28efbb-ce61-4cf6-8085-60c90d7a54c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572266290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.572266290
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.757854152
Short name T573
Test name
Test status
Simulation time 3481013372 ps
CPU time 85.73 seconds
Started Jun 26 04:52:41 PM PDT 24
Finished Jun 26 04:54:09 PM PDT 24
Peak memory 198740 kb
Host smart-64aa4031-50a6-41d5-b71e-89612cbcfa21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757854152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.757854152
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2207748921
Short name T148
Test name
Test status
Simulation time 17801422 ps
CPU time 0.58 seconds
Started Jun 26 04:52:47 PM PDT 24
Finished Jun 26 04:52:49 PM PDT 24
Peak memory 195228 kb
Host smart-7b550c01-30a4-413b-ab50-1d2d8671074f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207748921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2207748921
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1291410289
Short name T378
Test name
Test status
Simulation time 112998344 ps
CPU time 0.8 seconds
Started Jun 26 04:52:42 PM PDT 24
Finished Jun 26 04:52:44 PM PDT 24
Peak memory 196712 kb
Host smart-2766590a-0dbf-4946-b877-9adaa94f0bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291410289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1291410289
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4174100122
Short name T314
Test name
Test status
Simulation time 696410551 ps
CPU time 8.83 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:55 PM PDT 24
Peak memory 196184 kb
Host smart-28cb621f-e6c8-45e8-972e-4c2cd6cdd045
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174100122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4174100122
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3250224121
Short name T617
Test name
Test status
Simulation time 93320905 ps
CPU time 0.89 seconds
Started Jun 26 04:52:42 PM PDT 24
Finished Jun 26 04:52:45 PM PDT 24
Peak memory 197788 kb
Host smart-cc1302bf-84ff-4b02-9748-7362284753bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250224121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3250224121
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3157597483
Short name T381
Test name
Test status
Simulation time 97008137 ps
CPU time 0.72 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:51 PM PDT 24
Peak memory 194996 kb
Host smart-9b7eb2e5-0d12-4994-9200-6a921396e4c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157597483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3157597483
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3382742498
Short name T403
Test name
Test status
Simulation time 169254972 ps
CPU time 3.33 seconds
Started Jun 26 04:52:51 PM PDT 24
Finished Jun 26 04:52:56 PM PDT 24
Peak memory 198580 kb
Host smart-fe1f4194-c24b-407b-b19b-2dfb632da7dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382742498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3382742498
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.359580425
Short name T144
Test name
Test status
Simulation time 383828899 ps
CPU time 1.66 seconds
Started Jun 26 04:52:42 PM PDT 24
Finished Jun 26 04:52:45 PM PDT 24
Peak memory 196600 kb
Host smart-79bea42a-00b2-4218-b6c4-9727aa120bde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359580425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
359580425
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3673455637
Short name T690
Test name
Test status
Simulation time 23535131 ps
CPU time 0.78 seconds
Started Jun 26 04:52:52 PM PDT 24
Finished Jun 26 04:52:55 PM PDT 24
Peak memory 196064 kb
Host smart-e92c42f9-67a0-4424-80f2-ac5914c2fc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673455637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3673455637
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2841835967
Short name T666
Test name
Test status
Simulation time 276700978 ps
CPU time 1.08 seconds
Started Jun 26 04:52:47 PM PDT 24
Finished Jun 26 04:52:49 PM PDT 24
Peak memory 197460 kb
Host smart-6fc6c35d-2284-45f2-a4be-a96bb4361aaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841835967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2841835967
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3120092861
Short name T631
Test name
Test status
Simulation time 406500123 ps
CPU time 4.65 seconds
Started Jun 26 04:52:33 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 198624 kb
Host smart-5ee3cdd7-373d-425e-a1aa-d076ec1e809d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120092861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3120092861
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.68367745
Short name T108
Test name
Test status
Simulation time 351211791 ps
CPU time 1.17 seconds
Started Jun 26 04:52:40 PM PDT 24
Finished Jun 26 04:52:43 PM PDT 24
Peak memory 196548 kb
Host smart-f6e089db-0092-4dfb-bd65-c3cb3d165cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68367745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.68367745
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2016661098
Short name T443
Test name
Test status
Simulation time 825386818 ps
CPU time 1.24 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:47 PM PDT 24
Peak memory 196204 kb
Host smart-267a59da-b259-4f70-b2d4-4be22abbe19c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016661098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2016661098
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.4010460100
Short name T635
Test name
Test status
Simulation time 9550100930 ps
CPU time 130.78 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:55:01 PM PDT 24
Peak memory 198744 kb
Host smart-08372714-34e0-4dc7-b5cd-2f47323d918f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010460100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.4010460100
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2970198184
Short name T248
Test name
Test status
Simulation time 31155819 ps
CPU time 0.62 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 194384 kb
Host smart-271c2298-b936-4e94-9254-95ed576488f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970198184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2970198184
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3805862867
Short name T541
Test name
Test status
Simulation time 29853963 ps
CPU time 0.81 seconds
Started Jun 26 04:52:56 PM PDT 24
Finished Jun 26 04:53:00 PM PDT 24
Peak memory 195912 kb
Host smart-0b6619f2-d17c-4a44-8a75-7d1aae8a8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805862867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3805862867
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2106730544
Short name T61
Test name
Test status
Simulation time 126530025 ps
CPU time 6.4 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 198640 kb
Host smart-fccc11a9-e7e4-464f-8420-b09565799d15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106730544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2106730544
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3995498302
Short name T465
Test name
Test status
Simulation time 22252032 ps
CPU time 0.64 seconds
Started Jun 26 04:52:50 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 195096 kb
Host smart-80890567-732e-47f8-b305-a99753290d0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995498302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3995498302
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1654736907
Short name T133
Test name
Test status
Simulation time 24072504 ps
CPU time 0.79 seconds
Started Jun 26 04:52:51 PM PDT 24
Finished Jun 26 04:52:54 PM PDT 24
Peak memory 196040 kb
Host smart-3f29ff6f-1c5d-431d-a591-e0a73b0ef5da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654736907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1654736907
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.193960062
Short name T638
Test name
Test status
Simulation time 96256819 ps
CPU time 1.21 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:47 PM PDT 24
Peak memory 198632 kb
Host smart-b1947674-cfd1-4739-a9ce-8982ccf39ac5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193960062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.193960062
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.129082173
Short name T481
Test name
Test status
Simulation time 127260293 ps
CPU time 2.06 seconds
Started Jun 26 04:52:52 PM PDT 24
Finished Jun 26 04:52:56 PM PDT 24
Peak memory 197548 kb
Host smart-6eb06022-7a6a-4910-9324-ff2fac94ddc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129082173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
129082173
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.4183300679
Short name T567
Test name
Test status
Simulation time 257152913 ps
CPU time 1.04 seconds
Started Jun 26 04:52:45 PM PDT 24
Finished Jun 26 04:52:48 PM PDT 24
Peak memory 196684 kb
Host smart-dc2abbb4-1950-475d-be55-9d8934fb5e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183300679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.4183300679
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.990173436
Short name T266
Test name
Test status
Simulation time 61026262 ps
CPU time 1.19 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:51 PM PDT 24
Peak memory 196756 kb
Host smart-ca39cd4c-f6de-4003-abd5-b4f8eb3e2152
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990173436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.990173436
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.663628402
Short name T687
Test name
Test status
Simulation time 267388253 ps
CPU time 3.38 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:53:00 PM PDT 24
Peak memory 198628 kb
Host smart-5584c8af-3013-48fa-8acc-63d74b746ac3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663628402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.663628402
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2366794076
Short name T461
Test name
Test status
Simulation time 75102718 ps
CPU time 1.12 seconds
Started Jun 26 04:52:43 PM PDT 24
Finished Jun 26 04:52:46 PM PDT 24
Peak memory 197264 kb
Host smart-71ee3398-0a66-461c-85d3-8dfa02397e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366794076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2366794076
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.750046203
Short name T71
Test name
Test status
Simulation time 26618405 ps
CPU time 0.83 seconds
Started Jun 26 04:52:37 PM PDT 24
Finished Jun 26 04:52:41 PM PDT 24
Peak memory 195956 kb
Host smart-cc4b5b3a-f5ef-4f3a-b3ae-417785c8c171
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750046203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.750046203
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.810495367
Short name T373
Test name
Test status
Simulation time 8728136303 ps
CPU time 49.75 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:53:46 PM PDT 24
Peak memory 198676 kb
Host smart-312319c5-2ca3-421e-aab8-84a17746fe59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810495367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.810495367
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2119298354
Short name T680
Test name
Test status
Simulation time 30712323 ps
CPU time 0.56 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 194336 kb
Host smart-63a3a667-8b12-4dd6-8e4c-c6e0aea2bda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119298354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2119298354
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3631988525
Short name T679
Test name
Test status
Simulation time 30865036 ps
CPU time 0.93 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:52:56 PM PDT 24
Peak memory 196524 kb
Host smart-94d9fc84-fa1a-4893-ad79-347173982b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631988525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3631988525
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1550254521
Short name T304
Test name
Test status
Simulation time 863177410 ps
CPU time 10.6 seconds
Started Jun 26 04:52:42 PM PDT 24
Finished Jun 26 04:52:54 PM PDT 24
Peak memory 196200 kb
Host smart-019a8d95-414b-4615-bf37-a81dc1a11eff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550254521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1550254521
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.636522846
Short name T360
Test name
Test status
Simulation time 56708461 ps
CPU time 0.72 seconds
Started Jun 26 04:52:47 PM PDT 24
Finished Jun 26 04:52:49 PM PDT 24
Peak memory 195164 kb
Host smart-f91bcdaa-85c8-4d52-b1bf-c8d37e1c07d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636522846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.636522846
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3813861446
Short name T279
Test name
Test status
Simulation time 109737876 ps
CPU time 0.98 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:47 PM PDT 24
Peak memory 196508 kb
Host smart-93c5d523-7fe5-4c49-91fe-e35ca8430936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813861446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3813861446
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3718028411
Short name T259
Test name
Test status
Simulation time 342933863 ps
CPU time 3.38 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:52:55 PM PDT 24
Peak memory 198636 kb
Host smart-9b89a0f3-28f4-4417-ae3e-9828c5273450
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718028411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3718028411
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3240780696
Short name T348
Test name
Test status
Simulation time 181539384 ps
CPU time 3.15 seconds
Started Jun 26 04:52:45 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 197748 kb
Host smart-7b670b41-4ece-4de1-b0e9-046995e00e98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240780696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3240780696
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.74322811
Short name T30
Test name
Test status
Simulation time 78020801 ps
CPU time 0.8 seconds
Started Jun 26 04:52:43 PM PDT 24
Finished Jun 26 04:52:45 PM PDT 24
Peak memory 197152 kb
Host smart-22e02b83-4d7e-4a7c-b81f-50504747f88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74322811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.74322811
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2659396503
Short name T59
Test name
Test status
Simulation time 157980518 ps
CPU time 1.12 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:47 PM PDT 24
Peak memory 196724 kb
Host smart-3b6bbcbe-eef1-41b4-ad48-64521b74239d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659396503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2659396503
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3234352879
Short name T452
Test name
Test status
Simulation time 1382168310 ps
CPU time 4.61 seconds
Started Jun 26 04:52:43 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 198572 kb
Host smart-cdcc53fe-607c-445a-8c27-d317270c0f77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234352879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3234352879
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2974455179
Short name T525
Test name
Test status
Simulation time 58542438 ps
CPU time 0.87 seconds
Started Jun 26 04:52:42 PM PDT 24
Finished Jun 26 04:52:44 PM PDT 24
Peak memory 197916 kb
Host smart-c2f457d1-3671-421c-afe0-e3b988a44e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974455179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2974455179
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.2944885371
Short name T506
Test name
Test status
Simulation time 350988440 ps
CPU time 1.24 seconds
Started Jun 26 04:52:47 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 197172 kb
Host smart-adc61cc8-463f-488c-8015-ecb39fcae1c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944885371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.2944885371
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1017104731
Short name T713
Test name
Test status
Simulation time 55484522415 ps
CPU time 145.69 seconds
Started Jun 26 04:52:42 PM PDT 24
Finished Jun 26 04:55:10 PM PDT 24
Peak memory 198708 kb
Host smart-3f829236-cd4f-4b77-b83d-56b2c98377f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017104731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1017104731
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3417991476
Short name T640
Test name
Test status
Simulation time 22249920 ps
CPU time 0.54 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 194584 kb
Host smart-8ed80069-6ad5-4d26-b6a5-c0f6935347c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417991476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3417991476
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2230965111
Short name T301
Test name
Test status
Simulation time 52026184 ps
CPU time 0.9 seconds
Started Jun 26 04:52:40 PM PDT 24
Finished Jun 26 04:52:43 PM PDT 24
Peak memory 197284 kb
Host smart-a4493a21-0b2c-418c-b770-97e8461d870b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230965111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2230965111
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2554933308
Short name T212
Test name
Test status
Simulation time 628473783 ps
CPU time 21.92 seconds
Started Jun 26 04:52:45 PM PDT 24
Finished Jun 26 04:53:09 PM PDT 24
Peak memory 198540 kb
Host smart-faa8eed8-d3e1-4ff5-836b-7f277087435a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554933308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2554933308
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.21132608
Short name T455
Test name
Test status
Simulation time 1037324530 ps
CPU time 0.87 seconds
Started Jun 26 04:52:43 PM PDT 24
Finished Jun 26 04:52:46 PM PDT 24
Peak memory 197316 kb
Host smart-9ccd5d07-ddcd-4c3a-a946-82a84e1f8759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21132608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.21132608
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2596124118
Short name T449
Test name
Test status
Simulation time 156583350 ps
CPU time 1.35 seconds
Started Jun 26 04:52:43 PM PDT 24
Finished Jun 26 04:52:46 PM PDT 24
Peak memory 197628 kb
Host smart-9c3ed455-e66f-4698-ab74-2e5edef0a8d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596124118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2596124118
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.984551563
Short name T17
Test name
Test status
Simulation time 295024565 ps
CPU time 1.94 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 197672 kb
Host smart-4ca4676f-d4b7-4856-930d-90290f5966ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984551563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
984551563
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3357725093
Short name T163
Test name
Test status
Simulation time 83556178 ps
CPU time 0.99 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 197348 kb
Host smart-3d2232a9-dd3b-4d85-b332-a26300945c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357725093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3357725093
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.396060295
Short name T464
Test name
Test status
Simulation time 102698159 ps
CPU time 1.05 seconds
Started Jun 26 04:52:50 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 196700 kb
Host smart-4808b8a2-cb97-47bf-85d1-a02c26a73d27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396060295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.396060295
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1050658081
Short name T170
Test name
Test status
Simulation time 48776427 ps
CPU time 1.31 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:52:56 PM PDT 24
Peak memory 198520 kb
Host smart-12010244-ad4b-4509-ac5c-94fcf6ce99f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050658081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1050658081
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1729728052
Short name T678
Test name
Test status
Simulation time 340762093 ps
CPU time 1.31 seconds
Started Jun 26 04:52:47 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 197280 kb
Host smart-f84930a0-c797-4503-a1de-1051800838e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729728052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1729728052
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1052606357
Short name T283
Test name
Test status
Simulation time 44231989 ps
CPU time 0.91 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:51 PM PDT 24
Peak memory 195944 kb
Host smart-92d398b5-1b96-440a-a5e8-159147f91e14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052606357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1052606357
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1734590405
Short name T311
Test name
Test status
Simulation time 120538615234 ps
CPU time 235.79 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 198716 kb
Host smart-d01791d9-899b-4166-b1b2-d02459f35b09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734590405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1734590405
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.4242099652
Short name T44
Test name
Test status
Simulation time 19191416 ps
CPU time 0.57 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:01 PM PDT 24
Peak memory 195360 kb
Host smart-038af96d-7e73-4a62-ab35-01db6a2eaa7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242099652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.4242099652
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2543964744
Short name T189
Test name
Test status
Simulation time 47689294 ps
CPU time 0.85 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:53:10 PM PDT 24
Peak memory 196900 kb
Host smart-1b9c17d6-7fde-40d9-a03d-fecce3f28d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543964744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2543964744
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1930996986
Short name T355
Test name
Test status
Simulation time 905448962 ps
CPU time 25.23 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:53:20 PM PDT 24
Peak memory 197724 kb
Host smart-699253d4-fa30-4709-a5fa-91d858684687
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930996986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1930996986
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.825604545
Short name T591
Test name
Test status
Simulation time 69125023 ps
CPU time 0.78 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:52:50 PM PDT 24
Peak memory 196324 kb
Host smart-8958a96c-cd66-4f5a-99e6-e65211d0449b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825604545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.825604545
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.778305671
Short name T13
Test name
Test status
Simulation time 294787203 ps
CPU time 1.27 seconds
Started Jun 26 04:53:01 PM PDT 24
Finished Jun 26 04:53:05 PM PDT 24
Peak memory 198720 kb
Host smart-3250161f-92b2-4fb6-bfcc-4d2503d3aef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778305671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.778305671
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2747707130
Short name T345
Test name
Test status
Simulation time 96032506 ps
CPU time 1.89 seconds
Started Jun 26 04:52:59 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 198676 kb
Host smart-91044e9c-81cc-40d7-a54e-dc5fe5aad96d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747707130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2747707130
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3921478393
Short name T683
Test name
Test status
Simulation time 196283731 ps
CPU time 2.05 seconds
Started Jun 26 04:53:02 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 196748 kb
Host smart-0fdbdeae-27c5-4d4e-bd0c-7e8d1a6b11dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921478393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3921478393
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.4212546483
Short name T175
Test name
Test status
Simulation time 33594999 ps
CPU time 0.8 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:46 PM PDT 24
Peak memory 196240 kb
Host smart-ebeeb06d-205e-4587-b299-46b5e3f80b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212546483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.4212546483
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1649597867
Short name T523
Test name
Test status
Simulation time 32112763 ps
CPU time 1.14 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 196756 kb
Host smart-acebbb90-84e8-478e-b6e0-e3d7a2ba0bc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649597867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1649597867
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.4013747501
Short name T518
Test name
Test status
Simulation time 167972849 ps
CPU time 2.8 seconds
Started Jun 26 04:53:08 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 198580 kb
Host smart-631a8f9b-6632-4777-89fe-fcfcc420c693
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013747501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.4013747501
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.4235331224
Short name T327
Test name
Test status
Simulation time 163631519 ps
CPU time 1.35 seconds
Started Jun 26 04:52:51 PM PDT 24
Finished Jun 26 04:52:54 PM PDT 24
Peak memory 197460 kb
Host smart-4fa530d2-9407-47f2-9881-31d14a724344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235331224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.4235331224
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.794264257
Short name T231
Test name
Test status
Simulation time 336375200 ps
CPU time 1.23 seconds
Started Jun 26 04:52:44 PM PDT 24
Finished Jun 26 04:52:47 PM PDT 24
Peak memory 197532 kb
Host smart-d8226947-31ec-4d33-b6de-0447934b1018
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794264257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.794264257
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3509037143
Short name T362
Test name
Test status
Simulation time 16801277449 ps
CPU time 92.79 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:54:34 PM PDT 24
Peak memory 198788 kb
Host smart-f4330ef7-e8e9-4812-8ef8-48ac3884dff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509037143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3509037143
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2272572130
Short name T45
Test name
Test status
Simulation time 16159602 ps
CPU time 0.57 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 194660 kb
Host smart-1ed13e51-633c-46f7-829e-2d52b52db4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272572130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2272572130
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3600144703
Short name T73
Test name
Test status
Simulation time 22588863 ps
CPU time 0.76 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:09 PM PDT 24
Peak memory 196536 kb
Host smart-80899c31-b513-4ca8-94f5-0f44f01791b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600144703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3600144703
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3766375458
Short name T29
Test name
Test status
Simulation time 197780644 ps
CPU time 5.75 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:07 PM PDT 24
Peak memory 197544 kb
Host smart-15efd509-c232-4d78-8bc0-b877502c78b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766375458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3766375458
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2072528554
Short name T509
Test name
Test status
Simulation time 94499171 ps
CPU time 0.68 seconds
Started Jun 26 04:52:56 PM PDT 24
Finished Jun 26 04:53:00 PM PDT 24
Peak memory 195220 kb
Host smart-1893f674-98c5-4418-a394-6b9201926320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072528554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2072528554
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2570578649
Short name T274
Test name
Test status
Simulation time 70938258 ps
CPU time 0.65 seconds
Started Jun 26 04:52:52 PM PDT 24
Finished Jun 26 04:52:54 PM PDT 24
Peak memory 195592 kb
Host smart-17504db3-a5d6-4367-b9e4-63dde7323789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570578649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2570578649
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3103005868
Short name T453
Test name
Test status
Simulation time 40977002 ps
CPU time 1.64 seconds
Started Jun 26 04:52:55 PM PDT 24
Finished Jun 26 04:53:01 PM PDT 24
Peak memory 196872 kb
Host smart-dd1b855b-f0a9-4ede-9333-f3129bb006db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103005868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3103005868
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1917728368
Short name T557
Test name
Test status
Simulation time 596485342 ps
CPU time 1.85 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:52:57 PM PDT 24
Peak memory 196384 kb
Host smart-cde3694b-5dd9-42ab-995e-b22f3c3b49cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917728368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1917728368
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4013977574
Short name T486
Test name
Test status
Simulation time 27569321 ps
CPU time 0.79 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:02 PM PDT 24
Peak memory 196088 kb
Host smart-f8a3fbcb-9f99-4a6c-82ed-f71a0c4033b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013977574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4013977574
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2867489370
Short name T210
Test name
Test status
Simulation time 26983419 ps
CPU time 0.77 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 196140 kb
Host smart-a92eeecd-393f-469d-a79f-4a3e656db2d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867489370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2867489370
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3346979059
Short name T131
Test name
Test status
Simulation time 236301387 ps
CPU time 3.75 seconds
Started Jun 26 04:53:08 PM PDT 24
Finished Jun 26 04:53:14 PM PDT 24
Peak memory 198648 kb
Host smart-a204753f-3f67-4741-b0a7-f07a73d18727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346979059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3346979059
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.796035004
Short name T136
Test name
Test status
Simulation time 130690124 ps
CPU time 0.95 seconds
Started Jun 26 04:53:02 PM PDT 24
Finished Jun 26 04:53:05 PM PDT 24
Peak memory 197120 kb
Host smart-7c3f9bcb-8948-44f2-9b3b-d2f644fe3d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796035004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.796035004
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2147071789
Short name T229
Test name
Test status
Simulation time 158708171 ps
CPU time 0.99 seconds
Started Jun 26 04:53:03 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 196344 kb
Host smart-3cb3d3c9-517b-452b-9828-7824bb931e78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147071789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2147071789
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3707129885
Short name T165
Test name
Test status
Simulation time 229058238866 ps
CPU time 192.52 seconds
Started Jun 26 04:52:48 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 198784 kb
Host smart-008fb971-f767-4f63-8448-5edaf5d83db0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707129885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3707129885
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1507093984
Short name T67
Test name
Test status
Simulation time 19610140921 ps
CPU time 531.71 seconds
Started Jun 26 04:52:57 PM PDT 24
Finished Jun 26 05:01:51 PM PDT 24
Peak memory 198856 kb
Host smart-f4f7d7f5-d593-419a-95fd-be711bcf9467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1507093984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1507093984
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.342571152
Short name T503
Test name
Test status
Simulation time 13582099 ps
CPU time 0.55 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:58 PM PDT 24
Peak memory 195560 kb
Host smart-2640790e-3be6-4b5e-bc19-9d3a0810df88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342571152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.342571152
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.4242326979
Short name T237
Test name
Test status
Simulation time 16318856 ps
CPU time 0.63 seconds
Started Jun 26 04:51:41 PM PDT 24
Finished Jun 26 04:51:44 PM PDT 24
Peak memory 194608 kb
Host smart-5a82d822-36ac-4320-b1f0-05d7368e9a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242326979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.4242326979
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1996194536
Short name T441
Test name
Test status
Simulation time 2232831768 ps
CPU time 14.37 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 196184 kb
Host smart-e67460db-a068-43f1-b93d-88ef000dfb0e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996194536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1996194536
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2907514839
Short name T222
Test name
Test status
Simulation time 212745521 ps
CPU time 0.95 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:51:44 PM PDT 24
Peak memory 198548 kb
Host smart-e65af236-f8e0-4f48-b92e-3d9bd5a247dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907514839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2907514839
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3399279052
Short name T267
Test name
Test status
Simulation time 36181582 ps
CPU time 0.82 seconds
Started Jun 26 04:51:42 PM PDT 24
Finished Jun 26 04:51:45 PM PDT 24
Peak memory 196900 kb
Host smart-c33651f1-9823-4ca1-a3b3-47c7a881a3ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399279052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3399279052
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.76073532
Short name T575
Test name
Test status
Simulation time 498808988 ps
CPU time 3.21 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:51:45 PM PDT 24
Peak memory 198676 kb
Host smart-87385d46-3568-46c7-8dcf-690721d54096
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76073532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.gpio_intr_with_filter_rand_intr_event.76073532
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1163987637
Short name T493
Test name
Test status
Simulation time 624699349 ps
CPU time 3.41 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:51:46 PM PDT 24
Peak memory 197720 kb
Host smart-1398a431-195d-4040-8f78-fafe3683e884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163987637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1163987637
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3113380368
Short name T199
Test name
Test status
Simulation time 34785957 ps
CPU time 0.78 seconds
Started Jun 26 04:52:04 PM PDT 24
Finished Jun 26 04:52:07 PM PDT 24
Peak memory 197232 kb
Host smart-cd09f385-05d6-4f27-99a1-319687705e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113380368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3113380368
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3987057932
Short name T619
Test name
Test status
Simulation time 31009949 ps
CPU time 0.81 seconds
Started Jun 26 04:51:39 PM PDT 24
Finished Jun 26 04:51:43 PM PDT 24
Peak memory 197136 kb
Host smart-b0480067-4e86-4361-9da8-70505aead004
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987057932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3987057932
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1433441312
Short name T571
Test name
Test status
Simulation time 634902047 ps
CPU time 5.27 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:44 PM PDT 24
Peak memory 198512 kb
Host smart-a22e1823-db20-4003-818a-e75555e656da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433441312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1433441312
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1776544727
Short name T55
Test name
Test status
Simulation time 90230799 ps
CPU time 0.98 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:58 PM PDT 24
Peak memory 215284 kb
Host smart-a71f58a1-60e4-4198-bc6f-596e79f29a87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776544727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1776544727
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2260315915
Short name T214
Test name
Test status
Simulation time 118605884 ps
CPU time 1.12 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:52 PM PDT 24
Peak memory 197220 kb
Host smart-1c0df1e9-d634-45de-9280-e1de3b14067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260315915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2260315915
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.134742033
Short name T669
Test name
Test status
Simulation time 51701072 ps
CPU time 0.97 seconds
Started Jun 26 04:51:35 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 196120 kb
Host smart-7639d070-3958-4f4f-8457-6e7573954164
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134742033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.134742033
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3178320100
Short name T615
Test name
Test status
Simulation time 11976669602 ps
CPU time 140.93 seconds
Started Jun 26 04:52:06 PM PDT 24
Finished Jun 26 04:54:29 PM PDT 24
Peak memory 198764 kb
Host smart-f7180540-b156-4d2c-94fb-442719df22e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178320100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3178320100
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2401558994
Short name T580
Test name
Test status
Simulation time 36073269 ps
CPU time 0.58 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:53:09 PM PDT 24
Peak memory 194536 kb
Host smart-72643083-4c10-43bf-94f2-71eb7fc75091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401558994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2401558994
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3092744148
Short name T588
Test name
Test status
Simulation time 125052911 ps
CPU time 0.86 seconds
Started Jun 26 04:53:04 PM PDT 24
Finished Jun 26 04:53:07 PM PDT 24
Peak memory 196304 kb
Host smart-44149f67-3f9c-47bd-b137-a20dc434bab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092744148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3092744148
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2869002321
Short name T190
Test name
Test status
Simulation time 288609438 ps
CPU time 8.64 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:53:00 PM PDT 24
Peak memory 197652 kb
Host smart-0ba03199-b68d-40d0-aa58-94a2fe2ffe66
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869002321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2869002321
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3533813294
Short name T651
Test name
Test status
Simulation time 237155241 ps
CPU time 1.06 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 197056 kb
Host smart-d74f9bb6-120f-42c6-a6d9-bc873bd5bf3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533813294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3533813294
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2767644125
Short name T478
Test name
Test status
Simulation time 138775469 ps
CPU time 1.13 seconds
Started Jun 26 04:53:01 PM PDT 24
Finished Jun 26 04:53:05 PM PDT 24
Peak memory 196420 kb
Host smart-16b4e5bd-730a-4850-b5ca-d7a565a86ce1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767644125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2767644125
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.100294510
Short name T537
Test name
Test status
Simulation time 128292371 ps
CPU time 1.48 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 196964 kb
Host smart-905400f0-b6a7-4259-b4f0-c6aa77b61c47
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100294510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.100294510
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2719943021
Short name T375
Test name
Test status
Simulation time 61193923 ps
CPU time 1.48 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:03 PM PDT 24
Peak memory 196776 kb
Host smart-701a558d-6470-45bb-955f-0839167ff5af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719943021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2719943021
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2829352614
Short name T143
Test name
Test status
Simulation time 95625215 ps
CPU time 1.23 seconds
Started Jun 26 04:53:04 PM PDT 24
Finished Jun 26 04:53:07 PM PDT 24
Peak memory 196452 kb
Host smart-27d34209-63d9-4658-84f2-bb6bce45c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829352614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2829352614
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1877376865
Short name T180
Test name
Test status
Simulation time 58100807 ps
CPU time 1.22 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:52:56 PM PDT 24
Peak memory 197636 kb
Host smart-af20b80c-361a-4cbd-957f-2f93e9eb7713
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877376865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1877376865
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1286145320
Short name T260
Test name
Test status
Simulation time 868476863 ps
CPU time 3.68 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 198832 kb
Host smart-189820ef-04e0-4b28-b9cc-e269a9422f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286145320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1286145320
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.4285008839
Short name T192
Test name
Test status
Simulation time 49070700 ps
CPU time 0.93 seconds
Started Jun 26 04:53:01 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 197040 kb
Host smart-925b5872-53fb-4737-b6aa-1e74a0f9239a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285008839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.4285008839
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3546747118
Short name T511
Test name
Test status
Simulation time 60975690 ps
CPU time 1.24 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:52:52 PM PDT 24
Peak memory 198612 kb
Host smart-3af82435-edb1-477b-9027-b4ce86371b75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546747118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3546747118
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2093060262
Short name T7
Test name
Test status
Simulation time 10512905276 ps
CPU time 56.6 seconds
Started Jun 26 04:52:50 PM PDT 24
Finished Jun 26 04:53:49 PM PDT 24
Peak memory 198708 kb
Host smart-4f4caedf-33a2-4284-b336-e0deffab0217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093060262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2093060262
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.349899375
Short name T69
Test name
Test status
Simulation time 40231995330 ps
CPU time 1021.58 seconds
Started Jun 26 04:52:56 PM PDT 24
Finished Jun 26 05:10:01 PM PDT 24
Peak memory 198800 kb
Host smart-cd3eb1a5-493b-4e98-bb15-863ddea08778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=349899375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.349899375
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1519475676
Short name T598
Test name
Test status
Simulation time 16466006 ps
CPU time 0.58 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:08 PM PDT 24
Peak memory 194544 kb
Host smart-9448c6e0-4284-4c0c-993c-cfe15f8c010e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519475676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1519475676
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.55057704
Short name T641
Test name
Test status
Simulation time 17668289 ps
CPU time 0.66 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:52:56 PM PDT 24
Peak memory 194692 kb
Host smart-793305ca-5818-4899-b676-9c6e30b47c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55057704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.55057704
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.4073565134
Short name T602
Test name
Test status
Simulation time 653735271 ps
CPU time 9.85 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:18 PM PDT 24
Peak memory 197908 kb
Host smart-76c0031b-040a-4612-b43d-a881f7d42aec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073565134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.4073565134
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3452066043
Short name T490
Test name
Test status
Simulation time 186540605 ps
CPU time 0.81 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 196484 kb
Host smart-04af855c-096d-488c-b9c6-e626f6aa02dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452066043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3452066043
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3656945859
Short name T501
Test name
Test status
Simulation time 387287360 ps
CPU time 1.16 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:03 PM PDT 24
Peak memory 196572 kb
Host smart-69656804-2ef1-485b-9309-dbc0d0e60bd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656945859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3656945859
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2159690119
Short name T277
Test name
Test status
Simulation time 61150549 ps
CPU time 2.22 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:59 PM PDT 24
Peak memory 198588 kb
Host smart-ea2bdf53-f3e1-44e0-ac98-05f3d046d6fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159690119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2159690119
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2775960712
Short name T250
Test name
Test status
Simulation time 61300899 ps
CPU time 0.86 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 195140 kb
Host smart-3a8f75f9-f5c9-4f96-8dd9-75a08823affd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775960712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2775960712
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3028423950
Short name T157
Test name
Test status
Simulation time 174241082 ps
CPU time 1.38 seconds
Started Jun 26 04:52:50 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 198628 kb
Host smart-a7623262-6569-4851-993b-7f5e2abc2faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028423950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3028423950
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2665467698
Short name T569
Test name
Test status
Simulation time 116247682 ps
CPU time 1.21 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 197644 kb
Host smart-d1628157-50c2-4822-812b-fa89d50a2643
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665467698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2665467698
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2569626511
Short name T419
Test name
Test status
Simulation time 765291374 ps
CPU time 2.38 seconds
Started Jun 26 04:52:55 PM PDT 24
Finished Jun 26 04:53:01 PM PDT 24
Peak memory 197052 kb
Host smart-a1999b1e-de95-42f0-98e5-22d408aae0de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569626511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2569626511
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.874940984
Short name T492
Test name
Test status
Simulation time 87293718 ps
CPU time 1.34 seconds
Started Jun 26 04:53:04 PM PDT 24
Finished Jun 26 04:53:08 PM PDT 24
Peak memory 197372 kb
Host smart-d248b44e-121d-4e16-875a-5bdd42b1f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874940984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.874940984
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.741230532
Short name T162
Test name
Test status
Simulation time 66319771 ps
CPU time 1.03 seconds
Started Jun 26 04:52:54 PM PDT 24
Finished Jun 26 04:52:58 PM PDT 24
Peak memory 196132 kb
Host smart-3dc3120c-8892-4941-b20f-41a8f1814aec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741230532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.741230532
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2635588912
Short name T161
Test name
Test status
Simulation time 4966820495 ps
CPU time 32.67 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:53:29 PM PDT 24
Peak memory 198792 kb
Host smart-fed467d3-b73f-41bf-9872-c5cb4644774b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635588912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2635588912
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.876496160
Short name T483
Test name
Test status
Simulation time 23638655277 ps
CPU time 545.63 seconds
Started Jun 26 04:52:50 PM PDT 24
Finished Jun 26 05:01:58 PM PDT 24
Peak memory 198916 kb
Host smart-8538e972-65aa-49e2-8508-434ff8064592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=876496160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.876496160
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.776509942
Short name T531
Test name
Test status
Simulation time 49276014 ps
CPU time 0.58 seconds
Started Jun 26 04:53:08 PM PDT 24
Finished Jun 26 04:53:11 PM PDT 24
Peak memory 194892 kb
Host smart-b71e6eb3-cbbe-4dca-aa0b-4d00218afdb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776509942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.776509942
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.679642119
Short name T560
Test name
Test status
Simulation time 25448205 ps
CPU time 0.64 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:53:09 PM PDT 24
Peak memory 195440 kb
Host smart-8bb14122-c606-4fc3-b9c8-56a1e00b0210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679642119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.679642119
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2420887138
Short name T347
Test name
Test status
Simulation time 1053400744 ps
CPU time 18.49 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:26 PM PDT 24
Peak memory 198564 kb
Host smart-5ddc3c45-04f4-403a-a18a-56b5757c0283
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420887138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2420887138
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.396054205
Short name T470
Test name
Test status
Simulation time 162218419 ps
CPU time 0.73 seconds
Started Jun 26 04:52:56 PM PDT 24
Finished Jun 26 04:53:00 PM PDT 24
Peak memory 195464 kb
Host smart-bc0ce087-a2e0-4e15-9136-17e899c87edd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396054205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.396054205
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2460348503
Short name T268
Test name
Test status
Simulation time 71706014 ps
CPU time 0.82 seconds
Started Jun 26 04:52:49 PM PDT 24
Finished Jun 26 04:52:52 PM PDT 24
Peak memory 195948 kb
Host smart-3f6b9110-247e-43c8-b6df-c098ccba7947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460348503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2460348503
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1323274912
Short name T667
Test name
Test status
Simulation time 34773770 ps
CPU time 1.34 seconds
Started Jun 26 04:52:50 PM PDT 24
Finished Jun 26 04:52:53 PM PDT 24
Peak memory 197080 kb
Host smart-82e08939-6f84-4020-a157-5d0fc54f9fa4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323274912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1323274912
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2586872138
Short name T195
Test name
Test status
Simulation time 163835760 ps
CPU time 1.2 seconds
Started Jun 26 04:53:01 PM PDT 24
Finished Jun 26 04:53:05 PM PDT 24
Peak memory 197492 kb
Host smart-f418dc94-d86d-437e-85dc-644e4061e1c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586872138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2586872138
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.346515295
Short name T390
Test name
Test status
Simulation time 95439982 ps
CPU time 1.06 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:02 PM PDT 24
Peak memory 196608 kb
Host smart-a31042f8-854c-43ea-841e-96bcc382d8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346515295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.346515295
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1806173682
Short name T471
Test name
Test status
Simulation time 60114476 ps
CPU time 0.82 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:02 PM PDT 24
Peak memory 196036 kb
Host smart-ab92a9fc-3524-4660-bd1f-d477c266ab09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806173682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1806173682
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3771099859
Short name T171
Test name
Test status
Simulation time 309430398 ps
CPU time 3.15 seconds
Started Jun 26 04:52:59 PM PDT 24
Finished Jun 26 04:53:05 PM PDT 24
Peak memory 198568 kb
Host smart-f0189003-b896-4235-922d-ce3863f8e052
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771099859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3771099859
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1841285302
Short name T698
Test name
Test status
Simulation time 155164378 ps
CPU time 1.18 seconds
Started Jun 26 04:52:58 PM PDT 24
Finished Jun 26 04:53:02 PM PDT 24
Peak memory 196340 kb
Host smart-46455d1b-2e9f-4ad1-85b6-a3f6dbc0130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841285302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1841285302
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3502776585
Short name T673
Test name
Test status
Simulation time 197861136 ps
CPU time 1.07 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:03 PM PDT 24
Peak memory 196812 kb
Host smart-95bed1fc-05e1-4642-81c4-aff8a71f0043
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502776585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3502776585
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1368103299
Short name T319
Test name
Test status
Simulation time 10548102232 ps
CPU time 139.5 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:55:29 PM PDT 24
Peak memory 198684 kb
Host smart-29279747-6997-4087-97b3-b5235a36f712
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368103299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1368103299
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1218574399
Short name T422
Test name
Test status
Simulation time 21831319 ps
CPU time 0.57 seconds
Started Jun 26 04:52:59 PM PDT 24
Finished Jun 26 04:53:03 PM PDT 24
Peak memory 194648 kb
Host smart-c439189d-2674-4662-acf0-09909cdba313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218574399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1218574399
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2046815699
Short name T648
Test name
Test status
Simulation time 14760619 ps
CPU time 0.62 seconds
Started Jun 26 04:52:59 PM PDT 24
Finished Jun 26 04:53:02 PM PDT 24
Peak memory 194588 kb
Host smart-46d2fc86-1bf1-4523-b62c-23ab7f1f47d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046815699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2046815699
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.4120314896
Short name T512
Test name
Test status
Simulation time 100363097 ps
CPU time 3.31 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:11 PM PDT 24
Peak memory 197100 kb
Host smart-621f665f-6673-44ff-8b68-4a2e8defb269
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120314896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.4120314896
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1497157974
Short name T480
Test name
Test status
Simulation time 128023653 ps
CPU time 0.74 seconds
Started Jun 26 04:53:13 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 196336 kb
Host smart-08bd5884-3686-4c8f-ba42-586c26aec034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497157974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1497157974
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.204522950
Short name T618
Test name
Test status
Simulation time 315508108 ps
CPU time 1.27 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 198532 kb
Host smart-f2e9d537-c4e3-410c-a184-91897ec023d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204522950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.204522950
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2531617831
Short name T312
Test name
Test status
Simulation time 170376194 ps
CPU time 1.68 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:15 PM PDT 24
Peak memory 198652 kb
Host smart-80bec198-a968-4705-8ee2-796f3f2b3796
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531617831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2531617831
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.192338786
Short name T413
Test name
Test status
Simulation time 454860453 ps
CPU time 3.77 seconds
Started Jun 26 04:53:29 PM PDT 24
Finished Jun 26 04:53:38 PM PDT 24
Peak memory 197704 kb
Host smart-7c016419-d3fd-480d-a8b6-43e857523c70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192338786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
192338786
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1148720398
Short name T622
Test name
Test status
Simulation time 65385141 ps
CPU time 0.63 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 194908 kb
Host smart-a4adffb2-8eba-412d-bd14-cb61c9287f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148720398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1148720398
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3436343698
Short name T289
Test name
Test status
Simulation time 290554270 ps
CPU time 1.16 seconds
Started Jun 26 04:52:59 PM PDT 24
Finished Jun 26 04:53:03 PM PDT 24
Peak memory 197772 kb
Host smart-35c008ea-0811-489a-9180-40102a71174b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436343698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3436343698
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2148743284
Short name T141
Test name
Test status
Simulation time 78945496 ps
CPU time 1.19 seconds
Started Jun 26 04:53:05 PM PDT 24
Finished Jun 26 04:53:08 PM PDT 24
Peak memory 198536 kb
Host smart-86c70037-7ebf-4d99-a3df-22a495250a98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148743284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2148743284
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.697905054
Short name T307
Test name
Test status
Simulation time 149388109 ps
CPU time 1.15 seconds
Started Jun 26 04:52:51 PM PDT 24
Finished Jun 26 04:52:54 PM PDT 24
Peak memory 196444 kb
Host smart-7445dcba-44bc-4257-9b55-bf77a56a4510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697905054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.697905054
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3025900526
Short name T343
Test name
Test status
Simulation time 47140676 ps
CPU time 1.16 seconds
Started Jun 26 04:52:53 PM PDT 24
Finished Jun 26 04:52:57 PM PDT 24
Peak memory 196284 kb
Host smart-b9f93d58-b504-4085-88e8-ed0ea67f3ce5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025900526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3025900526
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.703117800
Short name T316
Test name
Test status
Simulation time 57262264696 ps
CPU time 204.52 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:56:27 PM PDT 24
Peak memory 198708 kb
Host smart-c2fee8ef-f9cd-4f3a-9ff9-33e2b268cf64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703117800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.703117800
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1131845071
Short name T513
Test name
Test status
Simulation time 19159482 ps
CPU time 0.58 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 195372 kb
Host smart-0d786668-7c4a-4d57-967c-f55d7c737051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131845071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1131845071
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.80898044
Short name T681
Test name
Test status
Simulation time 154911912 ps
CPU time 0.65 seconds
Started Jun 26 04:53:04 PM PDT 24
Finished Jun 26 04:53:07 PM PDT 24
Peak memory 194740 kb
Host smart-51017e4b-84fe-4d33-b854-f0f660bf0bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80898044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.80898044
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2680372190
Short name T384
Test name
Test status
Simulation time 567335660 ps
CPU time 19.39 seconds
Started Jun 26 04:53:05 PM PDT 24
Finished Jun 26 04:53:26 PM PDT 24
Peak memory 198584 kb
Host smart-84c94244-d994-4eb9-b614-f568399ddf4f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680372190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2680372190
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1721248672
Short name T402
Test name
Test status
Simulation time 201542322 ps
CPU time 0.88 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:09 PM PDT 24
Peak memory 197292 kb
Host smart-f354e30e-ab59-4eb9-98ab-9b1754268c05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721248672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1721248672
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1781700789
Short name T551
Test name
Test status
Simulation time 225443621 ps
CPU time 0.98 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 196524 kb
Host smart-bf28e3e9-fcbe-4467-997c-4650a7fd109d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781700789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1781700789
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1429236256
Short name T589
Test name
Test status
Simulation time 220563392 ps
CPU time 2.33 seconds
Started Jun 26 04:52:59 PM PDT 24
Finished Jun 26 04:53:05 PM PDT 24
Peak memory 198760 kb
Host smart-166db685-bc20-4c7c-8fa8-0efeed469b01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429236256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1429236256
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1245653348
Short name T270
Test name
Test status
Simulation time 542512722 ps
CPU time 1.47 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:15 PM PDT 24
Peak memory 196744 kb
Host smart-d5efd4c1-8005-431d-bc6f-d21bd592202c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245653348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1245653348
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3175124859
Short name T416
Test name
Test status
Simulation time 195773461 ps
CPU time 1.14 seconds
Started Jun 26 04:53:03 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 197512 kb
Host smart-11c06e1f-9b13-49b3-b664-73b3efc6d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175124859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3175124859
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1712195268
Short name T183
Test name
Test status
Simulation time 78056520 ps
CPU time 0.92 seconds
Started Jun 26 04:53:05 PM PDT 24
Finished Jun 26 04:53:08 PM PDT 24
Peak memory 197400 kb
Host smart-ac080ae9-202e-4ce6-ab07-e04c89cf2f62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712195268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1712195268
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2654591650
Short name T4
Test name
Test status
Simulation time 436808799 ps
CPU time 5.33 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:08 PM PDT 24
Peak memory 198572 kb
Host smart-758a7501-95d0-4ed1-b11f-e939884e3395
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654591650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2654591650
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3838452265
Short name T206
Test name
Test status
Simulation time 46990668 ps
CPU time 1.09 seconds
Started Jun 26 04:53:13 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 196652 kb
Host smart-9a839b42-b907-49e6-bbfb-f415e23485de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838452265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3838452265
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2371259911
Short name T444
Test name
Test status
Simulation time 52686492 ps
CPU time 1.11 seconds
Started Jun 26 04:53:11 PM PDT 24
Finished Jun 26 04:53:15 PM PDT 24
Peak memory 197036 kb
Host smart-6738a89e-6da0-431b-a903-99903b536e3e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371259911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2371259911
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.554100927
Short name T181
Test name
Test status
Simulation time 3962598290 ps
CPU time 51.75 seconds
Started Jun 26 04:53:04 PM PDT 24
Finished Jun 26 04:53:57 PM PDT 24
Peak memory 198656 kb
Host smart-c7382997-0a91-4106-b8f8-f0dc9a09a494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554100927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.554100927
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.623286598
Short name T656
Test name
Test status
Simulation time 13577868 ps
CPU time 0.58 seconds
Started Jun 26 04:53:20 PM PDT 24
Finished Jun 26 04:53:21 PM PDT 24
Peak memory 194880 kb
Host smart-8b6464bf-c9e5-4bf9-987d-17f52e68f749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623286598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.623286598
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.826650306
Short name T361
Test name
Test status
Simulation time 44150035 ps
CPU time 0.91 seconds
Started Jun 26 04:53:03 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 196204 kb
Host smart-daf7efed-dd7d-4ed3-a789-c6d78db5e764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826650306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.826650306
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.641969222
Short name T613
Test name
Test status
Simulation time 928312037 ps
CPU time 25.18 seconds
Started Jun 26 04:53:19 PM PDT 24
Finished Jun 26 04:53:45 PM PDT 24
Peak memory 197188 kb
Host smart-a3e80e5f-1c09-4ea0-b2e6-c1009f9dacfb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641969222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.641969222
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.163111723
Short name T227
Test name
Test status
Simulation time 38435235 ps
CPU time 0.61 seconds
Started Jun 26 04:53:13 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 195932 kb
Host smart-bdaebd97-93f9-4ea0-a7c2-5eb09bff2654
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163111723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.163111723
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1415379414
Short name T325
Test name
Test status
Simulation time 244752595 ps
CPU time 0.78 seconds
Started Jun 26 04:53:53 PM PDT 24
Finished Jun 26 04:53:56 PM PDT 24
Peak memory 196076 kb
Host smart-8f6758dd-15fc-4ad1-90f3-38748ead3ee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415379414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1415379414
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.890222424
Short name T524
Test name
Test status
Simulation time 87442385 ps
CPU time 3.5 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 198784 kb
Host smart-4494961d-aa88-4fdd-8da6-673faee02655
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890222424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.890222424
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2783012005
Short name T126
Test name
Test status
Simulation time 102387195 ps
CPU time 2.06 seconds
Started Jun 26 04:53:03 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 197024 kb
Host smart-c7c2378e-b13b-4d72-9c72-e1d0e21effea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783012005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2783012005
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3126975586
Short name T194
Test name
Test status
Simulation time 322869469 ps
CPU time 1.38 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:09 PM PDT 24
Peak memory 197608 kb
Host smart-b5e34f6a-2c04-47f4-b936-d92a9ca7b929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126975586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3126975586
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1632573143
Short name T264
Test name
Test status
Simulation time 33924520 ps
CPU time 0.87 seconds
Started Jun 26 04:53:02 PM PDT 24
Finished Jun 26 04:53:05 PM PDT 24
Peak memory 197316 kb
Host smart-d73e84da-0cd0-4491-a1cf-224e7a556182
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632573143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1632573143
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1463107128
Short name T554
Test name
Test status
Simulation time 925041399 ps
CPU time 6.36 seconds
Started Jun 26 04:53:15 PM PDT 24
Finished Jun 26 04:53:24 PM PDT 24
Peak memory 198496 kb
Host smart-92bbc43a-88d8-4572-bd10-1a807d2f2e59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463107128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1463107128
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1877653825
Short name T295
Test name
Test status
Simulation time 48220992 ps
CPU time 1.15 seconds
Started Jun 26 04:53:19 PM PDT 24
Finished Jun 26 04:53:21 PM PDT 24
Peak memory 196244 kb
Host smart-7072f4d0-7477-40ec-96a0-bec15137bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877653825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1877653825
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3509775955
Short name T290
Test name
Test status
Simulation time 267446305 ps
CPU time 1.4 seconds
Started Jun 26 04:53:02 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 198640 kb
Host smart-13d04854-9926-4fd7-a62c-3c995b4db761
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509775955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3509775955
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2298340183
Short name T111
Test name
Test status
Simulation time 158164672983 ps
CPU time 136.73 seconds
Started Jun 26 04:53:15 PM PDT 24
Finished Jun 26 04:55:35 PM PDT 24
Peak memory 199044 kb
Host smart-15eb9834-f99a-4596-8636-9df9bb2cd8ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298340183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2298340183
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1592493730
Short name T64
Test name
Test status
Simulation time 94866058737 ps
CPU time 2203.95 seconds
Started Jun 26 04:53:08 PM PDT 24
Finished Jun 26 05:29:55 PM PDT 24
Peak memory 198928 kb
Host smart-846ab3ea-bcb4-4716-87db-d2a4f55ac3c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1592493730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1592493730
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2778185155
Short name T652
Test name
Test status
Simulation time 134096627 ps
CPU time 0.59 seconds
Started Jun 26 04:53:30 PM PDT 24
Finished Jun 26 04:53:35 PM PDT 24
Peak memory 194624 kb
Host smart-b4332096-46a6-436c-90ac-490734fce473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778185155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2778185155
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1926659406
Short name T368
Test name
Test status
Simulation time 37269451 ps
CPU time 0.83 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 195972 kb
Host smart-980315a1-6fda-4ec4-97b4-b4dd7e72e59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926659406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1926659406
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.149444629
Short name T306
Test name
Test status
Simulation time 517547237 ps
CPU time 6.26 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:19 PM PDT 24
Peak memory 198660 kb
Host smart-a9efb598-c411-4340-b6f8-4c4c025a4c56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149444629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.149444629
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2041382774
Short name T463
Test name
Test status
Simulation time 354820508 ps
CPU time 1.05 seconds
Started Jun 26 04:53:26 PM PDT 24
Finished Jun 26 04:53:32 PM PDT 24
Peak memory 197316 kb
Host smart-0ca64a78-235b-4260-acbe-5fff7ec65440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041382774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2041382774
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.1327596500
Short name T342
Test name
Test status
Simulation time 248939537 ps
CPU time 1.02 seconds
Started Jun 26 04:53:16 PM PDT 24
Finished Jun 26 04:53:19 PM PDT 24
Peak memory 196688 kb
Host smart-cbc12b63-7a04-4687-8b29-e4010db25894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327596500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.1327596500
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1718745064
Short name T533
Test name
Test status
Simulation time 69634666 ps
CPU time 1.16 seconds
Started Jun 26 04:53:15 PM PDT 24
Finished Jun 26 04:53:19 PM PDT 24
Peak memory 197948 kb
Host smart-9b86a823-1e99-4008-ba3d-daa8e16889bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718745064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1718745064
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3172925927
Short name T661
Test name
Test status
Simulation time 62038144 ps
CPU time 1.16 seconds
Started Jun 26 04:53:03 PM PDT 24
Finished Jun 26 04:53:06 PM PDT 24
Peak memory 197088 kb
Host smart-f25dd670-8a55-45a2-9a9d-4375083cf6fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172925927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3172925927
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3197338832
Short name T344
Test name
Test status
Simulation time 30906826 ps
CPU time 0.68 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:53:10 PM PDT 24
Peak memory 194896 kb
Host smart-bee3f8ad-b7ce-4ca8-a45f-a45378c8a811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197338832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3197338832
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3466342708
Short name T522
Test name
Test status
Simulation time 83323561 ps
CPU time 0.94 seconds
Started Jun 26 04:53:24 PM PDT 24
Finished Jun 26 04:53:29 PM PDT 24
Peak memory 196636 kb
Host smart-6647b434-0138-437c-a778-6fc15bf6c938
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466342708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3466342708
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1669434925
Short name T372
Test name
Test status
Simulation time 224427400 ps
CPU time 2.65 seconds
Started Jun 26 04:53:06 PM PDT 24
Finished Jun 26 04:53:11 PM PDT 24
Peak memory 198612 kb
Host smart-9508251a-4859-4cdb-8745-39b2feba35e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669434925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1669434925
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1846709792
Short name T178
Test name
Test status
Simulation time 208964344 ps
CPU time 1 seconds
Started Jun 26 04:53:12 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 196580 kb
Host smart-6c4306d2-aaa9-498a-8201-5a6a2984a6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846709792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1846709792
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1400988943
Short name T697
Test name
Test status
Simulation time 57430100 ps
CPU time 1.19 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:53:10 PM PDT 24
Peak memory 198592 kb
Host smart-2de64401-f696-47b1-af05-5eff49914a72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400988943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1400988943
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3318972799
Short name T630
Test name
Test status
Simulation time 14724375955 ps
CPU time 156.38 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:55:45 PM PDT 24
Peak memory 198780 kb
Host smart-35f6c274-8b93-49e4-a841-4d8a18bd06ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318972799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3318972799
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.4088791812
Short name T305
Test name
Test status
Simulation time 26693540 ps
CPU time 0.61 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:12 PM PDT 24
Peak memory 194816 kb
Host smart-cb71a5d1-f3f6-4d89-ab42-8ea22ec8acdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088791812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4088791812
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3616650130
Short name T158
Test name
Test status
Simulation time 300265418 ps
CPU time 0.85 seconds
Started Jun 26 04:53:14 PM PDT 24
Finished Jun 26 04:53:18 PM PDT 24
Peak memory 197776 kb
Host smart-32e60045-d2bd-4d33-a884-c96c6ad8df22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616650130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3616650130
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2835585291
Short name T472
Test name
Test status
Simulation time 841188320 ps
CPU time 11.53 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:25 PM PDT 24
Peak memory 197608 kb
Host smart-a83df1ac-858d-4c95-bc8b-df7ae9eed12e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835585291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2835585291
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.692338234
Short name T628
Test name
Test status
Simulation time 514191884 ps
CPU time 1.08 seconds
Started Jun 26 04:53:00 PM PDT 24
Finished Jun 26 04:53:04 PM PDT 24
Peak memory 198588 kb
Host smart-72651803-1763-40ea-8ae3-d8ca5f0eef74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692338234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.692338234
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3468083223
Short name T323
Test name
Test status
Simulation time 85215739 ps
CPU time 0.95 seconds
Started Jun 26 04:53:08 PM PDT 24
Finished Jun 26 04:53:12 PM PDT 24
Peak memory 196596 kb
Host smart-2ce43068-dcb3-44eb-a950-ae7cb029aec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468083223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3468083223
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1138456450
Short name T540
Test name
Test status
Simulation time 133582415 ps
CPU time 2.62 seconds
Started Jun 26 04:53:08 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 198740 kb
Host smart-18c0819f-a74a-46d3-98fc-ecf51103385b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138456450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1138456450
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1063200285
Short name T121
Test name
Test status
Simulation time 136578672 ps
CPU time 3.08 seconds
Started Jun 26 04:53:26 PM PDT 24
Finished Jun 26 04:53:34 PM PDT 24
Peak memory 197832 kb
Host smart-f629eb6e-3a78-40a4-9059-80ae8ee19817
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063200285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1063200285
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3227795913
Short name T198
Test name
Test status
Simulation time 33013781 ps
CPU time 0.89 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 197720 kb
Host smart-72ed3c10-b6b2-49e4-b5a9-76dfb66925db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227795913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3227795913
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.671592640
Short name T244
Test name
Test status
Simulation time 104187876 ps
CPU time 1.07 seconds
Started Jun 26 04:53:15 PM PDT 24
Finished Jun 26 04:53:19 PM PDT 24
Peak memory 196592 kb
Host smart-c23bcc9a-8363-4d7c-95c5-f748bf2cb2cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671592640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.671592640
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2371549283
Short name T466
Test name
Test status
Simulation time 527459441 ps
CPU time 5.96 seconds
Started Jun 26 04:53:04 PM PDT 24
Finished Jun 26 04:53:12 PM PDT 24
Peak memory 198608 kb
Host smart-07e9224a-3a05-4c6d-8384-418a7e3b325c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371549283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2371549283
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.751696350
Short name T258
Test name
Test status
Simulation time 179119474 ps
CPU time 1.43 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:14 PM PDT 24
Peak memory 197424 kb
Host smart-ca4f0b60-4240-437d-bd44-2b8ad21aa1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751696350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.751696350
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.551593084
Short name T393
Test name
Test status
Simulation time 38900318 ps
CPU time 1.11 seconds
Started Jun 26 04:53:15 PM PDT 24
Finished Jun 26 04:53:18 PM PDT 24
Peak memory 196232 kb
Host smart-de8bc402-f11f-41e2-a0dc-680765aa4fa3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551593084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.551593084
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2633311089
Short name T363
Test name
Test status
Simulation time 6516605882 ps
CPU time 168.31 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:56:01 PM PDT 24
Peak memory 198680 kb
Host smart-d84808bf-3014-4375-b0ba-bb3c62f2a8ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633311089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2633311089
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1014703914
Short name T76
Test name
Test status
Simulation time 43932504 ps
CPU time 0.57 seconds
Started Jun 26 04:53:23 PM PDT 24
Finished Jun 26 04:53:25 PM PDT 24
Peak memory 195356 kb
Host smart-7c977c1a-6e76-4f04-aad4-84d621fa5ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014703914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1014703914
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.3209197610
Short name T459
Test name
Test status
Simulation time 29336734 ps
CPU time 0.7 seconds
Started Jun 26 04:53:12 PM PDT 24
Finished Jun 26 04:53:16 PM PDT 24
Peak memory 195856 kb
Host smart-d1998aec-01b5-4d32-9d70-58d521f2766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209197610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.3209197610
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2968167595
Short name T236
Test name
Test status
Simulation time 147432077 ps
CPU time 7.34 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 196124 kb
Host smart-2ce8f87a-5966-4eb0-afa2-5f472ea33306
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968167595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2968167595
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1271005861
Short name T280
Test name
Test status
Simulation time 95134089 ps
CPU time 0.64 seconds
Started Jun 26 04:53:14 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 195540 kb
Host smart-ac9e30e7-5332-48dd-8056-c11c0aabe0bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271005861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1271005861
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2766024587
Short name T600
Test name
Test status
Simulation time 48033339 ps
CPU time 1.26 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:13 PM PDT 24
Peak memory 196788 kb
Host smart-0130d708-5d64-4b2d-8772-866b9b8f888d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766024587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2766024587
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2297917366
Short name T596
Test name
Test status
Simulation time 757580514 ps
CPU time 1.82 seconds
Started Jun 26 04:53:05 PM PDT 24
Finished Jun 26 04:53:08 PM PDT 24
Peak memory 198624 kb
Host smart-c5a22cc2-6904-4c94-8357-8899fffeb94c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297917366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2297917366
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3979877409
Short name T298
Test name
Test status
Simulation time 287584407 ps
CPU time 2.3 seconds
Started Jun 26 04:53:07 PM PDT 24
Finished Jun 26 04:53:11 PM PDT 24
Peak memory 197604 kb
Host smart-1f632569-e3f2-44fa-97d9-b35b524c7c9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979877409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3979877409
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3203415399
Short name T228
Test name
Test status
Simulation time 42153992 ps
CPU time 1.06 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:14 PM PDT 24
Peak memory 197336 kb
Host smart-a2935d3c-a1f9-4db1-9436-f6feda7615a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203415399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3203415399
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3025586456
Short name T691
Test name
Test status
Simulation time 159141566 ps
CPU time 0.65 seconds
Started Jun 26 04:53:29 PM PDT 24
Finished Jun 26 04:53:35 PM PDT 24
Peak memory 195556 kb
Host smart-a529667f-914b-48a2-81ab-309554d0782f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025586456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3025586456
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2746562382
Short name T428
Test name
Test status
Simulation time 252442815 ps
CPU time 4.17 seconds
Started Jun 26 04:53:14 PM PDT 24
Finished Jun 26 04:53:22 PM PDT 24
Peak memory 198536 kb
Host smart-5a3c1859-2978-4049-8ef8-e4edd81b4e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746562382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2746562382
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4277400200
Short name T160
Test name
Test status
Simulation time 72494638 ps
CPU time 1.28 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:14 PM PDT 24
Peak memory 198588 kb
Host smart-b8a7afaf-2536-4cd3-95ef-fec4f9dc4bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277400200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4277400200
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2329552467
Short name T359
Test name
Test status
Simulation time 405989971 ps
CPU time 1.15 seconds
Started Jun 26 04:53:14 PM PDT 24
Finished Jun 26 04:53:18 PM PDT 24
Peak memory 197424 kb
Host smart-50001365-aef0-418b-ba1f-4cd37798370a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329552467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2329552467
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2103066219
Short name T658
Test name
Test status
Simulation time 6114709665 ps
CPU time 142.28 seconds
Started Jun 26 04:53:11 PM PDT 24
Finished Jun 26 04:55:37 PM PDT 24
Peak memory 198784 kb
Host smart-3013d265-3deb-4cae-ae3c-f6476a1681c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103066219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2103066219
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2177856399
Short name T601
Test name
Test status
Simulation time 64559787 ps
CPU time 0.55 seconds
Started Jun 26 04:53:11 PM PDT 24
Finished Jun 26 04:53:15 PM PDT 24
Peak memory 194548 kb
Host smart-97409275-46ce-428e-839d-46788e791c34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177856399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2177856399
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1594816944
Short name T700
Test name
Test status
Simulation time 56704721 ps
CPU time 0.78 seconds
Started Jun 26 04:53:28 PM PDT 24
Finished Jun 26 04:53:33 PM PDT 24
Peak memory 196696 kb
Host smart-1c380e46-00c3-4d54-a7bc-1e64a6ba337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594816944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1594816944
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1789481646
Short name T650
Test name
Test status
Simulation time 136346703 ps
CPU time 6.92 seconds
Started Jun 26 04:53:30 PM PDT 24
Finished Jun 26 04:53:41 PM PDT 24
Peak memory 197564 kb
Host smart-9b6b9d1b-6a4d-4dec-ade0-9caf0af352cc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789481646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1789481646
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.446373737
Short name T20
Test name
Test status
Simulation time 399820131 ps
CPU time 1.1 seconds
Started Jun 26 04:53:09 PM PDT 24
Finished Jun 26 04:53:21 PM PDT 24
Peak memory 197328 kb
Host smart-e26740e6-9a4e-49e1-be97-65b2622ac63d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446373737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.446373737
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.800113779
Short name T527
Test name
Test status
Simulation time 91787228 ps
CPU time 1.23 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:14 PM PDT 24
Peak memory 196628 kb
Host smart-c77edb6b-663f-479a-9920-e4d745b9c656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800113779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.800113779
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3459501340
Short name T528
Test name
Test status
Simulation time 130041829 ps
CPU time 1.44 seconds
Started Jun 26 04:53:11 PM PDT 24
Finished Jun 26 04:53:16 PM PDT 24
Peak memory 197344 kb
Host smart-464d35ed-ba67-4117-9e0d-eff2c4467376
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459501340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3459501340
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1674493310
Short name T387
Test name
Test status
Simulation time 77403132 ps
CPU time 1.68 seconds
Started Jun 26 04:53:30 PM PDT 24
Finished Jun 26 04:53:36 PM PDT 24
Peak memory 197132 kb
Host smart-045c9697-edd4-4031-b0e1-f6c2623155d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674493310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1674493310
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.2398491236
Short name T715
Test name
Test status
Simulation time 49579551 ps
CPU time 1.13 seconds
Started Jun 26 04:53:22 PM PDT 24
Finished Jun 26 04:53:24 PM PDT 24
Peak memory 197384 kb
Host smart-af821dec-1536-4a4b-aa7c-238d07e2c212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398491236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.2398491236
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.435819800
Short name T193
Test name
Test status
Simulation time 36147727 ps
CPU time 0.86 seconds
Started Jun 26 04:53:12 PM PDT 24
Finished Jun 26 04:53:17 PM PDT 24
Peak memory 197284 kb
Host smart-d8fb2981-cc8a-4103-aba6-988efb267290
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435819800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.435819800
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2023409393
Short name T439
Test name
Test status
Simulation time 175502695 ps
CPU time 4.19 seconds
Started Jun 26 04:53:24 PM PDT 24
Finished Jun 26 04:53:32 PM PDT 24
Peak memory 198560 kb
Host smart-ad201ab0-efa7-444e-be4f-cb919140fd30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023409393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2023409393
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1360816279
Short name T338
Test name
Test status
Simulation time 233358095 ps
CPU time 1.06 seconds
Started Jun 26 04:53:17 PM PDT 24
Finished Jun 26 04:53:20 PM PDT 24
Peak memory 197092 kb
Host smart-90d028e3-7687-4618-b58b-59c3ecadbd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360816279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1360816279
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1800740573
Short name T469
Test name
Test status
Simulation time 43166892 ps
CPU time 0.9 seconds
Started Jun 26 04:53:10 PM PDT 24
Finished Jun 26 04:53:15 PM PDT 24
Peak memory 197132 kb
Host smart-4e2cccb3-c153-48b9-bfe5-684c4c3a7058
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800740573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1800740573
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.821548309
Short name T31
Test name
Test status
Simulation time 7016825133 ps
CPU time 86.47 seconds
Started Jun 26 04:53:18 PM PDT 24
Finished Jun 26 04:54:46 PM PDT 24
Peak memory 198672 kb
Host smart-6203566f-2fef-44a6-8203-947fb5c61537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821548309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.821548309
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2106487272
Short name T176
Test name
Test status
Simulation time 15413454 ps
CPU time 0.61 seconds
Started Jun 26 04:52:03 PM PDT 24
Finished Jun 26 04:52:05 PM PDT 24
Peak memory 195244 kb
Host smart-1b73e7ad-3a6a-411a-980f-5e295244ad7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106487272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2106487272
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2673663240
Short name T18
Test name
Test status
Simulation time 37682834 ps
CPU time 0.7 seconds
Started Jun 26 04:51:40 PM PDT 24
Finished Jun 26 04:51:43 PM PDT 24
Peak memory 196424 kb
Host smart-0cac872a-2d9e-4c21-855b-10acc3a87e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673663240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2673663240
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.904254729
Short name T317
Test name
Test status
Simulation time 1203008586 ps
CPU time 16.43 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:52:07 PM PDT 24
Peak memory 196224 kb
Host smart-59567ab9-392b-4a82-b29d-e1e258c32dc7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904254729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.904254729
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.157153705
Short name T671
Test name
Test status
Simulation time 820979121 ps
CPU time 0.84 seconds
Started Jun 26 04:51:47 PM PDT 24
Finished Jun 26 04:51:49 PM PDT 24
Peak memory 196480 kb
Host smart-aa7e020a-21e9-4ce7-8f2f-a8518f843854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157153705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.157153705
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.810308641
Short name T153
Test name
Test status
Simulation time 112232920 ps
CPU time 0.77 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:51:55 PM PDT 24
Peak memory 196016 kb
Host smart-a30e8602-e993-4505-816e-a98ee1c04ff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810308641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.810308641
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.825235799
Short name T660
Test name
Test status
Simulation time 50187170 ps
CPU time 1.1 seconds
Started Jun 26 04:51:48 PM PDT 24
Finished Jun 26 04:51:50 PM PDT 24
Peak memory 198564 kb
Host smart-ff799c8e-f56c-45de-9217-d745911c0e27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825235799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.825235799
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1166867107
Short name T12
Test name
Test status
Simulation time 149369817 ps
CPU time 0.93 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 196164 kb
Host smart-139d4db9-03f5-4121-a26a-436f4add385b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166867107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1166867107
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1389015823
Short name T623
Test name
Test status
Simulation time 145663618 ps
CPU time 1.2 seconds
Started Jun 26 04:51:34 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 197616 kb
Host smart-474fc440-f254-4c75-9977-f0b7d335b1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389015823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1389015823
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1156775500
Short name T211
Test name
Test status
Simulation time 181232253 ps
CPU time 0.96 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:51 PM PDT 24
Peak memory 197300 kb
Host smart-07f76d33-1840-4383-8f6f-70e75e2c8810
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156775500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1156775500
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2718566243
Short name T616
Test name
Test status
Simulation time 34896322 ps
CPU time 1.52 seconds
Started Jun 26 04:51:46 PM PDT 24
Finished Jun 26 04:51:48 PM PDT 24
Peak memory 198668 kb
Host smart-3018b7d6-9e90-4120-bd15-8a48d49eed54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718566243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2718566243
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.248254217
Short name T451
Test name
Test status
Simulation time 390195123 ps
CPU time 1.26 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 196256 kb
Host smart-31c994d5-0158-4030-abdc-8a2beaee2c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248254217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.248254217
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3275680465
Short name T112
Test name
Test status
Simulation time 542770968 ps
CPU time 0.79 seconds
Started Jun 26 04:52:09 PM PDT 24
Finished Jun 26 04:52:12 PM PDT 24
Peak memory 195956 kb
Host smart-b655199a-8a67-4434-ba00-0b31dc1c53d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275680465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3275680465
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1045788582
Short name T706
Test name
Test status
Simulation time 3355569942 ps
CPU time 38.5 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:52:32 PM PDT 24
Peak memory 198784 kb
Host smart-7a6360ed-ef75-4bec-b43c-78915a459784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045788582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1045788582
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3669285569
Short name T335
Test name
Test status
Simulation time 13080656 ps
CPU time 0.56 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:57 PM PDT 24
Peak memory 194684 kb
Host smart-eb3b286d-0dbc-4725-b879-6c22e2637d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669285569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3669285569
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1362816702
Short name T450
Test name
Test status
Simulation time 57773997 ps
CPU time 0.65 seconds
Started Jun 26 04:51:51 PM PDT 24
Finished Jun 26 04:51:53 PM PDT 24
Peak memory 194648 kb
Host smart-31d9b239-1a20-4e42-826f-b9bc853c2a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362816702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1362816702
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4170045962
Short name T710
Test name
Test status
Simulation time 887400179 ps
CPU time 24.13 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:25 PM PDT 24
Peak memory 197240 kb
Host smart-a114f29a-e73b-4985-89b1-f9d82656fefc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170045962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4170045962
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.4029509220
Short name T410
Test name
Test status
Simulation time 35456126 ps
CPU time 0.71 seconds
Started Jun 26 04:51:36 PM PDT 24
Finished Jun 26 04:51:41 PM PDT 24
Peak memory 196512 kb
Host smart-585fdc01-d161-4841-ad2c-3827e1b4d42a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029509220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.4029509220
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3281354973
Short name T548
Test name
Test status
Simulation time 22818335 ps
CPU time 0.77 seconds
Started Jun 26 04:52:02 PM PDT 24
Finished Jun 26 04:52:05 PM PDT 24
Peak memory 196152 kb
Host smart-1ee2c29b-a4c0-41b0-8093-28ac14fbf8a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281354973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3281354973
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3066208880
Short name T204
Test name
Test status
Simulation time 200664456 ps
CPU time 3.12 seconds
Started Jun 26 04:51:37 PM PDT 24
Finished Jun 26 04:51:44 PM PDT 24
Peak memory 198704 kb
Host smart-e92f155c-db3c-4c8d-ada1-eb270649b580
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066208880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3066208880
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2875644291
Short name T353
Test name
Test status
Simulation time 107502885 ps
CPU time 1.05 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:51:56 PM PDT 24
Peak memory 196300 kb
Host smart-7c442ef2-1e61-4b12-b2bf-8addd1d56c5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875644291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2875644291
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.387683308
Short name T282
Test name
Test status
Simulation time 40216435 ps
CPU time 0.93 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 196672 kb
Host smart-91dd4dc3-12ae-47a5-8a7d-6852f1794b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387683308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.387683308
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.129767273
Short name T200
Test name
Test status
Simulation time 36403364 ps
CPU time 0.92 seconds
Started Jun 26 04:51:36 PM PDT 24
Finished Jun 26 04:51:41 PM PDT 24
Peak memory 196724 kb
Host smart-fde44198-191f-4212-94b6-43c28782e2dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129767273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.129767273
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.2134602172
Short name T58
Test name
Test status
Simulation time 444624777 ps
CPU time 5.26 seconds
Started Jun 26 04:51:48 PM PDT 24
Finished Jun 26 04:51:55 PM PDT 24
Peak memory 198572 kb
Host smart-a868028e-557e-4808-b671-98ffd1bf91c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134602172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.2134602172
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2207655868
Short name T24
Test name
Test status
Simulation time 125923013 ps
CPU time 0.95 seconds
Started Jun 26 04:51:49 PM PDT 24
Finished Jun 26 04:51:52 PM PDT 24
Peak memory 196112 kb
Host smart-ede44c97-1d8f-4269-9a82-e6ec2e8a5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207655868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2207655868
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4034341043
Short name T517
Test name
Test status
Simulation time 43126839 ps
CPU time 0.88 seconds
Started Jun 26 04:52:07 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 195980 kb
Host smart-6989218f-8e86-4a42-8458-f3b8eb35a767
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034341043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4034341043
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1189370070
Short name T582
Test name
Test status
Simulation time 6370427490 ps
CPU time 43.16 seconds
Started Jun 26 04:51:35 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 198812 kb
Host smart-55fbf635-cd56-4801-a5b6-fce12231b612
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189370070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1189370070
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4251539398
Short name T399
Test name
Test status
Simulation time 52783295 ps
CPU time 0.54 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:51:56 PM PDT 24
Peak memory 194568 kb
Host smart-430a6f70-f01f-4902-9818-d4c07c6daaa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251539398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4251539398
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3788062327
Short name T614
Test name
Test status
Simulation time 40029800 ps
CPU time 0.86 seconds
Started Jun 26 04:51:44 PM PDT 24
Finished Jun 26 04:51:47 PM PDT 24
Peak memory 197720 kb
Host smart-08dde61b-dcab-4d83-abeb-70554d31834d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788062327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3788062327
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2747195767
Short name T447
Test name
Test status
Simulation time 502938145 ps
CPU time 16.49 seconds
Started Jun 26 04:51:53 PM PDT 24
Finished Jun 26 04:52:12 PM PDT 24
Peak memory 197496 kb
Host smart-5e1a869b-6ff6-43f7-818b-81d072d73f97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747195767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2747195767
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.4109801767
Short name T140
Test name
Test status
Simulation time 244752960 ps
CPU time 0.9 seconds
Started Jun 26 04:51:59 PM PDT 24
Finished Jun 26 04:52:03 PM PDT 24
Peak memory 196692 kb
Host smart-406d9744-dbff-471d-b23e-068aa87662fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109801767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4109801767
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.884982454
Short name T654
Test name
Test status
Simulation time 328257845 ps
CPU time 1.44 seconds
Started Jun 26 04:52:00 PM PDT 24
Finished Jun 26 04:52:04 PM PDT 24
Peak memory 197640 kb
Host smart-7e13e367-a3e1-4c91-899d-3d91938b11b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884982454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.884982454
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1455095501
Short name T72
Test name
Test status
Simulation time 118873937 ps
CPU time 2.42 seconds
Started Jun 26 04:52:02 PM PDT 24
Finished Jun 26 04:52:07 PM PDT 24
Peak memory 198608 kb
Host smart-4431c3b1-f08e-489a-8e8c-82c1cac6a384
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455095501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1455095501
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1794487748
Short name T281
Test name
Test status
Simulation time 277589060 ps
CPU time 2.15 seconds
Started Jun 26 04:52:03 PM PDT 24
Finished Jun 26 04:52:07 PM PDT 24
Peak memory 197736 kb
Host smart-650a04f8-3af9-4f79-8598-06bdd9772e2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794487748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1794487748
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1617149743
Short name T642
Test name
Test status
Simulation time 40677725 ps
CPU time 0.9 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 196656 kb
Host smart-886bcae1-c6a4-4239-a649-9018601a4720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617149743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1617149743
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4265870967
Short name T709
Test name
Test status
Simulation time 31045248 ps
CPU time 1.19 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:02 PM PDT 24
Peak memory 196664 kb
Host smart-f52f3ab1-6042-4c1a-b7d6-8badd7832836
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265870967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4265870967
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3939790738
Short name T132
Test name
Test status
Simulation time 375701194 ps
CPU time 5.94 seconds
Started Jun 26 04:51:47 PM PDT 24
Finished Jun 26 04:51:54 PM PDT 24
Peak memory 198676 kb
Host smart-10675896-4fc8-45ac-9b7b-a6f73d52a4aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939790738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3939790738
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1579661105
Short name T115
Test name
Test status
Simulation time 59244879 ps
CPU time 1.09 seconds
Started Jun 26 04:51:35 PM PDT 24
Finished Jun 26 04:51:40 PM PDT 24
Peak memory 196476 kb
Host smart-d9ba246f-2bce-4bb3-8366-51a15af163bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579661105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1579661105
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3483226853
Short name T491
Test name
Test status
Simulation time 178940252 ps
CPU time 1.1 seconds
Started Jun 26 04:51:44 PM PDT 24
Finished Jun 26 04:51:46 PM PDT 24
Peak memory 196912 kb
Host smart-e0bda04b-9487-43b7-8a89-ece2c5728fe7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483226853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3483226853
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3318533644
Short name T10
Test name
Test status
Simulation time 2379703021 ps
CPU time 26.61 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:26 PM PDT 24
Peak memory 198828 kb
Host smart-bc8834ba-baeb-4cb5-b594-de62cd3fce63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318533644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3318533644
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3555637233
Short name T239
Test name
Test status
Simulation time 38605855 ps
CPU time 0.62 seconds
Started Jun 26 04:51:59 PM PDT 24
Finished Jun 26 04:52:03 PM PDT 24
Peak memory 194628 kb
Host smart-f6a51a2d-ea6e-4899-ba23-9cdda3659cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555637233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3555637233
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1253175126
Short name T146
Test name
Test status
Simulation time 46801426 ps
CPU time 0.87 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:58 PM PDT 24
Peak memory 195940 kb
Host smart-1191a5a4-1558-4819-ae90-b459fb2ec615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253175126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1253175126
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1972009179
Short name T646
Test name
Test status
Simulation time 629119034 ps
CPU time 17.21 seconds
Started Jun 26 04:51:59 PM PDT 24
Finished Jun 26 04:52:20 PM PDT 24
Peak memory 196220 kb
Host smart-7df8696f-ee70-4a4c-972b-860f766a3f9c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972009179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1972009179
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.262785618
Short name T245
Test name
Test status
Simulation time 35658890 ps
CPU time 0.74 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:16 PM PDT 24
Peak memory 196516 kb
Host smart-a46f251e-73f2-48ca-82d0-9eeeb960cad2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262785618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.262785618
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1721383929
Short name T574
Test name
Test status
Simulation time 693422441 ps
CPU time 1.03 seconds
Started Jun 26 04:52:13 PM PDT 24
Finished Jun 26 04:52:17 PM PDT 24
Peak memory 196684 kb
Host smart-07c0fd44-23f2-4773-bc36-dfdd7684996a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721383929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1721383929
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1852910653
Short name T508
Test name
Test status
Simulation time 189790176 ps
CPU time 3.59 seconds
Started Jun 26 04:52:06 PM PDT 24
Finished Jun 26 04:52:12 PM PDT 24
Peak memory 198684 kb
Host smart-b5ae2561-0f66-487a-9ef7-a7e2a70faacb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852910653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1852910653
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2900201657
Short name T434
Test name
Test status
Simulation time 108226103 ps
CPU time 3.18 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:51:57 PM PDT 24
Peak memory 197728 kb
Host smart-2b04b0d5-8eaa-4a69-83e5-f5bdb1b2edf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900201657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2900201657
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4224255540
Short name T276
Test name
Test status
Simulation time 96792364 ps
CPU time 1.34 seconds
Started Jun 26 04:51:57 PM PDT 24
Finished Jun 26 04:52:02 PM PDT 24
Peak memory 198716 kb
Host smart-b01566a9-29d8-4db6-9fcc-f406337a9f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224255540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4224255540
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3307244261
Short name T287
Test name
Test status
Simulation time 31306797 ps
CPU time 0.76 seconds
Started Jun 26 04:52:11 PM PDT 24
Finished Jun 26 04:52:14 PM PDT 24
Peak memory 196840 kb
Host smart-7958b478-f9e4-41d0-b250-089056b6034e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307244261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3307244261
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.975371169
Short name T555
Test name
Test status
Simulation time 256413425 ps
CPU time 2.93 seconds
Started Jun 26 04:51:51 PM PDT 24
Finished Jun 26 04:51:56 PM PDT 24
Peak memory 198632 kb
Host smart-ab7c7465-e821-4c74-9b73-332f67c50c2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975371169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.975371169
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2135798970
Short name T321
Test name
Test status
Simulation time 83821087 ps
CPU time 1.19 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 196336 kb
Host smart-8e90deaa-9488-4dae-87ff-6641ad8c28b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135798970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2135798970
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3383709217
Short name T500
Test name
Test status
Simulation time 239246004 ps
CPU time 0.89 seconds
Started Jun 26 04:51:56 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 195872 kb
Host smart-56567b49-1128-40df-82de-005b5aae7236
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383709217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3383709217
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1188496300
Short name T626
Test name
Test status
Simulation time 29251174968 ps
CPU time 177.96 seconds
Started Jun 26 04:52:02 PM PDT 24
Finished Jun 26 04:55:02 PM PDT 24
Peak memory 198744 kb
Host smart-8cde80aa-564a-4ff5-a74b-c98e132847e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188496300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1188496300
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3934291461
Short name T243
Test name
Test status
Simulation time 14585937 ps
CPU time 0.57 seconds
Started Jun 26 04:51:59 PM PDT 24
Finished Jun 26 04:52:03 PM PDT 24
Peak memory 195372 kb
Host smart-7e52a001-b1d3-4599-b745-f3a7d2711122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934291461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3934291461
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.310848921
Short name T612
Test name
Test status
Simulation time 13357844 ps
CPU time 0.66 seconds
Started Jun 26 04:51:52 PM PDT 24
Finished Jun 26 04:51:54 PM PDT 24
Peak memory 195356 kb
Host smart-927206be-f5ff-4d82-b430-c1721a727bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310848921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.310848921
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1482215436
Short name T262
Test name
Test status
Simulation time 2170877346 ps
CPU time 8.6 seconds
Started Jun 26 04:51:58 PM PDT 24
Finished Jun 26 04:52:10 PM PDT 24
Peak memory 198652 kb
Host smart-4ad7182b-1df2-4855-82a3-7f8021879852
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482215436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1482215436
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.8193101
Short name T534
Test name
Test status
Simulation time 178281986 ps
CPU time 1.08 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:00 PM PDT 24
Peak memory 197312 kb
Host smart-4724dc55-a3e6-4fe6-b2c0-cd4a3f86fb4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8193101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.8193101
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4077734686
Short name T577
Test name
Test status
Simulation time 49759521 ps
CPU time 1.33 seconds
Started Jun 26 04:51:50 PM PDT 24
Finished Jun 26 04:51:53 PM PDT 24
Peak memory 197380 kb
Host smart-b1a51963-acfa-48bd-9bf6-94533374d31a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077734686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4077734686
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4202317989
Short name T583
Test name
Test status
Simulation time 73400830 ps
CPU time 2.84 seconds
Started Jun 26 04:51:55 PM PDT 24
Finished Jun 26 04:52:01 PM PDT 24
Peak memory 198676 kb
Host smart-4083f5c2-ca00-4ec4-b9b7-9358ea63268f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202317989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4202317989
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3573478449
Short name T696
Test name
Test status
Simulation time 267851871 ps
CPU time 1.76 seconds
Started Jun 26 04:51:42 PM PDT 24
Finished Jun 26 04:51:46 PM PDT 24
Peak memory 196432 kb
Host smart-5dbb8f04-a2fc-4927-9baa-047f5bd81cee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573478449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3573478449
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1038308692
Short name T515
Test name
Test status
Simulation time 105869244 ps
CPU time 1.09 seconds
Started Jun 26 04:52:03 PM PDT 24
Finished Jun 26 04:52:06 PM PDT 24
Peak memory 197448 kb
Host smart-da09f346-3bb3-49d7-a8b9-a172523c82dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038308692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1038308692
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.456107861
Short name T74
Test name
Test status
Simulation time 75964099 ps
CPU time 1.23 seconds
Started Jun 26 04:52:08 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 197752 kb
Host smart-e6e6d544-e81f-4462-bc33-16a84eefac44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456107861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.456107861
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3728440316
Short name T122
Test name
Test status
Simulation time 123516716 ps
CPU time 3.51 seconds
Started Jun 26 04:52:06 PM PDT 24
Finished Jun 26 04:52:11 PM PDT 24
Peak memory 198652 kb
Host smart-9178f849-b0d8-437f-b901-877be6f20645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728440316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3728440316
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3533650034
Short name T25
Test name
Test status
Simulation time 46382884 ps
CPU time 1.18 seconds
Started Jun 26 04:52:05 PM PDT 24
Finished Jun 26 04:52:08 PM PDT 24
Peak memory 196544 kb
Host smart-ccbd0d00-0804-4a2f-aa39-10c1f7218769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533650034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3533650034
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.152261320
Short name T185
Test name
Test status
Simulation time 110104113 ps
CPU time 1.09 seconds
Started Jun 26 04:51:54 PM PDT 24
Finished Jun 26 04:51:58 PM PDT 24
Peak memory 196464 kb
Host smart-5c55f570-fa27-4a4c-81c7-dd51b0b05cdb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152261320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.152261320
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3213273209
Short name T415
Test name
Test status
Simulation time 4247752171 ps
CPU time 30.67 seconds
Started Jun 26 04:51:51 PM PDT 24
Finished Jun 26 04:52:23 PM PDT 24
Peak memory 198752 kb
Host smart-f2cad395-ac77-43d8-896c-4514f2a2424f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213273209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3213273209
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.308673083
Short name T34
Test name
Test status
Simulation time 19894419135 ps
CPU time 605.74 seconds
Started Jun 26 04:51:43 PM PDT 24
Finished Jun 26 05:01:50 PM PDT 24
Peak memory 198912 kb
Host smart-fd1180f1-e40d-4fb0-99cc-6b6eeb22765e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=308673083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.308673083
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2784301887
Short name T936
Test name
Test status
Simulation time 122637041 ps
CPU time 1.2 seconds
Started Jun 26 04:34:53 PM PDT 24
Finished Jun 26 04:34:59 PM PDT 24
Peak memory 196844 kb
Host smart-6cfb1d4a-773a-44eb-8757-0561f835cfb0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2784301887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2784301887
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1288656343
Short name T932
Test name
Test status
Simulation time 330723756 ps
CPU time 0.85 seconds
Started Jun 26 04:36:13 PM PDT 24
Finished Jun 26 04:36:17 PM PDT 24
Peak memory 196780 kb
Host smart-309273b0-2d89-4bbe-969c-deb9cd30bb2c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288656343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1288656343
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.4069101589
Short name T895
Test name
Test status
Simulation time 109550253 ps
CPU time 1.2 seconds
Started Jun 26 04:34:53 PM PDT 24
Finished Jun 26 04:34:59 PM PDT 24
Peak memory 191976 kb
Host smart-b2589ff3-a371-406d-943b-6e9b7a19b7da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4069101589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.4069101589
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3044427220
Short name T901
Test name
Test status
Simulation time 64808718 ps
CPU time 1.11 seconds
Started Jun 26 04:36:07 PM PDT 24
Finished Jun 26 04:36:12 PM PDT 24
Peak memory 196740 kb
Host smart-cbec1b77-f0bf-4a2a-af8f-ec5fc0cbcceb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044427220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3044427220
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2942195674
Short name T883
Test name
Test status
Simulation time 86531449 ps
CPU time 1.39 seconds
Started Jun 26 04:34:57 PM PDT 24
Finished Jun 26 04:35:03 PM PDT 24
Peak memory 196888 kb
Host smart-ac335a9f-2400-4bc7-addc-3cc9025d9fa8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2942195674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2942195674
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3530931148
Short name T880
Test name
Test status
Simulation time 147702946 ps
CPU time 1.09 seconds
Started Jun 26 04:35:11 PM PDT 24
Finished Jun 26 04:35:14 PM PDT 24
Peak memory 196692 kb
Host smart-a956c7af-370d-4ac2-ae10-7853e3b1f862
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530931148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3530931148
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2063793832
Short name T919
Test name
Test status
Simulation time 38209104 ps
CPU time 1.03 seconds
Started Jun 26 04:34:57 PM PDT 24
Finished Jun 26 04:35:03 PM PDT 24
Peak memory 198320 kb
Host smart-1e4816e6-c0dc-42d4-a44c-1cb678a989c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2063793832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2063793832
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1173192681
Short name T851
Test name
Test status
Simulation time 782824511 ps
CPU time 1.16 seconds
Started Jun 26 04:34:53 PM PDT 24
Finished Jun 26 04:34:58 PM PDT 24
Peak memory 196928 kb
Host smart-50bb6df5-8431-47d3-9cf5-654e158c32d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173192681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1173192681
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4280115071
Short name T904
Test name
Test status
Simulation time 67096090 ps
CPU time 1.35 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:35:19 PM PDT 24
Peak memory 197120 kb
Host smart-25df3f3d-ab0c-4d35-968e-e83a7a82b2c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4280115071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4280115071
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2743712683
Short name T889
Test name
Test status
Simulation time 94063180 ps
CPU time 0.94 seconds
Started Jun 26 04:35:09 PM PDT 24
Finished Jun 26 04:35:11 PM PDT 24
Peak memory 196804 kb
Host smart-0ef37777-1f27-4859-82f4-ab069a9e0c75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743712683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2743712683
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1073453878
Short name T928
Test name
Test status
Simulation time 192095092 ps
CPU time 1.22 seconds
Started Jun 26 04:34:55 PM PDT 24
Finished Jun 26 04:35:01 PM PDT 24
Peak memory 196832 kb
Host smart-484c282a-123d-4b7e-b8c5-ee7dbbff5fcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1073453878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1073453878
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.495961652
Short name T871
Test name
Test status
Simulation time 69821214 ps
CPU time 1.11 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:31 PM PDT 24
Peak memory 196148 kb
Host smart-a24724c7-abfa-4968-8ec1-cced015df742
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495961652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.495961652
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2279161166
Short name T888
Test name
Test status
Simulation time 52175928 ps
CPU time 1.11 seconds
Started Jun 26 04:34:52 PM PDT 24
Finished Jun 26 04:34:57 PM PDT 24
Peak memory 196068 kb
Host smart-9c96d3cf-ae0a-49f6-a7ff-b7487e412a25
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2279161166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2279161166
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3903712337
Short name T892
Test name
Test status
Simulation time 191624183 ps
CPU time 1.32 seconds
Started Jun 26 04:34:51 PM PDT 24
Finished Jun 26 04:34:55 PM PDT 24
Peak memory 198292 kb
Host smart-e7393082-ee38-48af-9a77-0117839f3adf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903712337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3903712337
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3363888613
Short name T923
Test name
Test status
Simulation time 187474888 ps
CPU time 0.93 seconds
Started Jun 26 04:35:11 PM PDT 24
Finished Jun 26 04:35:14 PM PDT 24
Peak memory 197160 kb
Host smart-fc79d562-dd2f-47d5-a03a-d480eb468e2d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3363888613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3363888613
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1190154322
Short name T916
Test name
Test status
Simulation time 146889122 ps
CPU time 1.33 seconds
Started Jun 26 04:34:54 PM PDT 24
Finished Jun 26 04:35:00 PM PDT 24
Peak memory 197132 kb
Host smart-b2301c0d-7471-4471-a946-58015c996d3a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190154322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1190154322
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3933630058
Short name T852
Test name
Test status
Simulation time 43998229 ps
CPU time 1.16 seconds
Started Jun 26 04:35:11 PM PDT 24
Finished Jun 26 04:35:15 PM PDT 24
Peak memory 197124 kb
Host smart-9c7d542f-2a0b-4ebd-9fb4-30e2f744447d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3933630058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3933630058
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2930196172
Short name T887
Test name
Test status
Simulation time 546806293 ps
CPU time 1.24 seconds
Started Jun 26 04:34:54 PM PDT 24
Finished Jun 26 04:34:59 PM PDT 24
Peak memory 196908 kb
Host smart-af4f53c1-4da0-4a47-a776-a577d0df3966
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930196172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2930196172
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1058015147
Short name T858
Test name
Test status
Simulation time 70112800 ps
CPU time 1.11 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:15 PM PDT 24
Peak memory 196868 kb
Host smart-18cfab81-b50e-4203-90b4-5a6743c0d38c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1058015147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1058015147
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3032009276
Short name T863
Test name
Test status
Simulation time 144859809 ps
CPU time 0.85 seconds
Started Jun 26 04:35:09 PM PDT 24
Finished Jun 26 04:35:11 PM PDT 24
Peak memory 195792 kb
Host smart-3133320e-9460-46b3-a2e5-484af6decbdc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032009276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3032009276
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2244963593
Short name T854
Test name
Test status
Simulation time 160976269 ps
CPU time 1.16 seconds
Started Jun 26 04:34:53 PM PDT 24
Finished Jun 26 04:34:58 PM PDT 24
Peak memory 197072 kb
Host smart-33a67cd4-efa1-41de-b5bd-1581a82a0dad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2244963593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2244963593
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3205140440
Short name T930
Test name
Test status
Simulation time 79281782 ps
CPU time 1.04 seconds
Started Jun 26 04:34:52 PM PDT 24
Finished Jun 26 04:34:58 PM PDT 24
Peak memory 195788 kb
Host smart-0690ef94-530a-4507-bcca-5a4735c3b20f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205140440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3205140440
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.444186119
Short name T934
Test name
Test status
Simulation time 43635140 ps
CPU time 1.17 seconds
Started Jun 26 04:34:55 PM PDT 24
Finished Jun 26 04:35:01 PM PDT 24
Peak memory 197136 kb
Host smart-d1a84e56-d833-4b2e-a381-4f27c0c106ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=444186119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.444186119
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2291837499
Short name T875
Test name
Test status
Simulation time 101417911 ps
CPU time 1.51 seconds
Started Jun 26 04:35:43 PM PDT 24
Finished Jun 26 04:35:49 PM PDT 24
Peak memory 196912 kb
Host smart-13d756ba-8ffc-40f9-b17c-8d2877036af0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291837499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2291837499
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2327923574
Short name T873
Test name
Test status
Simulation time 52828997 ps
CPU time 1.03 seconds
Started Jun 26 04:35:07 PM PDT 24
Finished Jun 26 04:35:10 PM PDT 24
Peak memory 195052 kb
Host smart-ed8f6dba-9f08-4bee-a684-30f764684c60
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2327923574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2327923574
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1016187685
Short name T914
Test name
Test status
Simulation time 65241160 ps
CPU time 1.15 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:15 PM PDT 24
Peak memory 196900 kb
Host smart-880dcbc3-e387-4b99-9677-859706e58d35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016187685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1016187685
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1438679790
Short name T920
Test name
Test status
Simulation time 66804323 ps
CPU time 1.13 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:24 PM PDT 24
Peak memory 196240 kb
Host smart-257d30b2-75ef-44ca-871b-c4363e08bfd0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1438679790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1438679790
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807303327
Short name T848
Test name
Test status
Simulation time 149432637 ps
CPU time 0.9 seconds
Started Jun 26 04:35:11 PM PDT 24
Finished Jun 26 04:35:14 PM PDT 24
Peak memory 196800 kb
Host smart-04d8f5d7-ec59-4de0-aa10-548d4b9b775e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807303327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2807303327
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.758528690
Short name T926
Test name
Test status
Simulation time 47728698 ps
CPU time 1.24 seconds
Started Jun 26 04:34:57 PM PDT 24
Finished Jun 26 04:35:03 PM PDT 24
Peak memory 198320 kb
Host smart-afbb7103-e518-4196-bd03-7093077cfa40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=758528690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.758528690
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1281856432
Short name T843
Test name
Test status
Simulation time 37855109 ps
CPU time 1.26 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:15 PM PDT 24
Peak memory 198348 kb
Host smart-d658ce18-bb5b-4452-8dfa-be70900de352
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281856432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1281856432
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.729562755
Short name T874
Test name
Test status
Simulation time 45481569 ps
CPU time 1.24 seconds
Started Jun 26 04:35:03 PM PDT 24
Finished Jun 26 04:35:06 PM PDT 24
Peak memory 196860 kb
Host smart-3774c32a-b9db-4578-9e5a-0362a2499929
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=729562755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.729562755
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1838426992
Short name T859
Test name
Test status
Simulation time 40481473 ps
CPU time 1.03 seconds
Started Jun 26 04:35:05 PM PDT 24
Finished Jun 26 04:35:08 PM PDT 24
Peak memory 196144 kb
Host smart-7bb8bf4a-c4d4-4e72-8ce6-f71fc1be3bfa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838426992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1838426992
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4057924049
Short name T841
Test name
Test status
Simulation time 90382282 ps
CPU time 1.25 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:15 PM PDT 24
Peak memory 197012 kb
Host smart-c4978047-a51b-476d-8128-fa8e3dba9923
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4057924049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.4057924049
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.480003949
Short name T918
Test name
Test status
Simulation time 104543097 ps
CPU time 1.75 seconds
Started Jun 26 04:35:02 PM PDT 24
Finished Jun 26 04:35:06 PM PDT 24
Peak memory 197144 kb
Host smart-ef4ce377-78a3-4539-86a8-b6847c3fbc83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480003949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.480003949
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4187086017
Short name T908
Test name
Test status
Simulation time 50052276 ps
CPU time 1.06 seconds
Started Jun 26 04:34:52 PM PDT 24
Finished Jun 26 04:34:58 PM PDT 24
Peak memory 196752 kb
Host smart-87912203-26e3-4ebb-bc3d-eedfe597530f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4187086017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4187086017
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861847676
Short name T891
Test name
Test status
Simulation time 66198618 ps
CPU time 1.07 seconds
Started Jun 26 04:35:02 PM PDT 24
Finished Jun 26 04:35:05 PM PDT 24
Peak memory 195988 kb
Host smart-b1ee47ed-c7c4-45b7-87a0-92bcf5796c3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861847676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.861847676
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4207681433
Short name T903
Test name
Test status
Simulation time 218209386 ps
CPU time 1.09 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:25 PM PDT 24
Peak memory 196836 kb
Host smart-5cde3180-3e77-4e88-908a-7607f1d22819
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4207681433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4207681433
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.643413618
Short name T890
Test name
Test status
Simulation time 35185752 ps
CPU time 1.03 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:23 PM PDT 24
Peak memory 196888 kb
Host smart-4fe5eb3e-61f1-4fc1-9c9e-0533197f46a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643413618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.643413618
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3005424365
Short name T840
Test name
Test status
Simulation time 64558057 ps
CPU time 1.21 seconds
Started Jun 26 04:35:04 PM PDT 24
Finished Jun 26 04:35:07 PM PDT 24
Peak memory 197028 kb
Host smart-0203ff57-1ce1-4419-be58-2c5d303db4ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3005424365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3005424365
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.419057623
Short name T931
Test name
Test status
Simulation time 245505324 ps
CPU time 1.07 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:35:26 PM PDT 24
Peak memory 198344 kb
Host smart-780903cd-b44f-4119-ad99-df499fc85a14
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419057623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.419057623
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3300498942
Short name T913
Test name
Test status
Simulation time 85426527 ps
CPU time 1.18 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:23 PM PDT 24
Peak memory 195936 kb
Host smart-4628412f-f496-4953-9d01-591852c0ea35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3300498942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3300498942
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1767202562
Short name T872
Test name
Test status
Simulation time 534641718 ps
CPU time 1.64 seconds
Started Jun 26 04:34:51 PM PDT 24
Finished Jun 26 04:34:56 PM PDT 24
Peak memory 197096 kb
Host smart-4b39d832-e07d-4e15-9ad7-90ce116b21a8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767202562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1767202562
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1667726698
Short name T900
Test name
Test status
Simulation time 398270841 ps
CPU time 1.05 seconds
Started Jun 26 04:35:02 PM PDT 24
Finished Jun 26 04:35:05 PM PDT 24
Peak memory 196772 kb
Host smart-07043ba8-0293-4541-90db-eebe753d1c41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1667726698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1667726698
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.522770302
Short name T877
Test name
Test status
Simulation time 96157210 ps
CPU time 1.41 seconds
Started Jun 26 04:35:24 PM PDT 24
Finished Jun 26 04:35:32 PM PDT 24
Peak memory 197208 kb
Host smart-1c092363-f510-4c47-9ac9-f829e06d7606
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522770302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.522770302
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.131817481
Short name T862
Test name
Test status
Simulation time 105952274 ps
CPU time 1.08 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:35:19 PM PDT 24
Peak memory 196200 kb
Host smart-9166e6c7-a8d1-40ea-bbea-504a8012f61e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=131817481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.131817481
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.677407024
Short name T885
Test name
Test status
Simulation time 36823966 ps
CPU time 1.01 seconds
Started Jun 26 04:35:10 PM PDT 24
Finished Jun 26 04:35:12 PM PDT 24
Peak memory 195624 kb
Host smart-9fc33358-0d43-45e6-96fc-b904ee250260
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677407024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.677407024
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.872477007
Short name T865
Test name
Test status
Simulation time 265936356 ps
CPU time 1.36 seconds
Started Jun 26 04:34:53 PM PDT 24
Finished Jun 26 04:34:58 PM PDT 24
Peak memory 196076 kb
Host smart-191d26f2-5354-47bb-90fb-99414f727e8e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=872477007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.872477007
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.685078216
Short name T878
Test name
Test status
Simulation time 40763051 ps
CPU time 1.1 seconds
Started Jun 26 04:34:51 PM PDT 24
Finished Jun 26 04:34:56 PM PDT 24
Peak memory 196244 kb
Host smart-16fc98c3-0230-499d-9daf-53808d0b1d79
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685078216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.685078216
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2230735933
Short name T915
Test name
Test status
Simulation time 417590370 ps
CPU time 1.36 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:35:26 PM PDT 24
Peak memory 196880 kb
Host smart-f5648950-ada0-4dcd-8730-925d80a721d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2230735933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2230735933
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.908489933
Short name T866
Test name
Test status
Simulation time 357265814 ps
CPU time 1.3 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:25 PM PDT 24
Peak memory 195948 kb
Host smart-6569e977-8176-44be-a7ea-5e52f341df02
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908489933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.908489933
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2412735082
Short name T906
Test name
Test status
Simulation time 614788957 ps
CPU time 1.17 seconds
Started Jun 26 04:34:57 PM PDT 24
Finished Jun 26 04:35:03 PM PDT 24
Peak memory 196868 kb
Host smart-a3dcb654-0d83-487b-8f11-ac51910f109c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2412735082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2412735082
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990672143
Short name T894
Test name
Test status
Simulation time 39593964 ps
CPU time 1.29 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:24 PM PDT 24
Peak memory 197548 kb
Host smart-be95ec50-5b46-447f-bfb3-ee1f63061e87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990672143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1990672143
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3272862516
Short name T909
Test name
Test status
Simulation time 54446284 ps
CPU time 1.04 seconds
Started Jun 26 04:35:06 PM PDT 24
Finished Jun 26 04:35:09 PM PDT 24
Peak memory 197476 kb
Host smart-75773dc0-bc47-43f3-a058-2a756302a111
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3272862516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3272862516
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2006876319
Short name T933
Test name
Test status
Simulation time 78437003 ps
CPU time 0.82 seconds
Started Jun 26 04:34:56 PM PDT 24
Finished Jun 26 04:35:01 PM PDT 24
Peak memory 195648 kb
Host smart-08205733-7880-46af-b528-54a6e8139909
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006876319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2006876319
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2718320641
Short name T842
Test name
Test status
Simulation time 54608678 ps
CPU time 1.19 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:35:27 PM PDT 24
Peak memory 198272 kb
Host smart-cec18dd1-bec5-4267-9fd6-4d40ea88bab5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2718320641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2718320641
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.414518845
Short name T907
Test name
Test status
Simulation time 84917166 ps
CPU time 1.17 seconds
Started Jun 26 04:35:10 PM PDT 24
Finished Jun 26 04:35:13 PM PDT 24
Peak memory 196236 kb
Host smart-58eada32-aed7-45cf-a309-9baeaae362f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414518845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.414518845
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1772409975
Short name T845
Test name
Test status
Simulation time 34991553 ps
CPU time 1.07 seconds
Started Jun 26 04:35:08 PM PDT 24
Finished Jun 26 04:35:10 PM PDT 24
Peak memory 196856 kb
Host smart-36ae4e33-aba8-4dfa-b1c1-a8bbf7e4a42f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1772409975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1772409975
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.616293240
Short name T850
Test name
Test status
Simulation time 54574030 ps
CPU time 1.16 seconds
Started Jun 26 04:35:26 PM PDT 24
Finished Jun 26 04:35:33 PM PDT 24
Peak memory 196072 kb
Host smart-33b10afd-1aa7-4ec9-8ca8-4e430af65451
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616293240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.616293240
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2013477861
Short name T893
Test name
Test status
Simulation time 33536697 ps
CPU time 0.97 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:23 PM PDT 24
Peak memory 195884 kb
Host smart-f4b27ae5-ca73-4828-9dbf-d2c022d1bc30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2013477861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2013477861
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4081086206
Short name T902
Test name
Test status
Simulation time 38105732 ps
CPU time 0.95 seconds
Started Jun 26 04:35:19 PM PDT 24
Finished Jun 26 04:35:24 PM PDT 24
Peak memory 196932 kb
Host smart-67c8bf36-a4bb-48d0-9547-f2d93dc00ceb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081086206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4081086206
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.852730950
Short name T899
Test name
Test status
Simulation time 37581086 ps
CPU time 1.33 seconds
Started Jun 26 04:35:16 PM PDT 24
Finished Jun 26 04:35:20 PM PDT 24
Peak memory 197184 kb
Host smart-b268f160-2079-4c5d-9984-235cfdb4c1f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=852730950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.852730950
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3243488378
Short name T856
Test name
Test status
Simulation time 49526255 ps
CPU time 1.38 seconds
Started Jun 26 04:35:08 PM PDT 24
Finished Jun 26 04:35:11 PM PDT 24
Peak memory 196996 kb
Host smart-03bf58e6-5c55-4c92-8bf6-345fc1602a83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243488378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3243488378
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2517970181
Short name T935
Test name
Test status
Simulation time 54168537 ps
CPU time 1.06 seconds
Started Jun 26 04:35:11 PM PDT 24
Finished Jun 26 04:35:13 PM PDT 24
Peak memory 198292 kb
Host smart-39a80dd3-f804-446b-b6ca-7431a1e21d48
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2517970181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2517970181
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2690259851
Short name T855
Test name
Test status
Simulation time 680666323 ps
CPU time 1.25 seconds
Started Jun 26 04:35:22 PM PDT 24
Finished Jun 26 04:35:29 PM PDT 24
Peak memory 196956 kb
Host smart-929874f8-1a25-4bed-9c31-0717595ac380
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690259851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2690259851
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2840329261
Short name T905
Test name
Test status
Simulation time 190467703 ps
CPU time 1.36 seconds
Started Jun 26 04:35:23 PM PDT 24
Finished Jun 26 04:35:31 PM PDT 24
Peak memory 196912 kb
Host smart-beebad06-8450-4de2-9adb-bb20b8963553
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2840329261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2840329261
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.926383821
Short name T864
Test name
Test status
Simulation time 82429648 ps
CPU time 1.16 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:35:19 PM PDT 24
Peak memory 197032 kb
Host smart-5ea339d9-2a32-4c06-873d-729561598c09
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926383821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.926383821
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1975062098
Short name T921
Test name
Test status
Simulation time 65581275 ps
CPU time 1.28 seconds
Started Jun 26 04:35:13 PM PDT 24
Finished Jun 26 04:35:16 PM PDT 24
Peak memory 197376 kb
Host smart-6ab46284-92b3-4b2e-81d1-2c37c993151e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1975062098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1975062098
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1787596140
Short name T844
Test name
Test status
Simulation time 98645721 ps
CPU time 0.98 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:28 PM PDT 24
Peak memory 196768 kb
Host smart-a1b3fadd-85c7-4a2d-af7a-e0e4ce901de6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787596140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1787596140
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.820897413
Short name T922
Test name
Test status
Simulation time 205220935 ps
CPU time 1.19 seconds
Started Jun 26 04:34:54 PM PDT 24
Finished Jun 26 04:35:00 PM PDT 24
Peak memory 196788 kb
Host smart-6f1a9cf3-02cc-4eab-beec-4ad6a8e8682b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=820897413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.820897413
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2683972090
Short name T927
Test name
Test status
Simulation time 66449646 ps
CPU time 1.02 seconds
Started Jun 26 04:35:13 PM PDT 24
Finished Jun 26 04:35:17 PM PDT 24
Peak memory 196964 kb
Host smart-ab180235-2f38-4121-8c90-cd98619ec9a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683972090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2683972090
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3193989578
Short name T898
Test name
Test status
Simulation time 345075242 ps
CPU time 1.22 seconds
Started Jun 26 04:35:16 PM PDT 24
Finished Jun 26 04:35:20 PM PDT 24
Peak memory 197132 kb
Host smart-5386f821-14a2-4a09-a903-df93fcc35c66
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3193989578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3193989578
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2417253712
Short name T839
Test name
Test status
Simulation time 146310900 ps
CPU time 1.17 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:35:26 PM PDT 24
Peak memory 196876 kb
Host smart-561ffce5-8b3d-4bc7-9fb2-95bac8873401
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417253712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2417253712
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1378110940
Short name T867
Test name
Test status
Simulation time 121876730 ps
CPU time 0.96 seconds
Started Jun 26 04:35:21 PM PDT 24
Finished Jun 26 04:35:28 PM PDT 24
Peak memory 196884 kb
Host smart-e9b60692-cd45-474d-89cf-4b97d9107e79
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1378110940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1378110940
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2936543872
Short name T925
Test name
Test status
Simulation time 105757156 ps
CPU time 1.25 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:35:19 PM PDT 24
Peak memory 198268 kb
Host smart-35706d5f-5e63-4323-a11e-b4d3a5527ef6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936543872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2936543872
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3499107827
Short name T924
Test name
Test status
Simulation time 89299801 ps
CPU time 1.58 seconds
Started Jun 26 04:35:33 PM PDT 24
Finished Jun 26 04:35:40 PM PDT 24
Peak memory 197228 kb
Host smart-3654f95a-029b-45f2-ba7f-b19bc4747359
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3499107827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3499107827
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3889388847
Short name T846
Test name
Test status
Simulation time 30150197 ps
CPU time 1.01 seconds
Started Jun 26 04:34:58 PM PDT 24
Finished Jun 26 04:35:03 PM PDT 24
Peak memory 196852 kb
Host smart-21d3b419-dc9f-43ed-a612-7b4ba8113f0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889388847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3889388847
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2410558873
Short name T886
Test name
Test status
Simulation time 1161525259 ps
CPU time 1.32 seconds
Started Jun 26 04:35:15 PM PDT 24
Finished Jun 26 04:35:20 PM PDT 24
Peak memory 196640 kb
Host smart-81834d6e-d314-48ae-8e4d-19ec7aa01236
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2410558873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2410558873
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3156140499
Short name T896
Test name
Test status
Simulation time 78206088 ps
CPU time 1.1 seconds
Started Jun 26 04:35:04 PM PDT 24
Finished Jun 26 04:35:07 PM PDT 24
Peak memory 196872 kb
Host smart-6808735d-e9fb-41b2-bd32-d5fb781b4892
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156140499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3156140499
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.122825336
Short name T847
Test name
Test status
Simulation time 104209464 ps
CPU time 1.1 seconds
Started Jun 26 04:35:10 PM PDT 24
Finished Jun 26 04:35:13 PM PDT 24
Peak memory 196892 kb
Host smart-98f24f8c-fdbc-4f88-b21c-9d56906803ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=122825336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.122825336
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1749901233
Short name T937
Test name
Test status
Simulation time 67278312 ps
CPU time 0.95 seconds
Started Jun 26 04:35:17 PM PDT 24
Finished Jun 26 04:35:23 PM PDT 24
Peak memory 196960 kb
Host smart-792a59f9-361d-434d-93f4-feabc45a5892
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749901233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1749901233
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1626902684
Short name T929
Test name
Test status
Simulation time 290267675 ps
CPU time 1.38 seconds
Started Jun 26 04:35:18 PM PDT 24
Finished Jun 26 04:35:25 PM PDT 24
Peak memory 197084 kb
Host smart-4107b37b-71b0-4f8a-930f-453c8ab16de1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1626902684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1626902684
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3983283982
Short name T860
Test name
Test status
Simulation time 35166784 ps
CPU time 0.95 seconds
Started Jun 26 04:35:21 PM PDT 24
Finished Jun 26 04:35:28 PM PDT 24
Peak memory 196732 kb
Host smart-6c1bef93-a20d-4a3f-ad14-239d184f328e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983283982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3983283982
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2460939074
Short name T882
Test name
Test status
Simulation time 41886424 ps
CPU time 1.15 seconds
Started Jun 26 04:35:05 PM PDT 24
Finished Jun 26 04:35:08 PM PDT 24
Peak memory 196220 kb
Host smart-a0e9fe97-c9c0-4eb6-a5db-71a4a56e8ea7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2460939074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2460939074
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.718656037
Short name T838
Test name
Test status
Simulation time 152047612 ps
CPU time 1.26 seconds
Started Jun 26 04:35:16 PM PDT 24
Finished Jun 26 04:35:21 PM PDT 24
Peak memory 197084 kb
Host smart-c9b69cd4-a95f-480e-892a-715cdd31b073
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718656037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.718656037
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1060149504
Short name T912
Test name
Test status
Simulation time 61011259 ps
CPU time 0.99 seconds
Started Jun 26 04:35:08 PM PDT 24
Finished Jun 26 04:35:10 PM PDT 24
Peak memory 196848 kb
Host smart-a87ce7ee-4e98-4ae3-a530-62a626aac039
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1060149504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1060149504
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1494296928
Short name T870
Test name
Test status
Simulation time 34049340 ps
CPU time 1.04 seconds
Started Jun 26 04:35:13 PM PDT 24
Finished Jun 26 04:35:17 PM PDT 24
Peak memory 196916 kb
Host smart-12b55a00-5733-4cae-80fa-bfc5833159f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494296928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1494296928
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.267949116
Short name T849
Test name
Test status
Simulation time 77928719 ps
CPU time 0.93 seconds
Started Jun 26 04:35:26 PM PDT 24
Finished Jun 26 04:35:33 PM PDT 24
Peak memory 196284 kb
Host smart-1dca6d4b-3c09-4c08-bf2d-b3c2a4334b5f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=267949116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.267949116
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3841481092
Short name T857
Test name
Test status
Simulation time 174354166 ps
CPU time 1.36 seconds
Started Jun 26 04:35:22 PM PDT 24
Finished Jun 26 04:35:30 PM PDT 24
Peak memory 198312 kb
Host smart-c2653f56-3e3e-47ce-bcad-831793e9fda3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841481092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3841481092
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4256907674
Short name T869
Test name
Test status
Simulation time 500329073 ps
CPU time 1.19 seconds
Started Jun 26 04:35:26 PM PDT 24
Finished Jun 26 04:35:33 PM PDT 24
Peak memory 197004 kb
Host smart-d238bcb4-ce3b-435b-8052-8537e5872844
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4256907674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4256907674
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39159688
Short name T879
Test name
Test status
Simulation time 35245208 ps
CPU time 0.83 seconds
Started Jun 26 04:35:20 PM PDT 24
Finished Jun 26 04:35:26 PM PDT 24
Peak memory 195684 kb
Host smart-03482368-48de-4f1e-aeb5-cdfa4f6aa3f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.39159688
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.463029480
Short name T868
Test name
Test status
Simulation time 205301412 ps
CPU time 1.02 seconds
Started Jun 26 04:35:12 PM PDT 24
Finished Jun 26 04:35:15 PM PDT 24
Peak memory 197668 kb
Host smart-f9ca403d-399e-4c71-8b1e-a316a95e5014
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=463029480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.463029480
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2726614474
Short name T910
Test name
Test status
Simulation time 65965275 ps
CPU time 1.16 seconds
Started Jun 26 04:34:52 PM PDT 24
Finished Jun 26 04:34:57 PM PDT 24
Peak memory 196812 kb
Host smart-74b07968-4bdf-45a6-bb1b-eb589a711d11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726614474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2726614474
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1535252851
Short name T917
Test name
Test status
Simulation time 39415660 ps
CPU time 1.14 seconds
Started Jun 26 04:35:07 PM PDT 24
Finished Jun 26 04:35:09 PM PDT 24
Peak memory 195936 kb
Host smart-720e9256-066d-4d40-8a78-64030b092998
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1535252851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1535252851
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2765828087
Short name T861
Test name
Test status
Simulation time 48790247 ps
CPU time 1.46 seconds
Started Jun 26 04:35:05 PM PDT 24
Finished Jun 26 04:35:09 PM PDT 24
Peak memory 197176 kb
Host smart-ae13cdfe-5c75-4d8f-8dff-50e39c5f78e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765828087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2765828087
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3139769776
Short name T884
Test name
Test status
Simulation time 90935904 ps
CPU time 1.31 seconds
Started Jun 26 04:34:52 PM PDT 24
Finished Jun 26 04:34:57 PM PDT 24
Peak memory 197136 kb
Host smart-e8dd6f14-4899-4c60-b840-519f9bdce276
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3139769776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3139769776
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1550403870
Short name T897
Test name
Test status
Simulation time 24445288 ps
CPU time 0.79 seconds
Started Jun 26 04:34:59 PM PDT 24
Finished Jun 26 04:35:04 PM PDT 24
Peak memory 195768 kb
Host smart-78c946a3-edb0-4a07-be18-6b26889dcf06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550403870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1550403870
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3409940628
Short name T881
Test name
Test status
Simulation time 249734775 ps
CPU time 0.97 seconds
Started Jun 26 04:35:07 PM PDT 24
Finished Jun 26 04:35:09 PM PDT 24
Peak memory 198300 kb
Host smart-383a6d35-edbb-4acd-a564-0d4e7b5fad04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3409940628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3409940628
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2010395725
Short name T876
Test name
Test status
Simulation time 126966005 ps
CPU time 1.08 seconds
Started Jun 26 04:34:55 PM PDT 24
Finished Jun 26 04:35:01 PM PDT 24
Peak memory 196924 kb
Host smart-d65f512d-c637-4596-ad7f-4fb233afb07b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010395725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2010395725
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1763206993
Short name T911
Test name
Test status
Simulation time 33509472 ps
CPU time 0.98 seconds
Started Jun 26 04:35:06 PM PDT 24
Finished Jun 26 04:35:08 PM PDT 24
Peak memory 196824 kb
Host smart-3cd3bade-f8e8-448c-8a27-c7d75016cb41
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1763206993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1763206993
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.895933305
Short name T853
Test name
Test status
Simulation time 272782688 ps
CPU time 1.21 seconds
Started Jun 26 04:35:01 PM PDT 24
Finished Jun 26 04:35:05 PM PDT 24
Peak memory 196828 kb
Host smart-3c5ad20e-79fc-49c5-9abf-28f8f8d421bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895933305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.895933305
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%