Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3618428	1			T21	11		T22	240		T23	19011
all_pins[1]	3618428	1			T21	11		T22	240		T23	19011
all_pins[2]	3618428	1			T21	11		T22	240		T23	19011
all_pins[3]	3618428	1			T21	11		T22	240		T23	19011
all_pins[4]	3618428	1			T21	11		T22	240		T23	19011
all_pins[5]	3618428	1			T21	11		T22	240		T23	19011
all_pins[6]	3618428	1			T21	11		T22	240		T23	19011
all_pins[7]	3618428	1			T21	11		T22	240		T23	19011
all_pins[8]	3618428	1			T21	11		T22	240		T23	19011
all_pins[9]	3618428	1			T21	11		T22	240		T23	19011
all_pins[10]	3618428	1			T21	11		T22	240		T23	19011
all_pins[11]	3618428	1			T21	11		T22	240		T23	19011
all_pins[12]	3618428	1			T21	11		T22	240		T23	19011
all_pins[13]	3618428	1			T21	11		T22	240		T23	19011
all_pins[14]	3618428	1			T21	11		T22	240		T23	19011
all_pins[15]	3618428	1			T21	11		T22	240		T23	19011
all_pins[16]	3618428	1			T21	11		T22	240		T23	19011
all_pins[17]	3618428	1			T21	11		T22	240		T23	19011
all_pins[18]	3618428	1			T21	11		T22	240		T23	19011
all_pins[19]	3618428	1			T21	11		T22	240		T23	19011
all_pins[20]	3618428	1			T21	11		T22	240		T23	19011
all_pins[21]	3618428	1			T21	11		T22	240		T23	19011
all_pins[22]	3618428	1			T21	11		T22	240		T23	19011
all_pins[23]	3618428	1			T21	11		T22	240		T23	19011
all_pins[24]	3618428	1			T21	11		T22	240		T23	19011
all_pins[25]	3618428	1			T21	11		T22	240		T23	19011
all_pins[26]	3618428	1			T21	11		T22	240		T23	19011
all_pins[27]	3618428	1			T21	11		T22	240		T23	19011
all_pins[28]	3618428	1			T21	11		T22	240		T23	19011
all_pins[29]	3618428	1			T21	11		T22	240		T23	19011
all_pins[30]	3618428	1			T21	11		T22	240		T23	19011
all_pins[31]	3618428	1			T21	11		T22	240		T23	19011

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	71925677	1			T21	352		T22	4599		T23	379942
values[0x1]	43864019	1			T22	3081		T23	228410		T1	316631
transitions[0x0=>0x1]	26280504	1			T22	1849		T23	136986		T1	189297
transitions[0x1=>0x0]	26280342	1			T22	1849		T23	136985		T1	189297

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2244897	1			T21	11		T22	92		T23	11861
all_pins[0]	values[0x1]	1373531	1			T22	148		T23	7150		T1	10035
all_pins[0]	transitions[0x0=>0x1]	851635	1			T22	118		T23	4378		T1	6113
all_pins[0]	transitions[0x1=>0x0]	845333	1			T22	35		T23	4300		T1	6044
all_pins[1]	values[0x0]	2249943	1			T21	11		T22	141		T23	11966
all_pins[1]	values[0x1]	1368485	1			T22	99		T23	7045		T1	9723
all_pins[1]	transitions[0x0=>0x1]	818152	1			T22	40		T23	4163		T1	5801
all_pins[1]	transitions[0x1=>0x0]	823198	1			T22	89		T23	4268		T1	6113
all_pins[2]	values[0x0]	2244032	1			T21	11		T22	160		T23	11620
all_pins[2]	values[0x1]	1374396	1			T22	80		T23	7391		T1	9979
all_pins[2]	transitions[0x0=>0x1]	824297	1			T22	51		T23	4506		T1	5915
all_pins[2]	transitions[0x1=>0x0]	818386	1			T22	70		T23	4160		T1	5659
all_pins[3]	values[0x0]	2249377	1			T21	11		T22	164		T23	11801
all_pins[3]	values[0x1]	1369051	1			T22	76		T23	7210		T1	9433
all_pins[3]	transitions[0x0=>0x1]	817899	1			T22	57		T23	4230		T1	5677
all_pins[3]	transitions[0x1=>0x0]	823244	1			T22	61		T23	4411		T1	6223
all_pins[4]	values[0x0]	2244926	1			T21	11		T22	101		T23	11838
all_pins[4]	values[0x1]	1373502	1			T22	139		T23	7173		T1	9447
all_pins[4]	transitions[0x0=>0x1]	822421	1			T22	87		T23	4194		T1	5833
all_pins[4]	transitions[0x1=>0x0]	817970	1			T22	24		T23	4231		T1	5819
all_pins[5]	values[0x0]	2249892	1			T21	11		T22	89		T23	12131
all_pins[5]	values[0x1]	1368536	1			T22	151		T23	6880		T1	9870
all_pins[5]	transitions[0x0=>0x1]	821589	1			T22	47		T23	4138		T1	6105
all_pins[5]	transitions[0x1=>0x0]	826555	1			T22	35		T23	4431		T1	5682
all_pins[6]	values[0x0]	2252822	1			T21	11		T22	178		T23	11780
all_pins[6]	values[0x1]	1365606	1			T22	62		T23	7231		T1	9985
all_pins[6]	transitions[0x0=>0x1]	817191	1			T22	4		T23	4424		T1	6120
all_pins[6]	transitions[0x1=>0x0]	820121	1			T22	93		T23	4073		T1	6005
all_pins[7]	values[0x0]	2243887	1			T21	11		T22	178		T23	11942
all_pins[7]	values[0x1]	1374541	1			T22	62		T23	7069		T1	10095
all_pins[7]	transitions[0x0=>0x1]	823182	1			T22	49		T23	4249		T1	5916
all_pins[7]	transitions[0x1=>0x0]	814247	1			T22	49		T23	4411		T1	5806
all_pins[8]	values[0x0]	2253779	1			T21	11		T22	149		T23	11675
all_pins[8]	values[0x1]	1364649	1			T22	91		T23	7336		T1	9976
all_pins[8]	transitions[0x0=>0x1]	815827	1			T22	79		T23	4288		T1	5989
all_pins[8]	transitions[0x1=>0x0]	825719	1			T22	50		T23	4021		T1	6108
all_pins[9]	values[0x0]	2251881	1			T21	11		T22	146		T23	12002
all_pins[9]	values[0x1]	1366547	1			T22	94		T23	7009		T1	8951
all_pins[9]	transitions[0x0=>0x1]	820784	1			T22	60		T23	4141		T1	5398
all_pins[9]	transitions[0x1=>0x0]	818886	1			T22	57		T23	4468		T1	6423
all_pins[10]	values[0x0]	2246530	1			T21	11		T22	156		T23	12115
all_pins[10]	values[0x1]	1371898	1			T22	84		T23	6896		T1	9897
all_pins[10]	transitions[0x0=>0x1]	822227	1			T22	53		T23	4140		T1	6219
all_pins[10]	transitions[0x1=>0x0]	816876	1			T22	63		T23	4253		T1	5273
all_pins[11]	values[0x0]	2250773	1			T21	11		T22	146		T23	11439
all_pins[11]	values[0x1]	1367655	1			T22	94		T23	7572		T1	9735
all_pins[11]	transitions[0x0=>0x1]	818750	1			T22	45		T23	4554		T1	5864
all_pins[11]	transitions[0x1=>0x0]	822993	1			T22	35		T23	3878		T1	6026
all_pins[12]	values[0x0]	2247968	1			T21	11		T22	135		T23	11874
all_pins[12]	values[0x1]	1370460	1			T22	105		T23	7137		T1	10303
all_pins[12]	transitions[0x0=>0x1]	821625	1			T22	65		T23	3971		T1	6202
all_pins[12]	transitions[0x1=>0x0]	818820	1			T22	54		T23	4406		T1	5634
all_pins[13]	values[0x0]	2251015	1			T21	11		T22	108		T23	11727
all_pins[13]	values[0x1]	1367413	1			T22	132		T23	7284		T1	9948
all_pins[13]	transitions[0x0=>0x1]	817928	1			T22	78		T23	4403		T1	5773
all_pins[13]	transitions[0x1=>0x0]	820975	1			T22	51		T23	4256		T1	6128
all_pins[14]	values[0x0]	2249290	1			T21	11		T22	176		T23	11924
all_pins[14]	values[0x1]	1369138	1			T22	64		T23	7087		T1	10095
all_pins[14]	transitions[0x0=>0x1]	820084	1			T22	51		T23	4163		T1	5963
all_pins[14]	transitions[0x1=>0x0]	818359	1			T22	119		T23	4360		T1	5816
all_pins[15]	values[0x0]	2243770	1			T21	11		T22	146		T23	11769
all_pins[15]	values[0x1]	1374658	1			T22	94		T23	7242		T1	9998
all_pins[15]	transitions[0x0=>0x1]	823510	1			T22	63		T23	4589		T1	5856
all_pins[15]	transitions[0x1=>0x0]	817990	1			T22	33		T23	4434		T1	5953
all_pins[16]	values[0x0]	2245251	1			T21	11		T22	179		T23	11618
all_pins[16]	values[0x1]	1373177	1			T22	61		T23	7393		T1	10153
all_pins[16]	transitions[0x0=>0x1]	819868	1			T22	30		T23	4335		T1	5970
all_pins[16]	transitions[0x1=>0x0]	821349	1			T22	63		T23	4184		T1	5815
all_pins[17]	values[0x0]	2252228	1			T21	11		T22	117		T23	12160
all_pins[17]	values[0x1]	1366200	1			T22	123		T23	6851		T1	10169
all_pins[17]	transitions[0x0=>0x1]	815344	1			T22	91		T23	4057		T1	5973
all_pins[17]	transitions[0x1=>0x0]	822321	1			T22	29		T23	4599		T1	5957
all_pins[18]	values[0x0]	2243872	1			T21	11		T22	139		T23	11780
all_pins[18]	values[0x1]	1374556	1			T22	101		T23	7231		T1	9887
all_pins[18]	transitions[0x0=>0x1]	822863	1			T22	26		T23	4486		T1	5874
all_pins[18]	transitions[0x1=>0x0]	814507	1			T22	48		T23	4106		T1	6156
all_pins[19]	values[0x0]	2244067	1			T21	11		T22	131		T23	11420
all_pins[19]	values[0x1]	1374361	1			T22	109		T23	7591		T1	9813
all_pins[19]	transitions[0x0=>0x1]	822442	1			T22	70		T23	4624		T1	6023
all_pins[19]	transitions[0x1=>0x0]	822637	1			T22	62		T23	4264		T1	6097
all_pins[20]	values[0x0]	2246285	1			T21	11		T22	91		T23	12018
all_pins[20]	values[0x1]	1372143	1			T22	149		T23	6993		T1	9660
all_pins[20]	transitions[0x0=>0x1]	820836	1			T22	91		T23	4077		T1	5979
all_pins[20]	transitions[0x1=>0x0]	823054	1			T22	51		T23	4675		T1	6132
all_pins[21]	values[0x0]	2247104	1			T21	11		T22	175		T23	12214
all_pins[21]	values[0x1]	1371324	1			T22	65		T23	6797		T1	10017
all_pins[21]	transitions[0x0=>0x1]	819746	1			T22	17		T23	4213		T1	6012
all_pins[21]	transitions[0x1=>0x0]	820565	1			T22	101		T23	4409		T1	5655
all_pins[22]	values[0x0]	2249466	1			T21	11		T22	138		T23	12038
all_pins[22]	values[0x1]	1368962	1			T22	102		T23	6973		T1	9763
all_pins[22]	transitions[0x0=>0x1]	818241	1			T22	62		T23	4380		T1	5664
all_pins[22]	transitions[0x1=>0x0]	820603	1			T22	25		T23	4204		T1	5918
all_pins[23]	values[0x0]	2248446	1			T21	11		T22	192		T23	11902
all_pins[23]	values[0x1]	1369982	1			T22	48		T23	7109		T1	10160
all_pins[23]	transitions[0x0=>0x1]	821089	1			T22	18		T23	4388		T1	6240
all_pins[23]	transitions[0x1=>0x0]	820069	1			T22	72		T23	4252		T1	5843
all_pins[24]	values[0x0]	2245666	1			T21	11		T22	108		T23	11866
all_pins[24]	values[0x1]	1372762	1			T22	132		T23	7145		T1	10212
all_pins[24]	transitions[0x0=>0x1]	820067	1			T22	101		T23	4304		T1	5947
all_pins[24]	transitions[0x1=>0x0]	817287	1			T22	17		T23	4268		T1	5895
all_pins[25]	values[0x0]	2246914	1			T21	11		T22	169		T23	12038
all_pins[25]	values[0x1]	1371514	1			T22	71		T23	6973		T1	10136
all_pins[25]	transitions[0x0=>0x1]	819902	1			T22	17		T23	4176		T1	5930
all_pins[25]	transitions[0x1=>0x0]	821150	1			T22	78		T23	4348		T1	6006
all_pins[26]	values[0x0]	2249257	1			T21	11		T22	158		T23	11506
all_pins[26]	values[0x1]	1369171	1			T22	82		T23	7505		T1	9940
all_pins[26]	transitions[0x0=>0x1]	821731	1			T22	64		T23	4630		T1	5685
all_pins[26]	transitions[0x1=>0x0]	824074	1			T22	53		T23	4098		T1	5881
all_pins[27]	values[0x0]	2252011	1			T21	11		T22	143		T23	11909
all_pins[27]	values[0x1]	1366417	1			T22	97		T23	7102		T1	9743
all_pins[27]	transitions[0x0=>0x1]	817778	1			T22	54		T23	3924		T1	5837
all_pins[27]	transitions[0x1=>0x0]	820532	1			T22	39		T23	4327		T1	6034
all_pins[28]	values[0x0]	2243175	1			T21	11		T22	166		T23	11546
all_pins[28]	values[0x1]	1375253	1			T22	74		T23	7465		T1	9599
all_pins[28]	transitions[0x0=>0x1]	825569	1			T22	63		T23	4419		T1	5844
all_pins[28]	transitions[0x1=>0x0]	816733	1			T22	86		T23	4056		T1	5988
all_pins[29]	values[0x0]	2239552	1			T21	11		T22	101		T23	12398
all_pins[29]	values[0x1]	1378876	1			T22	139		T23	6613		T1	10144
all_pins[29]	transitions[0x0=>0x1]	822159	1			T22	102		T23	3793		T1	6008
all_pins[29]	transitions[0x1=>0x0]	818536	1			T22	37		T23	4645		T1	5463
all_pins[30]	values[0x0]	2246564	1			T21	11		T22	152		T23	12127
all_pins[30]	values[0x1]	1371864	1			T22	88		T23	6884		T1	9799
all_pins[30]	transitions[0x0=>0x1]	818381	1			T22	34		T23	4380		T1	5676
all_pins[30]	transitions[0x1=>0x0]	825393	1			T22	85		T23	4109		T1	6021
all_pins[31]	values[0x0]	2251037	1			T21	11		T22	175		T23	11938
all_pins[31]	values[0x1]	1367391	1			T22	65		T23	7073		T1	9966
all_pins[31]	transitions[0x0=>0x1]	817387	1			T22	62		T23	4269		T1	5891
all_pins[31]	transitions[0x1=>0x0]	821860	1			T22	85		T23	4080		T1	5724