Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[1]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[2]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[3]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[4]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[5]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[6]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[7]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[8]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[9]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[10]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[11]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[12]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[13]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[14]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[15]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[16]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[17]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[18]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[19]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[20]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[21]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[22]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[23]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[24]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[25]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[26]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[27]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[28]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[29]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[30]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[31]	12316761	1			T21	11		T22	448		T23	56870

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234163370

1

T21

352

T22

7151

T23

595191

auto[1]

159972982

1

T22

7185

T23

122464

T1

183252

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

318003731

1

T21

352

T22

14336

T23

134454

auto[1]

76132621

1

T23

475296

T1

583647

T11

3327

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295737663

1

T21

352

T22

14336

T23

123345

auto[1]

98398689

1

T23

586381

T1

796854

T11

6652

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4604409	1			T21	11		T22	232		T23	10528
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3436349	1			T22	216		T23	20812		T1	33338
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1194711	1			T23	7566		T1	9175		T11	44
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1516899	1			T23	655		T1	1312		T11	158
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	379112	1			T23	9899		T1	14992		T11	17
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1185281	1			T23	7410		T1	9111		T11	67
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4602037	1			T21	11		T22	249		T23	10386
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3438857	1			T22	199		T23	20738		T1	33732
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1199747	1			T23	7140		T1	9284		T11	58
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1512685	1			T23	665		T1	1242		T11	128
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	376753	1			T23	10541		T1	14697		T11	20
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1186682	1			T23	7400		T1	8854		T11	26
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4607348	1			T21	11		T22	222		T23	10532
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3439744	1			T22	226		T23	21047		T1	34031
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1199630	1			T23	7569		T1	9295		T11	51
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1510138	1			T23	653		T1	1304		T11	146
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	373022	1			T23	10069		T1	13996		T11	18
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1186879	1			T23	7000		T1	9075		T11	23
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4609132	1			T21	11		T22	205		T23	10499
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3442178	1			T22	243		T23	20474		T1	34141
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1197047	1			T23	7751		T1	9682		T11	79
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1510537	1			T23	590		T1	1155		T11	120
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	375412	1			T23	10257		T1	13622		T11	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1182455	1			T23	7299		T1	9158		T11	47
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4606554	1			T21	11		T22	221		T23	10621
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3434181	1			T22	227		T23	20336		T1	33031
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1193341	1			T23	7457		T1	8917		T11	49
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1516056	1			T23	636		T1	1288		T11	102
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	380721	1			T23	10608		T1	15364		T11	14
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1185908	1			T23	7212		T1	9062		T11	37
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4608929	1			T21	11		T22	210		T23	10578
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3436076	1			T22	238		T23	20488		T1	33930
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1202460	1			T23	7515		T1	9101		T11	60
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1506179	1			T23	647		T1	1295		T11	152
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	377236	1			T23	10344		T1	14505		T11	19
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1185881	1			T23	7298		T1	9016		T11	42
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4591901	1			T21	11		T22	226		T23	10498
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3445754	1			T22	222		T23	20411		T1	33563
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1196321	1			T23	7724		T1	9092		T11	56
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1513385	1			T23	676		T1	1278		T11	142
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	378997	1			T23	10018		T1	14518		T11	23
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1190403	1			T23	7543		T1	9138		T11	45
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4615654	1			T21	11		T22	230		T23	10270
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3428786	1			T22	218		T23	20329		T1	33516
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1200119	1			T23	7610		T1	9325		T11	65
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1508172	1			T23	710		T1	1216		T11	126
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	376141	1			T23	10401		T1	14608		T11	18
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1187889	1			T23	7550		T1	8992		T11	65
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4612169	1			T21	11		T22	209		T23	10484
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3433494	1			T22	239		T23	20419		T1	33712
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1194582	1			T23	7348		T1	8965		T11	60
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1511777	1			T23	663		T1	1180		T11	147
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	377629	1			T23	10544		T1	14836		T11	22
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1187110	1			T23	7412		T1	8906		T11	23
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4607306	1			T21	11		T22	234		T23	10428
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3438607	1			T22	214		T23	20751		T1	32790
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1196523	1			T23	7439		T1	9077		T11	51
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1510459	1			T23	607		T1	1284		T11	198
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	377483	1			T23	10288		T1	15093		T11	15
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1186383	1			T23	7357		T1	9589		T11	50
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4602743	1			T21	11		T22	240		T23	10490
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3440892	1			T22	208		T23	20063		T1	33586
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1194149	1			T23	7566		T1	9024		T11	39
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1512411	1			T23	654		T1	1293		T11	139
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	378035	1			T23	10681		T1	14569		T11	13
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1188531	1			T23	7416		T1	9154		T11	66
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4601539	1			T21	11		T22	225		T23	10361
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3439531	1			T22	223		T23	20409		T1	33250
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1196868	1			T23	7063		T1	9424		T11	77
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1513282	1			T23	681		T1	1231		T11	136
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	377560	1			T23	10865		T1	14637		T11	13
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1187981	1			T23	7491		T1	8945		T11	47
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4595570	1			T21	11		T22	228		T23	10457
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3443991	1			T22	220		T23	20467		T1	33200
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1195886	1			T23	7890		T1	9052		T11	63
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1515895	1			T23	648		T1	1370		T11	125
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	379282	1			T23	10196		T1	15147		T11	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1186137	1			T23	7212		T1	9083		T11	64
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4603742	1			T21	11		T22	229		T23	10432
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3438851	1			T22	219		T23	20838		T1	33658
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1193501	1			T23	7235		T1	9290		T11	52
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1515822	1			T23	652		T1	1126		T11	187
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	374853	1			T23	10071		T1	14452		T11	29
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1189992	1			T23	7642		T1	8990		T11	70
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4602997	1			T21	11		T22	227		T23	10456
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3446477	1			T22	221		T23	20857		T1	33919
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1195251	1			T23	7593		T1	8917		T11	34
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1510788	1			T23	621		T1	1411		T11	149
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	374537	1			T23	9944		T1	14568		T11	11
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1186711	1			T23	7399		T1	9004		T11	51
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4600559	1			T21	11		T22	227		T23	10397
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3446375	1			T22	221		T23	20874		T1	33724
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1197619	1			T23	7523		T1	9096		T11	72
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1512028	1			T23	618		T1	1254		T11	117
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	377727	1			T23	10299		T1	14760		T11	8
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1182453	1			T23	7159		T1	8941		T11	42
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4624908	1			T21	11		T22	228		T23	10443
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3427152	1			T22	220		T23	21207		T1	33290
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1190750	1			T23	7394		T1	9091		T11	75
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1513456	1			T23	591		T1	1193		T11	114
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	379660	1			T23	10194		T1	15123		T11	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1180835	1			T23	7041		T1	8938		T11	16
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4606500	1			T21	11		T22	229		T23	10394
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3443752	1			T22	219		T23	20394		T1	33368
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1195590	1			T23	7296		T1	9238		T11	41
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1515564	1			T23	706		T1	1322		T11	192
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	375307	1			T23	10602		T1	14757		T11	15
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1180048	1			T23	7478		T1	8921		T11	60
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4603448	1			T21	11		T22	218		T23	10506
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3447843	1			T22	230		T23	20565		T1	33473
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1191175	1			T23	7828		T1	9356		T11	56
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1517661	1			T23	656		T1	1300		T11	143
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	375762	1			T23	10202		T1	14685		T11	18
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1180872	1			T23	7113		T1	8977		T11	86
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4607622	1			T21	11		T22	238		T23	10518
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3438573	1			T22	210		T23	20683		T1	33774
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1190401	1			T23	7503		T1	9451		T11	57
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1515873	1			T23	600		T1	1260		T11	132
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	376489	1			T23	10220		T1	14256		T11	15
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1187803	1			T23	7346		T1	8972		T11	29
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4613451	1			T21	11		T22	213		T23	10407
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3436617	1			T22	235		T23	20792		T1	34287
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1191913	1			T23	7379		T1	9308		T11	59
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1516395	1			T23	653		T1	1197		T11	161
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	376789	1			T23	10414		T1	14289		T11	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1181596	1			T23	7225		T1	8618		T11	78
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4617377	1			T21	11		T22	226		T23	10668
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3432781	1			T22	222		T23	20341		T1	33300
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1193643	1			T23	7120		T1	9096		T11	87
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1511445	1			T23	628		T1	1361		T11	86
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	379438	1			T23	10486		T1	14829		T11	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1182077	1			T23	7627		T1	9250		T11	42
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4609113	1			T21	11		T22	229		T23	10462
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3440351	1			T22	219		T23	20764		T1	33884
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1197476	1			T23	7587		T1	9071		T11	76
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1516811	1			T23	609		T1	1250		T11	163
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	373922	1			T23	10117		T1	14377		T11	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1179088	1			T23	7331		T1	8997		T11	53
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4617033	1			T21	11		T22	218		T23	10532
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3435522	1			T22	230		T23	20989		T1	33549
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1196523	1			T23	7517		T1	9015		T11	51
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1518002	1			T23	597		T1	1220		T11	171
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	373829	1			T23	10227		T1	14767		T11	14
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1175852	1			T23	7008		T1	9182		T11	62
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4620443	1			T21	11		T22	224		T23	10489
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3429764	1			T22	224		T23	20620		T1	33374
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1191015	1			T23	7688		T1	9265		T11	55
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1515534	1			T23	668		T1	1380		T11	155
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	377703	1			T23	10178		T1	14752		T11	21
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1182302	1			T23	7227		T1	9244		T11	37
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4605641	1			T21	11		T22	197		T23	10372
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3445178	1			T22	251		T23	20511		T1	33170
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1199813	1			T23	7719		T1	9186		T11	45
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1510297	1			T23	625		T1	1291		T11	152
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	375865	1			T23	10426		T1	14872		T11	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1179967	1			T23	7217		T1	9254		T11	53
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4602512	1			T21	11		T22	233		T23	10481
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3447156	1			T22	215		T23	19946		T1	33485
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1192342	1			T23	7434		T1	9457		T11	54
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1515742	1			T23	669		T1	1198		T11	135
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	376665	1			T23	10604		T1	14457		T11	5
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1182344	1			T23	7736		T1	9178		T11	26
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4618919	1			T21	11		T22	206		T23	10304
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3427158	1			T22	242		T23	20351		T1	33570
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1196831	1			T23	7574		T1	9429		T11	24
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1514620	1			T23	729		T1	1294		T11	162
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	378751	1			T23	10335		T1	14430		T11	24
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1180482	1			T23	7577		T1	9109		T11	52
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4611579	1			T21	11		T22	219		T23	10461
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3429597	1			T22	229		T23	20415		T1	34075
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1184096	1			T23	6945		T1	9106		T11	48
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1524281	1			T23	695		T1	1154		T11	188
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	378875	1			T23	10699		T1	14239		T11	26
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1188333	1			T23	7655		T1	9031		T11	51
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4611534	1			T21	11		T22	216		T23	10489
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3436397	1			T22	232		T23	20591		T1	34208
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1193225	1			T23	7609		T1	9225		T11	40
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1514689	1			T23	659		T1	1220		T11	149
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	376125	1			T23	10167		T1	14103		T11	15
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1184791	1			T23	7355		T1	8962		T11	55
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4622747	1			T21	11		T22	231		T23	10365
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3435021	1			T22	217		T23	20766		T1	33806
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1196561	1			T23	7938		T1	9003		T11	91
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1510114	1			T23	640		T1	1291		T11	88
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	374327	1			T23	10012		T1	14374		T11	9
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1177991	1			T23	7149		T1	9231		T11	33
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4617399	1			T21	11		T22	212		T23	10378
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3433778	1			T22	236		T23	20760		T1	34318
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1188956	1			T23	7245		T1	9229		T11	28
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1515493	1			T23	639		T1	1211		T11	147
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	377636	1			T23	10202		T1	14394		T11	15
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1183499	1			T23	7646		T1	8523		T11	32

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal