Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[1]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[2]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[3]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[4]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[5]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[6]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[7]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[8]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[9]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[10]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[11]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[12]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[13]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[14]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[15]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[16]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[17]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[18]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[19]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[20]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[21]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[22]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[23]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[24]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[25]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[26]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[27]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[28]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[29]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[30]	12316761	1			T21	11		T22	448		T23	56870
bins_for_gpio_bits[31]	12316761	1			T21	11		T22	448		T23	56870

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234163370

1

T21

352

T22

7151

T23

595191

auto[1]

159972982

1

T22

7185

T23

122464

T1

183252

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

234155571

1

T21

352

T22

7151

T23

595342

auto[1]

159980781

1

T22

7185

T23

122449

T1

183233

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7103877	1			T21	11		T22	232		T23	17421
bins_for_gpio_bits[0]	auto[0]	auto[1]	211953	1			T23	1335		T1	1605		T11	11
bins_for_gpio_bits[0]	auto[1]	auto[0]	212142	1			T23	1328		T1	1601		T11	11
bins_for_gpio_bits[0]	auto[1]	auto[1]	4788789	1			T22	216		T23	36786		T1	55836
bins_for_gpio_bits[1]	auto[0]	auto[0]	7102668	1			T21	11		T22	249		T23	16926
bins_for_gpio_bits[1]	auto[0]	auto[1]	211563	1			T23	1270		T1	1653		T11	3
bins_for_gpio_bits[1]	auto[1]	auto[0]	211801	1			T23	1265		T1	1645		T11	3
bins_for_gpio_bits[1]	auto[1]	auto[1]	4790729	1			T22	199		T23	37409		T1	55630
bins_for_gpio_bits[2]	auto[0]	auto[0]	7105064	1			T21	11		T22	222		T23	17471
bins_for_gpio_bits[2]	auto[0]	auto[1]	211882	1			T23	1287		T1	1608		T11	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	212052	1			T23	1283		T1	1602		T11	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	4787763	1			T22	226		T23	36829		T1	55494
bins_for_gpio_bits[3]	auto[0]	auto[0]	7104894	1			T21	11		T22	205		T23	17532
bins_for_gpio_bits[3]	auto[0]	auto[1]	211567	1			T23	1313		T1	1624		T11	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	211822	1			T23	1308		T1	1614		T11	11
bins_for_gpio_bits[3]	auto[1]	auto[1]	4788478	1			T22	243		T23	36717		T1	55297
bins_for_gpio_bits[4]	auto[0]	auto[0]	7104740	1			T21	11		T22	221		T23	17433
bins_for_gpio_bits[4]	auto[0]	auto[1]	210975	1			T23	1286		T1	1562		T11	6
bins_for_gpio_bits[4]	auto[1]	auto[0]	211211	1			T23	1281		T1	1558		T11	6
bins_for_gpio_bits[4]	auto[1]	auto[1]	4789835	1			T22	227		T23	36870		T1	55895
bins_for_gpio_bits[5]	auto[0]	auto[0]	7105653	1			T21	11		T22	210		T23	17453
bins_for_gpio_bits[5]	auto[0]	auto[1]	211659	1			T23	1292		T1	1602		T11	8
bins_for_gpio_bits[5]	auto[1]	auto[0]	211915	1			T23	1287		T1	1594		T11	8
bins_for_gpio_bits[5]	auto[1]	auto[1]	4787534	1			T22	238		T23	36838		T1	55849
bins_for_gpio_bits[6]	auto[0]	auto[0]	7089654	1			T21	11		T22	226		T23	17594
bins_for_gpio_bits[6]	auto[0]	auto[1]	211725	1			T23	1307		T1	1587		T11	10
bins_for_gpio_bits[6]	auto[1]	auto[0]	211953	1			T23	1304		T1	1583		T11	10
bins_for_gpio_bits[6]	auto[1]	auto[1]	4803429	1			T22	222		T23	36665		T1	55632
bins_for_gpio_bits[7]	auto[0]	auto[0]	7112143	1			T21	11		T22	230		T23	17282
bins_for_gpio_bits[7]	auto[0]	auto[1]	211563	1			T23	1315		T1	1604		T11	8
bins_for_gpio_bits[7]	auto[1]	auto[0]	211802	1			T23	1308		T1	1600		T11	9
bins_for_gpio_bits[7]	auto[1]	auto[1]	4781253	1			T22	218		T23	36965		T1	55512
bins_for_gpio_bits[8]	auto[0]	auto[0]	7107218	1			T21	11		T22	209		T23	17239
bins_for_gpio_bits[8]	auto[0]	auto[1]	211014	1			T23	1260		T1	1589		T11	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	211310	1			T23	1256		T1	1583		T11	6
bins_for_gpio_bits[8]	auto[1]	auto[1]	4787219	1			T22	239		T23	37115		T1	55865
bins_for_gpio_bits[9]	auto[0]	auto[0]	7102445	1			T21	11		T22	234		T23	17166
bins_for_gpio_bits[9]	auto[0]	auto[1]	211560	1			T23	1312		T1	1572		T11	9
bins_for_gpio_bits[9]	auto[1]	auto[0]	211843	1			T23	1308		T1	1562		T11	10
bins_for_gpio_bits[9]	auto[1]	auto[1]	4790913	1			T22	214		T23	37084		T1	55900
bins_for_gpio_bits[10]	auto[0]	auto[0]	7097315	1			T21	11		T22	240		T23	17392
bins_for_gpio_bits[10]	auto[0]	auto[1]	211753	1			T23	1321		T1	1568		T11	9
bins_for_gpio_bits[10]	auto[1]	auto[0]	211988	1			T23	1318		T1	1562		T11	10
bins_for_gpio_bits[10]	auto[1]	auto[1]	4795705	1			T22	208		T23	36839		T1	55741
bins_for_gpio_bits[11]	auto[0]	auto[0]	7099882	1			T21	11		T22	225		T23	16849
bins_for_gpio_bits[11]	auto[0]	auto[1]	211563	1			T23	1266		T1	1578		T11	8
bins_for_gpio_bits[11]	auto[1]	auto[0]	211807	1			T23	1256		T1	1574		T11	9
bins_for_gpio_bits[11]	auto[1]	auto[1]	4793509	1			T22	223		T23	37499		T1	55254
bins_for_gpio_bits[12]	auto[0]	auto[0]	7095805	1			T21	11		T22	228		T23	17666
bins_for_gpio_bits[12]	auto[0]	auto[1]	211353	1			T23	1334		T1	1549		T11	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	211546	1			T23	1329		T1	1543		T11	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	4798057	1			T22	220		T23	36541		T1	55881
bins_for_gpio_bits[13]	auto[0]	auto[0]	7101353	1			T21	11		T22	229		T23	17056
bins_for_gpio_bits[13]	auto[0]	auto[1]	211483	1			T23	1269		T1	1643		T11	9
bins_for_gpio_bits[13]	auto[1]	auto[0]	211712	1			T23	1263		T1	1639		T11	10
bins_for_gpio_bits[13]	auto[1]	auto[1]	4792213	1			T22	219		T23	37282		T1	55457
bins_for_gpio_bits[14]	auto[0]	auto[0]	7097115	1			T21	11		T22	227		T23	17346
bins_for_gpio_bits[14]	auto[0]	auto[1]	211656	1			T23	1327		T1	1562		T11	9
bins_for_gpio_bits[14]	auto[1]	auto[0]	211921	1			T23	1324		T1	1558		T11	9
bins_for_gpio_bits[14]	auto[1]	auto[1]	4796069	1			T22	221		T23	36873		T1	55929
bins_for_gpio_bits[15]	auto[0]	auto[0]	7098273	1			T21	11		T22	227		T23	17259
bins_for_gpio_bits[15]	auto[0]	auto[1]	211719	1			T23	1289		T1	1603		T11	9
bins_for_gpio_bits[15]	auto[1]	auto[0]	211933	1			T23	1279		T1	1594		T11	9
bins_for_gpio_bits[15]	auto[1]	auto[1]	4794836	1			T22	221		T23	37043		T1	55822
bins_for_gpio_bits[16]	auto[0]	auto[0]	7117541	1			T21	11		T22	228		T23	17118
bins_for_gpio_bits[16]	auto[0]	auto[1]	211349	1			T23	1317		T1	1603		T11	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	211573	1			T23	1310		T1	1598		T11	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	4776298	1			T22	220		T23	37125		T1	55748
bins_for_gpio_bits[17]	auto[0]	auto[0]	7105428	1			T21	11		T22	229		T23	17115
bins_for_gpio_bits[17]	auto[0]	auto[1]	211975	1			T23	1283		T1	1635		T11	10
bins_for_gpio_bits[17]	auto[1]	auto[0]	212226	1			T23	1281		T1	1624		T11	11
bins_for_gpio_bits[17]	auto[1]	auto[1]	4787132	1			T22	219		T23	37191		T1	55411
bins_for_gpio_bits[18]	auto[0]	auto[0]	7100583	1			T21	11		T22	218		T23	17661
bins_for_gpio_bits[18]	auto[0]	auto[1]	211460	1			T23	1334		T1	1588		T11	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	211701	1			T23	1329		T1	1580		T11	13
bins_for_gpio_bits[18]	auto[1]	auto[1]	4793017	1			T22	230		T23	36546		T1	55547
bins_for_gpio_bits[19]	auto[0]	auto[0]	7101770	1			T21	11		T22	238		T23	17326
bins_for_gpio_bits[19]	auto[0]	auto[1]	211871	1			T23	1301		T1	1599		T11	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	212126	1			T23	1295		T1	1594		T11	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	4790994	1			T22	210		T23	36948		T1	55403
bins_for_gpio_bits[20]	auto[0]	auto[0]	7109791	1			T21	11		T22	213		T23	17130
bins_for_gpio_bits[20]	auto[0]	auto[1]	211744	1			T23	1313		T1	1630		T11	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	211968	1			T23	1309		T1	1621		T11	13
bins_for_gpio_bits[20]	auto[1]	auto[1]	4783258	1			T22	235		T23	37118		T1	55564
bins_for_gpio_bits[21]	auto[0]	auto[0]	7110503	1			T21	11		T22	226		T23	17111
bins_for_gpio_bits[21]	auto[0]	auto[1]	211663	1			T23	1309		T1	1623		T11	7
bins_for_gpio_bits[21]	auto[1]	auto[0]	211962	1			T23	1305		T1	1618		T11	7
bins_for_gpio_bits[21]	auto[1]	auto[1]	4782633	1			T22	222		T23	37145		T1	55756
bins_for_gpio_bits[22]	auto[0]	auto[0]	7111314	1			T21	11		T22	229		T23	17307
bins_for_gpio_bits[22]	auto[0]	auto[1]	211836	1			T23	1356		T1	1632		T11	14
bins_for_gpio_bits[22]	auto[1]	auto[0]	212086	1			T23	1351		T1	1625		T11	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	4781525	1			T22	219		T23	36856		T1	55626
bins_for_gpio_bits[23]	auto[0]	auto[0]	7119659	1			T21	11		T22	218		T23	17344
bins_for_gpio_bits[23]	auto[0]	auto[1]	211628	1			T23	1305		T1	1597		T11	9
bins_for_gpio_bits[23]	auto[1]	auto[0]	211899	1			T23	1302		T1	1588		T11	9
bins_for_gpio_bits[23]	auto[1]	auto[1]	4773575	1			T22	230		T23	36919		T1	55901
bins_for_gpio_bits[24]	auto[0]	auto[0]	7115607	1			T21	11		T22	224		T23	17521
bins_for_gpio_bits[24]	auto[0]	auto[1]	211116	1			T23	1328		T1	1595		T11	7
bins_for_gpio_bits[24]	auto[1]	auto[0]	211385	1			T23	1324		T1	1591		T11	7
bins_for_gpio_bits[24]	auto[1]	auto[1]	4778653	1			T22	224		T23	36697		T1	55775
bins_for_gpio_bits[25]	auto[0]	auto[0]	7103941	1			T21	11		T22	197		T23	17397
bins_for_gpio_bits[25]	auto[0]	auto[1]	211553	1			T23	1323		T1	1617		T11	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	211810	1			T23	1319		T1	1610		T11	9
bins_for_gpio_bits[25]	auto[1]	auto[1]	4789457	1			T22	251		T23	36831		T1	55679
bins_for_gpio_bits[26]	auto[0]	auto[0]	7098598	1			T21	11		T22	233		T23	17273
bins_for_gpio_bits[26]	auto[0]	auto[1]	211722	1			T23	1313		T1	1621		T11	9
bins_for_gpio_bits[26]	auto[1]	auto[0]	211998	1			T23	1311		T1	1616		T11	9
bins_for_gpio_bits[26]	auto[1]	auto[1]	4794443	1			T22	215		T23	36973		T1	55499
bins_for_gpio_bits[27]	auto[0]	auto[0]	7118649	1			T21	11		T22	206		T23	17313
bins_for_gpio_bits[27]	auto[0]	auto[1]	211450	1			T23	1297		T1	1599		T11	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	211721	1			T23	1294		T1	1595		T11	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	4774941	1			T22	242		T23	36966		T1	55510
bins_for_gpio_bits[28]	auto[0]	auto[0]	7108071	1			T21	11		T22	219		T23	16879
bins_for_gpio_bits[28]	auto[0]	auto[1]	211659	1			T23	1227		T1	1635		T11	10
bins_for_gpio_bits[28]	auto[1]	auto[0]	211885	1			T23	1222		T1	1631		T11	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	4785146	1			T22	229		T23	37542		T1	55710
bins_for_gpio_bits[29]	auto[0]	auto[0]	7107788	1			T21	11		T22	216		T23	17420
bins_for_gpio_bits[29]	auto[0]	auto[1]	211428	1			T23	1340		T1	1647		T11	8
bins_for_gpio_bits[29]	auto[1]	auto[0]	211660	1			T23	1337		T1	1643		T11	8
bins_for_gpio_bits[29]	auto[1]	auto[1]	4785885	1			T22	232		T23	36773		T1	55626
bins_for_gpio_bits[30]	auto[0]	auto[0]	7117603	1			T21	11		T22	231		T23	17629
bins_for_gpio_bits[30]	auto[0]	auto[1]	211554	1			T23	1315		T1	1595		T11	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	211819	1			T23	1314		T1	1591		T11	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	4775785	1			T22	217		T23	36612		T1	55816
bins_for_gpio_bits[31]	auto[0]	auto[0]	7110134	1			T21	11		T22	212		T23	16987
bins_for_gpio_bits[31]	auto[0]	auto[1]	211496	1			T23	1282		T1	1641		T11	8
bins_for_gpio_bits[31]	auto[1]	auto[0]	211714	1			T23	1275		T1	1635		T11	8
bins_for_gpio_bits[31]	auto[1]	auto[1]	4783417	1			T22	236		T23	37326		T1	55594