Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7333223 |
1 |
|
|
T21 |
1 |
|
T22 |
122 |
|
T23 |
33231 |
| auto[1] |
5186353 |
1 |
|
|
T22 |
453 |
|
T23 |
24939 |
|
T1 |
39120 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11854164 |
1 |
|
|
T21 |
1 |
|
T22 |
492 |
|
T23 |
55429 |
| auto[1] |
665412 |
1 |
|
|
T22 |
83 |
|
T23 |
2741 |
|
T1 |
4934 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7321362 |
1 |
|
|
T21 |
1 |
|
T22 |
198 |
|
T23 |
32440 |
| auto[1] |
5198214 |
1 |
|
|
T22 |
377 |
|
T23 |
25730 |
|
T1 |
38154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2258871 |
1 |
|
|
T22 |
59 |
|
T23 |
12009 |
|
T1 |
16196 |
| auto[1] |
auto[0] |
auto[1] |
331329 |
1 |
|
|
T22 |
19 |
|
T23 |
1439 |
|
T1 |
2390 |
| auto[1] |
auto[1] |
auto[0] |
2273931 |
1 |
|
|
T22 |
235 |
|
T23 |
10980 |
|
T1 |
17024 |
| auto[1] |
auto[1] |
auto[1] |
334083 |
1 |
|
|
T22 |
64 |
|
T23 |
1302 |
|
T1 |
2544 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7360352 |
1 |
|
|
T21 |
1 |
|
T22 |
262 |
|
T23 |
33009 |
| auto[1] |
5159224 |
1 |
|
|
T22 |
313 |
|
T23 |
25161 |
|
T1 |
38766 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11854080 |
1 |
|
|
T21 |
1 |
|
T22 |
518 |
|
T23 |
55163 |
| auto[1] |
665496 |
1 |
|
|
T22 |
57 |
|
T23 |
3007 |
|
T1 |
5283 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7322828 |
1 |
|
|
T21 |
1 |
|
T22 |
301 |
|
T23 |
30959 |
| auto[1] |
5196748 |
1 |
|
|
T22 |
274 |
|
T23 |
27211 |
|
T1 |
40184 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2268353 |
1 |
|
|
T22 |
88 |
|
T23 |
12492 |
|
T1 |
17364 |
| auto[1] |
auto[0] |
auto[1] |
333097 |
1 |
|
|
T22 |
22 |
|
T23 |
1683 |
|
T1 |
2584 |
| auto[1] |
auto[1] |
auto[0] |
2262899 |
1 |
|
|
T22 |
129 |
|
T23 |
11712 |
|
T1 |
17537 |
| auto[1] |
auto[1] |
auto[1] |
332399 |
1 |
|
|
T22 |
35 |
|
T23 |
1324 |
|
T1 |
2699 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7341126 |
1 |
|
|
T21 |
1 |
|
T22 |
336 |
|
T23 |
33240 |
| auto[1] |
5178450 |
1 |
|
|
T22 |
239 |
|
T23 |
24930 |
|
T1 |
39064 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11862042 |
1 |
|
|
T21 |
1 |
|
T22 |
488 |
|
T23 |
55511 |
| auto[1] |
657534 |
1 |
|
|
T22 |
87 |
|
T23 |
2659 |
|
T1 |
5288 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371479 |
1 |
|
|
T21 |
1 |
|
T22 |
136 |
|
T23 |
32472 |
| auto[1] |
5148097 |
1 |
|
|
T22 |
439 |
|
T23 |
25698 |
|
T1 |
39703 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2229505 |
1 |
|
|
T22 |
193 |
|
T23 |
11880 |
|
T1 |
16699 |
| auto[1] |
auto[0] |
auto[1] |
325059 |
1 |
|
|
T22 |
48 |
|
T23 |
1376 |
|
T1 |
2551 |
| auto[1] |
auto[1] |
auto[0] |
2261058 |
1 |
|
|
T22 |
159 |
|
T23 |
11159 |
|
T1 |
17716 |
| auto[1] |
auto[1] |
auto[1] |
332475 |
1 |
|
|
T22 |
39 |
|
T23 |
1283 |
|
T1 |
2737 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7366890 |
1 |
|
|
T21 |
1 |
|
T22 |
267 |
|
T23 |
30612 |
| auto[1] |
5152686 |
1 |
|
|
T22 |
308 |
|
T23 |
27558 |
|
T1 |
38068 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11854376 |
1 |
|
|
T21 |
1 |
|
T22 |
512 |
|
T23 |
55162 |
| auto[1] |
665200 |
1 |
|
|
T22 |
63 |
|
T23 |
3008 |
|
T1 |
5307 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7323456 |
1 |
|
|
T21 |
1 |
|
T22 |
293 |
|
T23 |
30918 |
| auto[1] |
5196120 |
1 |
|
|
T22 |
282 |
|
T23 |
27252 |
|
T1 |
40641 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2277601 |
1 |
|
|
T22 |
137 |
|
T23 |
11012 |
|
T1 |
18072 |
| auto[1] |
auto[0] |
auto[1] |
334520 |
1 |
|
|
T22 |
42 |
|
T23 |
1327 |
|
T1 |
2757 |
| auto[1] |
auto[1] |
auto[0] |
2253319 |
1 |
|
|
T22 |
82 |
|
T23 |
13232 |
|
T1 |
17262 |
| auto[1] |
auto[1] |
auto[1] |
330680 |
1 |
|
|
T22 |
21 |
|
T23 |
1681 |
|
T1 |
2550 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7346665 |
1 |
|
|
T21 |
1 |
|
T22 |
284 |
|
T23 |
32635 |
| auto[1] |
5172911 |
1 |
|
|
T22 |
291 |
|
T23 |
25535 |
|
T1 |
39416 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11858663 |
1 |
|
|
T21 |
1 |
|
T22 |
512 |
|
T23 |
55503 |
| auto[1] |
660913 |
1 |
|
|
T22 |
63 |
|
T23 |
2667 |
|
T1 |
5111 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7338602 |
1 |
|
|
T21 |
1 |
|
T22 |
266 |
|
T23 |
32532 |
| auto[1] |
5180974 |
1 |
|
|
T22 |
309 |
|
T23 |
25638 |
|
T1 |
38686 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2262572 |
1 |
|
|
T22 |
105 |
|
T23 |
11638 |
|
T1 |
16395 |
| auto[1] |
auto[0] |
auto[1] |
330210 |
1 |
|
|
T22 |
25 |
|
T23 |
1358 |
|
T1 |
2472 |
| auto[1] |
auto[1] |
auto[0] |
2257489 |
1 |
|
|
T22 |
141 |
|
T23 |
11333 |
|
T1 |
17180 |
| auto[1] |
auto[1] |
auto[1] |
330703 |
1 |
|
|
T22 |
38 |
|
T23 |
1309 |
|
T1 |
2639 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7360793 |
1 |
|
|
T21 |
1 |
|
T22 |
188 |
|
T23 |
31555 |
| auto[1] |
5158783 |
1 |
|
|
T22 |
387 |
|
T23 |
26615 |
|
T1 |
39441 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11862184 |
1 |
|
|
T21 |
1 |
|
T22 |
515 |
|
T23 |
55387 |
| auto[1] |
657392 |
1 |
|
|
T22 |
60 |
|
T23 |
2783 |
|
T1 |
4657 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7368845 |
1 |
|
|
T21 |
1 |
|
T22 |
224 |
|
T23 |
32125 |
| auto[1] |
5150731 |
1 |
|
|
T22 |
351 |
|
T23 |
26045 |
|
T1 |
36399 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2260759 |
1 |
|
|
T22 |
105 |
|
T23 |
11012 |
|
T1 |
16196 |
| auto[1] |
auto[0] |
auto[1] |
331917 |
1 |
|
|
T22 |
24 |
|
T23 |
1278 |
|
T1 |
2459 |
| auto[1] |
auto[1] |
auto[0] |
2232580 |
1 |
|
|
T22 |
186 |
|
T23 |
12250 |
|
T1 |
15546 |
| auto[1] |
auto[1] |
auto[1] |
325475 |
1 |
|
|
T22 |
36 |
|
T23 |
1505 |
|
T1 |
2198 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7383404 |
1 |
|
|
T21 |
1 |
|
T22 |
309 |
|
T23 |
32897 |
| auto[1] |
5136172 |
1 |
|
|
T22 |
266 |
|
T23 |
25273 |
|
T1 |
38823 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11857377 |
1 |
|
|
T21 |
1 |
|
T22 |
526 |
|
T23 |
55316 |
| auto[1] |
662199 |
1 |
|
|
T22 |
49 |
|
T23 |
2854 |
|
T1 |
5420 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7336337 |
1 |
|
|
T21 |
1 |
|
T22 |
329 |
|
T23 |
31832 |
| auto[1] |
5183239 |
1 |
|
|
T22 |
246 |
|
T23 |
26338 |
|
T1 |
41051 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2275453 |
1 |
|
|
T22 |
137 |
|
T23 |
12177 |
|
T1 |
17502 |
| auto[1] |
auto[0] |
auto[1] |
332912 |
1 |
|
|
T22 |
37 |
|
T23 |
1481 |
|
T1 |
2633 |
| auto[1] |
auto[1] |
auto[0] |
2245587 |
1 |
|
|
T22 |
60 |
|
T23 |
11307 |
|
T1 |
18129 |
| auto[1] |
auto[1] |
auto[1] |
329287 |
1 |
|
|
T22 |
12 |
|
T23 |
1373 |
|
T1 |
2787 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7317072 |
1 |
|
|
T21 |
1 |
|
T22 |
285 |
|
T23 |
30946 |
| auto[1] |
5202504 |
1 |
|
|
T22 |
290 |
|
T23 |
27224 |
|
T1 |
39304 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11857842 |
1 |
|
|
T21 |
1 |
|
T22 |
516 |
|
T23 |
55315 |
| auto[1] |
661734 |
1 |
|
|
T22 |
59 |
|
T23 |
2855 |
|
T1 |
5180 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7338559 |
1 |
|
|
T21 |
1 |
|
T22 |
287 |
|
T23 |
32008 |
| auto[1] |
5181017 |
1 |
|
|
T22 |
288 |
|
T23 |
26162 |
|
T1 |
39638 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2251614 |
1 |
|
|
T22 |
100 |
|
T23 |
11123 |
|
T1 |
17093 |
| auto[1] |
auto[0] |
auto[1] |
329496 |
1 |
|
|
T22 |
22 |
|
T23 |
1327 |
|
T1 |
2602 |
| auto[1] |
auto[1] |
auto[0] |
2267669 |
1 |
|
|
T22 |
129 |
|
T23 |
12184 |
|
T1 |
17365 |
| auto[1] |
auto[1] |
auto[1] |
332238 |
1 |
|
|
T22 |
37 |
|
T23 |
1528 |
|
T1 |
2578 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7347241 |
1 |
|
|
T21 |
1 |
|
T22 |
370 |
|
T23 |
32028 |
| auto[1] |
5172335 |
1 |
|
|
T22 |
205 |
|
T23 |
26142 |
|
T1 |
38260 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11859724 |
1 |
|
|
T21 |
1 |
|
T22 |
534 |
|
T23 |
55445 |
| auto[1] |
659852 |
1 |
|
|
T22 |
41 |
|
T23 |
2725 |
|
T1 |
5128 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7345816 |
1 |
|
|
T21 |
1 |
|
T22 |
330 |
|
T23 |
32648 |
| auto[1] |
5173760 |
1 |
|
|
T22 |
245 |
|
T23 |
25522 |
|
T1 |
38873 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2249235 |
1 |
|
|
T22 |
104 |
|
T23 |
10865 |
|
T1 |
17450 |
| auto[1] |
auto[0] |
auto[1] |
328646 |
1 |
|
|
T22 |
19 |
|
T23 |
1324 |
|
T1 |
2729 |
| auto[1] |
auto[1] |
auto[0] |
2264673 |
1 |
|
|
T22 |
100 |
|
T23 |
11932 |
|
T1 |
16295 |
| auto[1] |
auto[1] |
auto[1] |
331206 |
1 |
|
|
T22 |
22 |
|
T23 |
1401 |
|
T1 |
2399 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371882 |
1 |
|
|
T21 |
1 |
|
T22 |
191 |
|
T23 |
33282 |
| auto[1] |
5147694 |
1 |
|
|
T22 |
384 |
|
T23 |
24888 |
|
T1 |
39484 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11857900 |
1 |
|
|
T21 |
1 |
|
T22 |
537 |
|
T23 |
55665 |
| auto[1] |
661676 |
1 |
|
|
T22 |
38 |
|
T23 |
2505 |
|
T1 |
5098 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7336494 |
1 |
|
|
T21 |
1 |
|
T22 |
395 |
|
T23 |
34017 |
| auto[1] |
5183082 |
1 |
|
|
T22 |
180 |
|
T23 |
24153 |
|
T1 |
38477 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2276664 |
1 |
|
|
T22 |
21 |
|
T23 |
11323 |
|
T1 |
15677 |
| auto[1] |
auto[0] |
auto[1] |
333294 |
1 |
|
|
T22 |
6 |
|
T23 |
1359 |
|
T1 |
2298 |
| auto[1] |
auto[1] |
auto[0] |
2244742 |
1 |
|
|
T22 |
121 |
|
T23 |
10325 |
|
T1 |
17702 |
| auto[1] |
auto[1] |
auto[1] |
328382 |
1 |
|
|
T22 |
32 |
|
T23 |
1146 |
|
T1 |
2800 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7339675 |
1 |
|
|
T21 |
1 |
|
T22 |
247 |
|
T23 |
32489 |
| auto[1] |
5179901 |
1 |
|
|
T22 |
328 |
|
T23 |
25681 |
|
T1 |
37184 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11861886 |
1 |
|
|
T21 |
1 |
|
T22 |
521 |
|
T23 |
55324 |
| auto[1] |
657690 |
1 |
|
|
T22 |
54 |
|
T23 |
2846 |
|
T1 |
4861 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7371699 |
1 |
|
|
T21 |
1 |
|
T22 |
287 |
|
T23 |
31742 |
| auto[1] |
5147877 |
1 |
|
|
T22 |
288 |
|
T23 |
26428 |
|
T1 |
37487 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2243129 |
1 |
|
|
T22 |
124 |
|
T23 |
12336 |
|
T1 |
16534 |
| auto[1] |
auto[0] |
auto[1] |
329089 |
1 |
|
|
T22 |
24 |
|
T23 |
1557 |
|
T1 |
2441 |
| auto[1] |
auto[1] |
auto[0] |
2247058 |
1 |
|
|
T22 |
110 |
|
T23 |
11246 |
|
T1 |
16092 |
| auto[1] |
auto[1] |
auto[1] |
328601 |
1 |
|
|
T22 |
30 |
|
T23 |
1289 |
|
T1 |
2420 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7386522 |
1 |
|
|
T21 |
1 |
|
T22 |
295 |
|
T23 |
31228 |
| auto[1] |
5133054 |
1 |
|
|
T22 |
280 |
|
T23 |
26942 |
|
T1 |
37005 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11861723 |
1 |
|
|
T21 |
1 |
|
T22 |
517 |
|
T23 |
55452 |
| auto[1] |
657853 |
1 |
|
|
T22 |
58 |
|
T23 |
2718 |
|
T1 |
4861 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7356956 |
1 |
|
|
T21 |
1 |
|
T22 |
266 |
|
T23 |
33132 |
| auto[1] |
5162620 |
1 |
|
|
T22 |
309 |
|
T23 |
25038 |
|
T1 |
38064 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2278635 |
1 |
|
|
T22 |
124 |
|
T23 |
10702 |
|
T1 |
16935 |
| auto[1] |
auto[0] |
auto[1] |
333033 |
1 |
|
|
T22 |
29 |
|
T23 |
1263 |
|
T1 |
2409 |
| auto[1] |
auto[1] |
auto[0] |
2226132 |
1 |
|
|
T22 |
127 |
|
T23 |
11618 |
|
T1 |
16268 |
| auto[1] |
auto[1] |
auto[1] |
324820 |
1 |
|
|
T22 |
29 |
|
T23 |
1455 |
|
T1 |
2452 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7366938 |
1 |
|
|
T21 |
1 |
|
T22 |
279 |
|
T23 |
31648 |
| auto[1] |
5152638 |
1 |
|
|
T22 |
296 |
|
T23 |
26522 |
|
T1 |
37813 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11862168 |
1 |
|
|
T21 |
1 |
|
T22 |
501 |
|
T23 |
55271 |
| auto[1] |
657408 |
1 |
|
|
T22 |
74 |
|
T23 |
2899 |
|
T1 |
4838 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7362387 |
1 |
|
|
T21 |
1 |
|
T22 |
180 |
|
T23 |
31300 |
| auto[1] |
5157189 |
1 |
|
|
T22 |
395 |
|
T23 |
26870 |
|
T1 |
37792 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2260306 |
1 |
|
|
T22 |
176 |
|
T23 |
12335 |
|
T1 |
16414 |
| auto[1] |
auto[0] |
auto[1] |
330423 |
1 |
|
|
T22 |
40 |
|
T23 |
1455 |
|
T1 |
2382 |
| auto[1] |
auto[1] |
auto[0] |
2239475 |
1 |
|
|
T22 |
145 |
|
T23 |
11636 |
|
T1 |
16540 |
| auto[1] |
auto[1] |
auto[1] |
326985 |
1 |
|
|
T22 |
34 |
|
T23 |
1444 |
|
T1 |
2456 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7342638 |
1 |
|
|
T21 |
1 |
|
T22 |
156 |
|
T23 |
31666 |
| auto[1] |
5176938 |
1 |
|
|
T22 |
419 |
|
T23 |
26504 |
|
T1 |
37297 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11857302 |
1 |
|
|
T21 |
1 |
|
T22 |
494 |
|
T23 |
55469 |
| auto[1] |
662274 |
1 |
|
|
T22 |
81 |
|
T23 |
2701 |
|
T1 |
5124 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7333761 |
1 |
|
|
T21 |
1 |
|
T22 |
188 |
|
T23 |
32600 |
| auto[1] |
5185815 |
1 |
|
|
T22 |
387 |
|
T23 |
25570 |
|
T1 |
37869 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2254641 |
1 |
|
|
T22 |
47 |
|
T23 |
11105 |
|
T1 |
17134 |
| auto[1] |
auto[0] |
auto[1] |
329752 |
1 |
|
|
T22 |
7 |
|
T23 |
1234 |
|
T1 |
2774 |
| auto[1] |
auto[1] |
auto[0] |
2268900 |
1 |
|
|
T22 |
259 |
|
T23 |
11764 |
|
T1 |
15611 |
| auto[1] |
auto[1] |
auto[1] |
332522 |
1 |
|
|
T22 |
74 |
|
T23 |
1467 |
|
T1 |
2350 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7348794 |
1 |
|
|
T21 |
1 |
|
T22 |
388 |
|
T23 |
33652 |
| auto[1] |
5170782 |
1 |
|
|
T22 |
187 |
|
T23 |
24518 |
|
T1 |
39155 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11858590 |
1 |
|
|
T21 |
1 |
|
T22 |
516 |
|
T23 |
55547 |
| auto[1] |
660986 |
1 |
|
|
T22 |
59 |
|
T23 |
2623 |
|
T1 |
5257 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7345401 |
1 |
|
|
T21 |
1 |
|
T22 |
283 |
|
T23 |
34026 |
| auto[1] |
5174175 |
1 |
|
|
T22 |
292 |
|
T23 |
24144 |
|
T1 |
39141 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2252956 |
1 |
|
|
T22 |
161 |
|
T23 |
11408 |
|
T1 |
17025 |
| auto[1] |
auto[0] |
auto[1] |
329357 |
1 |
|
|
T22 |
37 |
|
T23 |
1416 |
|
T1 |
2566 |
| auto[1] |
auto[1] |
auto[0] |
2260233 |
1 |
|
|
T22 |
72 |
|
T23 |
10113 |
|
T1 |
16859 |
| auto[1] |
auto[1] |
auto[1] |
331629 |
1 |
|
|
T22 |
22 |
|
T23 |
1207 |
|
T1 |
2691 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7365733 |
1 |
|
|
T21 |
1 |
|
T22 |
272 |
|
T23 |
32480 |
| auto[1] |
5153843 |
1 |
|
|
T22 |
303 |
|
T23 |
25690 |
|
T1 |
38256 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11852496 |
1 |
|
|
T21 |
1 |
|
T22 |
518 |
|
T23 |
55352 |
| auto[1] |
667080 |
1 |
|
|
T22 |
57 |
|
T23 |
2818 |
|
T1 |
5177 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7319723 |
1 |
|
|
T21 |
1 |
|
T22 |
306 |
|
T23 |
31601 |
| auto[1] |
5199853 |
1 |
|
|
T22 |
269 |
|
T23 |
26569 |
|
T1 |
39445 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2267455 |
1 |
|
|
T22 |
93 |
|
T23 |
11647 |
|
T1 |
17002 |
| auto[1] |
auto[0] |
auto[1] |
334036 |
1 |
|
|
T22 |
25 |
|
T23 |
1398 |
|
T1 |
2594 |
| auto[1] |
auto[1] |
auto[0] |
2265318 |
1 |
|
|
T22 |
119 |
|
T23 |
12104 |
|
T1 |
17266 |
| auto[1] |
auto[1] |
auto[1] |
333044 |
1 |
|
|
T22 |
32 |
|
T23 |
1420 |
|
T1 |
2583 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7362326 |
1 |
|
|
T21 |
1 |
|
T22 |
415 |
|
T23 |
32921 |
| auto[1] |
5157250 |
1 |
|
|
T22 |
160 |
|
T23 |
25249 |
|
T1 |
39760 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11857983 |
1 |
|
|
T21 |
1 |
|
T22 |
551 |
|
T23 |
55334 |
| auto[1] |
661593 |
1 |
|
|
T22 |
24 |
|
T23 |
2836 |
|
T1 |
5177 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7338850 |
1 |
|
|
T21 |
1 |
|
T22 |
454 |
|
T23 |
32390 |
| auto[1] |
5180726 |
1 |
|
|
T22 |
121 |
|
T23 |
25780 |
|
T1 |
39553 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2257562 |
1 |
|
|
T22 |
63 |
|
T23 |
12154 |
|
T1 |
16738 |
| auto[1] |
auto[0] |
auto[1] |
330173 |
1 |
|
|
T22 |
17 |
|
T23 |
1558 |
|
T1 |
2502 |
| auto[1] |
auto[1] |
auto[0] |
2261571 |
1 |
|
|
T22 |
34 |
|
T23 |
10790 |
|
T1 |
17638 |
| auto[1] |
auto[1] |
auto[1] |
331420 |
1 |
|
|
T22 |
7 |
|
T23 |
1278 |
|
T1 |
2675 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7344080 |
1 |
|
|
T21 |
1 |
|
T22 |
170 |
|
T23 |
33195 |
| auto[1] |
5175496 |
1 |
|
|
T22 |
405 |
|
T23 |
24975 |
|
T1 |
39854 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11853695 |
1 |
|
|
T21 |
1 |
|
T22 |
519 |
|
T23 |
55514 |
| auto[1] |
665881 |
1 |
|
|
T22 |
56 |
|
T23 |
2656 |
|
T1 |
5341 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7313816 |
1 |
|
|
T21 |
1 |
|
T22 |
296 |
|
T23 |
32167 |
| auto[1] |
5205760 |
1 |
|
|
T22 |
279 |
|
T23 |
26003 |
|
T1 |
40230 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2271795 |
1 |
|
|
T22 |
73 |
|
T23 |
12229 |
|
T1 |
17019 |
| auto[1] |
auto[0] |
auto[1] |
331946 |
1 |
|
|
T22 |
19 |
|
T23 |
1339 |
|
T1 |
2583 |
| auto[1] |
auto[1] |
auto[0] |
2268084 |
1 |
|
|
T22 |
150 |
|
T23 |
11118 |
|
T1 |
17870 |
| auto[1] |
auto[1] |
auto[1] |
333935 |
1 |
|
|
T22 |
37 |
|
T23 |
1317 |
|
T1 |
2758 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7383258 |
1 |
|
|
T21 |
1 |
|
T22 |
292 |
|
T23 |
31822 |
| auto[1] |
5136318 |
1 |
|
|
T22 |
283 |
|
T23 |
26348 |
|
T1 |
39474 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11858034 |
1 |
|
|
T21 |
1 |
|
T22 |
482 |
|
T23 |
55470 |
| auto[1] |
661542 |
1 |
|
|
T22 |
93 |
|
T23 |
2700 |
|
T1 |
4907 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7341005 |
1 |
|
|
T21 |
1 |
|
T22 |
77 |
|
T23 |
32146 |
| auto[1] |
5178571 |
1 |
|
|
T22 |
498 |
|
T23 |
26024 |
|
T1 |
38497 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2272685 |
1 |
|
|
T22 |
211 |
|
T23 |
11335 |
|
T1 |
16190 |
| auto[1] |
auto[0] |
auto[1] |
332941 |
1 |
|
|
T22 |
49 |
|
T23 |
1274 |
|
T1 |
2302 |
| auto[1] |
auto[1] |
auto[0] |
2244344 |
1 |
|
|
T22 |
194 |
|
T23 |
11989 |
|
T1 |
17400 |
| auto[1] |
auto[1] |
auto[1] |
328601 |
1 |
|
|
T22 |
44 |
|
T23 |
1426 |
|
T1 |
2605 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7386688 |
1 |
|
|
T21 |
1 |
|
T22 |
341 |
|
T23 |
30958 |
| auto[1] |
5132888 |
1 |
|
|
T22 |
234 |
|
T23 |
27212 |
|
T1 |
39235 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11860196 |
1 |
|
|
T21 |
1 |
|
T22 |
544 |
|
T23 |
55513 |
| auto[1] |
659380 |
1 |
|
|
T22 |
31 |
|
T23 |
2657 |
|
T1 |
4873 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7365394 |
1 |
|
|
T21 |
1 |
|
T22 |
390 |
|
T23 |
33459 |
| auto[1] |
5154182 |
1 |
|
|
T22 |
185 |
|
T23 |
24711 |
|
T1 |
36892 |