Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7381402 |
1 |
|
|
T21 |
1 |
|
T22 |
288 |
|
T23 |
32054 |
| auto[1] |
5138174 |
1 |
|
|
T22 |
287 |
|
T23 |
26116 |
|
T1 |
39055 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11860853 |
1 |
|
|
T21 |
1 |
|
T22 |
526 |
|
T23 |
55221 |
| auto[1] |
658723 |
1 |
|
|
T22 |
49 |
|
T23 |
2949 |
|
T1 |
5072 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7360126 |
1 |
|
|
T21 |
1 |
|
T22 |
303 |
|
T23 |
31066 |
| auto[1] |
5159450 |
1 |
|
|
T22 |
272 |
|
T23 |
27104 |
|
T1 |
39149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2265355 |
1 |
|
|
T22 |
145 |
|
T23 |
12376 |
|
T1 |
16676 |
| auto[1] |
auto[0] |
auto[1] |
332318 |
1 |
|
|
T22 |
29 |
|
T23 |
1518 |
|
T1 |
2482 |
| auto[1] |
auto[1] |
auto[0] |
2235372 |
1 |
|
|
T22 |
78 |
|
T23 |
11779 |
|
T1 |
17401 |
| auto[1] |
auto[1] |
auto[1] |
326405 |
1 |
|
|
T22 |
20 |
|
T23 |
1431 |
|
T1 |
2590 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |