Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7366890 |
1 |
|
|
T21 |
1 |
|
T22 |
267 |
|
T23 |
30612 |
| auto[1] |
5152686 |
1 |
|
|
T22 |
308 |
|
T23 |
27558 |
|
T1 |
38068 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10388933 |
1 |
|
|
T21 |
1 |
|
T22 |
419 |
|
T23 |
41831 |
| auto[1] |
2130643 |
1 |
|
|
T22 |
156 |
|
T23 |
16339 |
|
T1 |
22188 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7339178 |
1 |
|
|
T21 |
1 |
|
T22 |
272 |
|
T23 |
32980 |
| auto[1] |
5180398 |
1 |
|
|
T22 |
303 |
|
T23 |
25190 |
|
T1 |
36773 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1526327 |
1 |
|
|
T22 |
40 |
|
T23 |
4177 |
|
T1 |
7344 |
| auto[1] |
auto[0] |
auto[1] |
1063127 |
1 |
|
|
T22 |
57 |
|
T23 |
7887 |
|
T1 |
11217 |
| auto[1] |
auto[1] |
auto[0] |
1523428 |
1 |
|
|
T22 |
107 |
|
T23 |
4674 |
|
T1 |
7241 |
| auto[1] |
auto[1] |
auto[1] |
1067516 |
1 |
|
|
T22 |
99 |
|
T23 |
8452 |
|
T1 |
10971 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |